root/drivers/tty/moxa.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef MOXA_H_FILE
   3 #define MOXA_H_FILE
   4 
   5 #define MOXA            0x400
   6 #define MOXA_GET_IQUEUE         (MOXA + 1)      /* get input buffered count */
   7 #define MOXA_GET_OQUEUE         (MOXA + 2)      /* get output buffered count */
   8 #define MOXA_GETDATACOUNT       (MOXA + 23)
   9 #define MOXA_GET_IOQUEUE        (MOXA + 27)
  10 #define MOXA_FLUSH_QUEUE        (MOXA + 28)
  11 #define MOXA_GETMSTATUS         (MOXA + 65)
  12 
  13 /*
  14  *    System Configuration
  15  */
  16 
  17 #define Magic_code      0x404
  18 
  19 /*
  20  *    for C218 BIOS initialization
  21  */
  22 #define C218_ConfBase   0x800
  23 #define C218_status     (C218_ConfBase + 0)     /* BIOS running status    */
  24 #define C218_diag       (C218_ConfBase + 2)     /* diagnostic status      */
  25 #define C218_key        (C218_ConfBase + 4)     /* WORD (0x218 for C218) */
  26 #define C218DLoad_len   (C218_ConfBase + 6)     /* WORD           */
  27 #define C218check_sum   (C218_ConfBase + 8)     /* BYTE           */
  28 #define C218chksum_ok   (C218_ConfBase + 0x0a)  /* BYTE (1:ok)            */
  29 #define C218_TestRx     (C218_ConfBase + 0x10)  /* 8 bytes for 8 ports    */
  30 #define C218_TestTx     (C218_ConfBase + 0x18)  /* 8 bytes for 8 ports    */
  31 #define C218_RXerr      (C218_ConfBase + 0x20)  /* 8 bytes for 8 ports    */
  32 #define C218_ErrFlag    (C218_ConfBase + 0x28)  /* 8 bytes for 8 ports    */
  33 
  34 #define C218_LoadBuf    0x0F00
  35 #define C218_KeyCode    0x218
  36 #define CP204J_KeyCode  0x204
  37 
  38 /*
  39  *    for C320 BIOS initialization
  40  */
  41 #define C320_ConfBase   0x800
  42 #define C320_LoadBuf    0x0f00
  43 #define STS_init        0x05    /* for C320_status        */
  44 
  45 #define C320_status     C320_ConfBase + 0       /* BIOS running status    */
  46 #define C320_diag       C320_ConfBase + 2       /* diagnostic status      */
  47 #define C320_key        C320_ConfBase + 4       /* WORD (0320H for C320) */
  48 #define C320DLoad_len   C320_ConfBase + 6       /* WORD           */
  49 #define C320check_sum   C320_ConfBase + 8       /* WORD           */
  50 #define C320chksum_ok   C320_ConfBase + 0x0a    /* WORD (1:ok)            */
  51 #define C320bapi_len    C320_ConfBase + 0x0c    /* WORD           */
  52 #define C320UART_no     C320_ConfBase + 0x0e    /* WORD           */
  53 
  54 #define C320_KeyCode    0x320
  55 
  56 #define FixPage_addr    0x0000  /* starting addr of static page  */
  57 #define DynPage_addr    0x2000  /* starting addr of dynamic page */
  58 #define C218_start      0x3000  /* starting addr of C218 BIOS prg */
  59 #define Control_reg     0x1ff0  /* select page and reset control */
  60 #define HW_reset        0x80
  61 
  62 /*
  63  *    Function Codes
  64  */
  65 #define FC_CardReset    0x80
  66 #define FC_ChannelReset 1       /* C320 firmware not supported */
  67 #define FC_EnableCH     2
  68 #define FC_DisableCH    3
  69 #define FC_SetParam     4
  70 #define FC_SetMode      5
  71 #define FC_SetRate      6
  72 #define FC_LineControl  7
  73 #define FC_LineStatus   8
  74 #define FC_XmitControl  9
  75 #define FC_FlushQueue   10
  76 #define FC_SendBreak    11
  77 #define FC_StopBreak    12
  78 #define FC_LoopbackON   13
  79 #define FC_LoopbackOFF  14
  80 #define FC_ClrIrqTable  15
  81 #define FC_SendXon      16
  82 #define FC_SetTermIrq   17      /* C320 firmware not supported */
  83 #define FC_SetCntIrq    18      /* C320 firmware not supported */
  84 #define FC_SetBreakIrq  19
  85 #define FC_SetLineIrq   20
  86 #define FC_SetFlowCtl   21
  87 #define FC_GenIrq       22
  88 #define FC_InCD180      23
  89 #define FC_OutCD180     24
  90 #define FC_InUARTreg    23
  91 #define FC_OutUARTreg   24
  92 #define FC_SetXonXoff   25
  93 #define FC_OutCD180CCR  26
  94 #define FC_ExtIQueue    27
  95 #define FC_ExtOQueue    28
  96 #define FC_ClrLineIrq   29
  97 #define FC_HWFlowCtl    30
  98 #define FC_GetClockRate 35
  99 #define FC_SetBaud      36
 100 #define FC_SetDataMode  41
 101 #define FC_GetCCSR      43
 102 #define FC_GetDataError 45
 103 #define FC_RxControl    50
 104 #define FC_ImmSend      51
 105 #define FC_SetXonState  52
 106 #define FC_SetXoffState 53
 107 #define FC_SetRxFIFOTrig 54
 108 #define FC_SetTxFIFOCnt 55
 109 #define FC_UnixRate     56
 110 #define FC_UnixResetTimer 57
 111 
 112 #define RxFIFOTrig1     0
 113 #define RxFIFOTrig4     1
 114 #define RxFIFOTrig8     2
 115 #define RxFIFOTrig14    3
 116 
 117 /*
 118  *    Dual-Ported RAM
 119  */
 120 #define DRAM_global     0
 121 #define INT_data        (DRAM_global + 0)
 122 #define Config_base     (DRAM_global + 0x108)
 123 
 124 #define IRQindex        (INT_data + 0)
 125 #define IRQpending      (INT_data + 4)
 126 #define IRQtable        (INT_data + 8)
 127 
 128 /*
 129  *    Interrupt Status
 130  */
 131 #define IntrRx          0x01    /* receiver data O.K.             */
 132 #define IntrTx          0x02    /* transmit buffer empty  */
 133 #define IntrFunc        0x04    /* function complete              */
 134 #define IntrBreak       0x08    /* received break         */
 135 #define IntrLine        0x10    /* line status change
 136                                    for transmitter                */
 137 #define IntrIntr        0x20    /* received INTR code             */
 138 #define IntrQuit        0x40    /* received QUIT code             */
 139 #define IntrEOF         0x80    /* received EOF code              */
 140 
 141 #define IntrRxTrigger   0x100   /* rx data count reach tigger value */
 142 #define IntrTxTrigger   0x200   /* tx data count below trigger value */
 143 
 144 #define Magic_no        (Config_base + 0)
 145 #define Card_model_no   (Config_base + 2)
 146 #define Total_ports     (Config_base + 4)
 147 #define Module_cnt      (Config_base + 8)
 148 #define Module_no       (Config_base + 10)
 149 #define Timer_10ms      (Config_base + 14)
 150 #define Disable_IRQ     (Config_base + 20)
 151 #define TMS320_PORT1    (Config_base + 22)
 152 #define TMS320_PORT2    (Config_base + 24)
 153 #define TMS320_CLOCK    (Config_base + 26)
 154 
 155 /*
 156  *    DATA BUFFER in DRAM
 157  */
 158 #define Extern_table    0x400   /* Base address of the external table
 159                                    (24 words *    64) total 3K bytes
 160                                    (24 words * 128) total 6K bytes */
 161 #define Extern_size     0x60    /* 96 bytes                       */
 162 #define RXrptr          0x00    /* read pointer for RX buffer     */
 163 #define RXwptr          0x02    /* write pointer for RX buffer    */
 164 #define TXrptr          0x04    /* read pointer for TX buffer     */
 165 #define TXwptr          0x06    /* write pointer for TX buffer    */
 166 #define HostStat        0x08    /* IRQ flag and general flag      */
 167 #define FlagStat        0x0A
 168 #define FlowControl     0x0C    /* B7 B6 B5 B4 B3 B2 B1 B0              */
 169                                 /*  x  x  x  x  |  |  |  |            */
 170                                 /*              |  |  |  + CTS flow   */
 171                                 /*              |  |  +--- RTS flow   */
 172                                 /*              |  +------ TX Xon/Xoff */
 173                                 /*              +--------- RX Xon/Xoff */
 174 #define Break_cnt       0x0E    /* received break count   */
 175 #define CD180TXirq      0x10    /* if non-0: enable TX irq        */
 176 #define RX_mask         0x12
 177 #define TX_mask         0x14
 178 #define Ofs_rxb         0x16
 179 #define Ofs_txb         0x18
 180 #define Page_rxb        0x1A
 181 #define Page_txb        0x1C
 182 #define EndPage_rxb     0x1E
 183 #define EndPage_txb     0x20
 184 #define Data_error      0x22
 185 #define RxTrigger       0x28
 186 #define TxTrigger       0x2a
 187 
 188 #define rRXwptr         0x34
 189 #define Low_water       0x36
 190 
 191 #define FuncCode        0x40
 192 #define FuncArg         0x42
 193 #define FuncArg1        0x44
 194 
 195 #define C218rx_size     0x2000  /* 8K bytes */
 196 #define C218tx_size     0x8000  /* 32K bytes */
 197 
 198 #define C218rx_mask     (C218rx_size - 1)
 199 #define C218tx_mask     (C218tx_size - 1)
 200 
 201 #define C320p8rx_size   0x2000
 202 #define C320p8tx_size   0x8000
 203 #define C320p8rx_mask   (C320p8rx_size - 1)
 204 #define C320p8tx_mask   (C320p8tx_size - 1)
 205 
 206 #define C320p16rx_size  0x2000
 207 #define C320p16tx_size  0x4000
 208 #define C320p16rx_mask  (C320p16rx_size - 1)
 209 #define C320p16tx_mask  (C320p16tx_size - 1)
 210 
 211 #define C320p24rx_size  0x2000
 212 #define C320p24tx_size  0x2000
 213 #define C320p24rx_mask  (C320p24rx_size - 1)
 214 #define C320p24tx_mask  (C320p24tx_size - 1)
 215 
 216 #define C320p32rx_size  0x1000
 217 #define C320p32tx_size  0x1000
 218 #define C320p32rx_mask  (C320p32rx_size - 1)
 219 #define C320p32tx_mask  (C320p32tx_size - 1)
 220 
 221 #define Page_size       0x2000U
 222 #define Page_mask       (Page_size - 1)
 223 #define C218rx_spage    3
 224 #define C218tx_spage    4
 225 #define C218rx_pageno   1
 226 #define C218tx_pageno   4
 227 #define C218buf_pageno  5
 228 
 229 #define C320p8rx_spage  3
 230 #define C320p8tx_spage  4
 231 #define C320p8rx_pgno   1
 232 #define C320p8tx_pgno   4
 233 #define C320p8buf_pgno  5
 234 
 235 #define C320p16rx_spage 3
 236 #define C320p16tx_spage 4
 237 #define C320p16rx_pgno  1
 238 #define C320p16tx_pgno  2
 239 #define C320p16buf_pgno 3
 240 
 241 #define C320p24rx_spage 3
 242 #define C320p24tx_spage 4
 243 #define C320p24rx_pgno  1
 244 #define C320p24tx_pgno  1
 245 #define C320p24buf_pgno 2
 246 
 247 #define C320p32rx_spage 3
 248 #define C320p32tx_ofs   C320p32rx_size
 249 #define C320p32tx_spage 3
 250 #define C320p32buf_pgno 1
 251 
 252 /*
 253  *    Host Status
 254  */
 255 #define WakeupRx        0x01
 256 #define WakeupTx        0x02
 257 #define WakeupBreak     0x08
 258 #define WakeupLine      0x10
 259 #define WakeupIntr      0x20
 260 #define WakeupQuit      0x40
 261 #define WakeupEOF       0x80    /* used in VTIME control */
 262 #define WakeupRxTrigger 0x100
 263 #define WakeupTxTrigger 0x200
 264 /*
 265  *    Flag status
 266  */
 267 #define Rx_over         0x01
 268 #define Xoff_state      0x02
 269 #define Tx_flowOff      0x04
 270 #define Tx_enable       0x08
 271 #define CTS_state       0x10
 272 #define DSR_state       0x20
 273 #define DCD_state       0x80
 274 /*
 275  *    FlowControl
 276  */
 277 #define CTS_FlowCtl     1
 278 #define RTS_FlowCtl     2
 279 #define Tx_FlowCtl      4
 280 #define Rx_FlowCtl      8
 281 #define IXM_IXANY       0x10
 282 
 283 #define LowWater        128
 284 
 285 #define DTR_ON          1
 286 #define RTS_ON          2
 287 #define CTS_ON          1
 288 #define DSR_ON          2
 289 #define DCD_ON          8
 290 
 291 /* mode definition */
 292 #define MX_CS8          0x03
 293 #define MX_CS7          0x02
 294 #define MX_CS6          0x01
 295 #define MX_CS5          0x00
 296 
 297 #define MX_STOP1        0x00
 298 #define MX_STOP15       0x04
 299 #define MX_STOP2        0x08
 300 
 301 #define MX_PARNONE      0x00
 302 #define MX_PAREVEN      0x40
 303 #define MX_PARODD       0xC0
 304 #define MX_PARMARK      0xA0
 305 #define MX_PARSPACE     0x20
 306 
 307 #endif