This source file includes following definitions.
- get_ross_icr
- put_ross_icr
- hyper_flush_whole_icache
- hyper_clear_all_tags
- hyper_flush_unconditional_combined
- hyper_flush_cache_user
- hyper_flush_cache_page
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8 #ifndef _SPARC_ROSS_H
9 #define _SPARC_ROSS_H
10
11 #include <asm/asi.h>
12 #include <asm/page.h>
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44 #define HYPERSPARC_CWENABLE 0x00200000
45 #define HYPERSPARC_SBENABLE 0x00100000
46 #define HYPERSPARC_WBENABLE 0x00080000
47 #define HYPERSPARC_MIDMASK 0x00078000
48 #define HYPERSPARC_BMODE 0x00004000
49 #define HYPERSPARC_ACENABLE 0x00002000
50 #define HYPERSPARC_CSIZE 0x00001000
51 #define HYPERSPARC_MRFLCT 0x00000800
52 #define HYPERSPARC_CMODE 0x00000400
53 #define HYPERSPARC_CENABLE 0x00000100
54 #define HYPERSPARC_NFAULT 0x00000002
55 #define HYPERSPARC_MENABLE 0x00000001
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95 #define HYPERSPARC_ICCR_FTD 0x00000002
96 #define HYPERSPARC_ICCR_ICE 0x00000001
97
98 #ifndef __ASSEMBLY__
99
100 static inline unsigned int get_ross_icr(void)
101 {
102 unsigned int icreg;
103
104 __asm__ __volatile__(".word 0x8347c000\n\t"
105 "mov %%g1, %0\n\t"
106 : "=r" (icreg)
107 :
108 : "g1", "memory");
109
110 return icreg;
111 }
112
113 static inline void put_ross_icr(unsigned int icreg)
114 {
115 __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
116 ".word 0xbf806000\n\t"
117 "nop\n\t"
118 "nop\n\t"
119 "nop\n\t"
120 :
121 : "r" (icreg)
122 : "g1", "memory");
123
124 return;
125 }
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129
130 static inline void hyper_flush_whole_icache(void)
131 {
132 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
133 :
134 : "i" (ASI_M_FLUSH_IWHOLE)
135 : "memory");
136 return;
137 }
138
139 extern int vac_cache_size;
140 extern int vac_line_size;
141
142 static inline void hyper_clear_all_tags(void)
143 {
144 unsigned long addr;
145
146 for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
147 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
148 :
149 : "r" (addr), "i" (ASI_M_DATAC_TAG)
150 : "memory");
151 }
152
153 static inline void hyper_flush_unconditional_combined(void)
154 {
155 unsigned long addr;
156
157 for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
158 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
159 :
160 : "r" (addr), "i" (ASI_M_FLUSH_CTX)
161 : "memory");
162 }
163
164 static inline void hyper_flush_cache_user(void)
165 {
166 unsigned long addr;
167
168 for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
169 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
170 :
171 : "r" (addr), "i" (ASI_M_FLUSH_USER)
172 : "memory");
173 }
174
175 static inline void hyper_flush_cache_page(unsigned long page)
176 {
177 unsigned long end;
178
179 page &= PAGE_MASK;
180 end = page + PAGE_SIZE;
181 while (page < end) {
182 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
183 :
184 : "r" (page), "i" (ASI_M_FLUSH_PAGE)
185 : "memory");
186 page += vac_line_size;
187 }
188 }
189
190 #endif
191
192 #endif