This source file includes following definitions.
- ltq_vrx200_pcie_phy_common_setup
- pcie_phy_36mhz_mode_setup
- ltq_vrx200_pcie_phy_wait_for_pll
- ltq_vrx200_pcie_phy_apply_workarounds
- ltq_vrx200_pcie_phy_init
- ltq_vrx200_pcie_phy_exit
- ltq_vrx200_pcie_phy_power_on
- ltq_vrx200_pcie_phy_power_off
- ltq_vrx200_pcie_phy_xlate
- ltq_vrx200_pcie_phy_probe
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14 #include <linux/bitfield.h>
15 #include <linux/bits.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26
27 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
28
29 #define PCIE_PHY_PLL_CTRL1 0x44
30
31 #define PCIE_PHY_PLL_CTRL2 0x46
32 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)
33 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN BIT(8)
34 #define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN BIT(9)
35
36 #define PCIE_PHY_PLL_CTRL3 0x48
37 #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN BIT(1)
38 #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK GENMASK(6, 4)
39
40 #define PCIE_PHY_PLL_CTRL4 0x4a
41 #define PCIE_PHY_PLL_CTRL5 0x4c
42 #define PCIE_PHY_PLL_CTRL6 0x4e
43 #define PCIE_PHY_PLL_CTRL7 0x50
44 #define PCIE_PHY_PLL_A_CTRL1 0x52
45
46 #define PCIE_PHY_PLL_A_CTRL2 0x54
47 #define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN BIT(14)
48
49 #define PCIE_PHY_PLL_A_CTRL3 0x56
50 #define PCIE_PHY_PLL_A_CTRL3_MMD_MASK GENMASK(15, 13)
51
52 #define PCIE_PHY_PLL_STATUS 0x58
53
54 #define PCIE_PHY_TX1_CTRL1 0x60
55 #define PCIE_PHY_TX1_CTRL1_FORCE_EN BIT(3)
56 #define PCIE_PHY_TX1_CTRL1_LOAD_EN BIT(4)
57
58 #define PCIE_PHY_TX1_CTRL2 0x62
59 #define PCIE_PHY_TX1_CTRL3 0x64
60 #define PCIE_PHY_TX1_A_CTRL1 0x66
61 #define PCIE_PHY_TX1_A_CTRL2 0x68
62 #define PCIE_PHY_TX1_MOD1 0x6a
63 #define PCIE_PHY_TX1_MOD2 0x6c
64 #define PCIE_PHY_TX1_MOD3 0x6e
65
66 #define PCIE_PHY_TX2_CTRL1 0x70
67 #define PCIE_PHY_TX2_CTRL1_LOAD_EN BIT(4)
68
69 #define PCIE_PHY_TX2_CTRL2 0x72
70 #define PCIE_PHY_TX2_A_CTRL1 0x76
71 #define PCIE_PHY_TX2_A_CTRL2 0x78
72 #define PCIE_PHY_TX2_MOD1 0x7a
73 #define PCIE_PHY_TX2_MOD2 0x7c
74 #define PCIE_PHY_TX2_MOD3 0x7e
75
76 #define PCIE_PHY_RX1_CTRL1 0xa0
77 #define PCIE_PHY_RX1_CTRL1_LOAD_EN BIT(1)
78
79 #define PCIE_PHY_RX1_CTRL2 0xa2
80 #define PCIE_PHY_RX1_CDR 0xa4
81 #define PCIE_PHY_RX1_EI 0xa6
82 #define PCIE_PHY_RX1_A_CTRL 0xaa
83
84 struct ltq_vrx200_pcie_phy_priv {
85 struct phy *phy;
86 unsigned int mode;
87 struct device *dev;
88 struct regmap *phy_regmap;
89 struct regmap *rcu_regmap;
90 struct clk *pdi_clk;
91 struct clk *phy_clk;
92 struct reset_control *phy_reset;
93 struct reset_control *pcie_reset;
94 u32 rcu_ahb_endian_offset;
95 u32 rcu_ahb_endian_big_endian_mask;
96 };
97
98 static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy)
99 {
100 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
101
102
103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
104
105
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
108
109
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
112
113 regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
114 PCIE_PHY_TX1_CTRL1_FORCE_EN,
115 PCIE_PHY_TX1_CTRL1_FORCE_EN);
116
117
118 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
119
120
121 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
122
123
124 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
125
126
127 regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
128 0x4700);
129
130
131 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
132
133
134 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
135 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);
136
137
138 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
139 }
140
141 static void pcie_phy_36mhz_mode_setup(struct phy *phy)
142 {
143 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
144
145 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
146 PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);
147
148 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
149 PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);
150
151 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
152 PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,
153 PCIE_PHY_PLL_CTRL2_PLL_SDM_EN);
154
155 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
156 PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,
157 PCIE_PHY_PLL_CTRL2_CONST_SDM_EN);
158
159 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
160 PCIE_PHY_PLL_A_CTRL3_MMD_MASK,
161 FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));
162
163 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
164 PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);
165
166
167 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);
168
169 regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
170 PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
171 FIELD_PREP(PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
172 0xee));
173
174
175 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);
176 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);
177 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);
178 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);
179 }
180
181 static int ltq_vrx200_pcie_phy_wait_for_pll(struct phy *phy)
182 {
183 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
184 unsigned int tmp;
185 int ret;
186
187 ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS,
188 tmp, ((tmp & 0x0070) == 0x0070), 10,
189 10000);
190 if (ret) {
191 dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n",
192 tmp);
193 return ret;
194 }
195
196 return 0;
197 }
198
199 static void ltq_vrx200_pcie_phy_apply_workarounds(struct phy *phy)
200 {
201 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
202 static const struct reg_default slices[] = {
203 {
204 .reg = PCIE_PHY_TX1_CTRL1,
205 .def = PCIE_PHY_TX1_CTRL1_LOAD_EN,
206 },
207 {
208 .reg = PCIE_PHY_TX2_CTRL1,
209 .def = PCIE_PHY_TX2_CTRL1_LOAD_EN,
210 },
211 {
212 .reg = PCIE_PHY_RX1_CTRL1,
213 .def = PCIE_PHY_RX1_CTRL1_LOAD_EN,
214 }
215 };
216 int i;
217
218 for (i = 0; i < ARRAY_SIZE(slices); i++) {
219
220 regmap_update_bits(priv->phy_regmap, slices[i].reg,
221 slices[i].def, slices[i].def);
222
223 udelay(1);
224
225
226 regmap_update_bits(priv->phy_regmap, slices[i].reg,
227 slices[i].def, 0x0);
228 }
229
230 for (i = 0; i < 5; i++) {
231
232 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);
233 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);
234 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);
235 usleep_range(1000, 2000);
236 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);
237
238
239 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);
240 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);
241 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);
242 usleep_range(1000, 2000);
243 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);
244 }
245 }
246
247 static int ltq_vrx200_pcie_phy_init(struct phy *phy)
248 {
249 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
250 int ret;
251
252 if (of_device_is_big_endian(priv->dev->of_node))
253 regmap_update_bits(priv->rcu_regmap,
254 priv->rcu_ahb_endian_offset,
255 priv->rcu_ahb_endian_big_endian_mask,
256 priv->rcu_ahb_endian_big_endian_mask);
257 else
258 regmap_update_bits(priv->rcu_regmap,
259 priv->rcu_ahb_endian_offset,
260 priv->rcu_ahb_endian_big_endian_mask, 0x0);
261
262 ret = reset_control_assert(priv->phy_reset);
263 if (ret)
264 goto err;
265
266 udelay(1);
267
268 ret = reset_control_deassert(priv->phy_reset);
269 if (ret)
270 goto err;
271
272 udelay(1);
273
274 ret = reset_control_deassert(priv->pcie_reset);
275 if (ret)
276 goto err_assert_phy_reset;
277
278
279 usleep_range(20, 40);
280
281 return 0;
282
283 err_assert_phy_reset:
284 reset_control_assert(priv->phy_reset);
285 err:
286 return ret;
287 }
288
289 static int ltq_vrx200_pcie_phy_exit(struct phy *phy)
290 {
291 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
292 int ret;
293
294 ret = reset_control_assert(priv->pcie_reset);
295 if (ret)
296 return ret;
297
298 ret = reset_control_assert(priv->phy_reset);
299 if (ret)
300 return ret;
301
302 return 0;
303 }
304
305 static int ltq_vrx200_pcie_phy_power_on(struct phy *phy)
306 {
307 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
308 int ret;
309
310
311 ret = clk_prepare_enable(priv->pdi_clk);
312 if (ret)
313 goto err;
314
315
316 ltq_vrx200_pcie_phy_common_setup(phy);
317
318 pcie_phy_36mhz_mode_setup(phy);
319
320
321 ret = clk_prepare_enable(priv->phy_clk);
322 if (ret)
323 goto err_disable_pdi_clk;
324
325
326 ret = ltq_vrx200_pcie_phy_wait_for_pll(phy);
327 if (ret)
328 goto err_disable_phy_clk;
329
330 ltq_vrx200_pcie_phy_apply_workarounds(phy);
331
332 return 0;
333
334 err_disable_phy_clk:
335 clk_disable_unprepare(priv->phy_clk);
336 err_disable_pdi_clk:
337 clk_disable_unprepare(priv->pdi_clk);
338 err:
339 return ret;
340 }
341
342 static int ltq_vrx200_pcie_phy_power_off(struct phy *phy)
343 {
344 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
345
346 clk_disable_unprepare(priv->phy_clk);
347 clk_disable_unprepare(priv->pdi_clk);
348
349 return 0;
350 }
351
352 static struct phy_ops ltq_vrx200_pcie_phy_ops = {
353 .init = ltq_vrx200_pcie_phy_init,
354 .exit = ltq_vrx200_pcie_phy_exit,
355 .power_on = ltq_vrx200_pcie_phy_power_on,
356 .power_off = ltq_vrx200_pcie_phy_power_off,
357 .owner = THIS_MODULE,
358 };
359
360 static struct phy *ltq_vrx200_pcie_phy_xlate(struct device *dev,
361 struct of_phandle_args *args)
362 {
363 struct ltq_vrx200_pcie_phy_priv *priv = dev_get_drvdata(dev);
364 unsigned int mode;
365
366 if (args->args_count != 1) {
367 dev_err(dev, "invalid number of arguments\n");
368 return ERR_PTR(-EINVAL);
369 }
370
371 mode = args->args[0];
372
373 switch (mode) {
374 case LANTIQ_PCIE_PHY_MODE_36MHZ:
375 priv->mode = mode;
376 break;
377
378 case LANTIQ_PCIE_PHY_MODE_25MHZ:
379 case LANTIQ_PCIE_PHY_MODE_25MHZ_SSC:
380 case LANTIQ_PCIE_PHY_MODE_36MHZ_SSC:
381 case LANTIQ_PCIE_PHY_MODE_100MHZ:
382 case LANTIQ_PCIE_PHY_MODE_100MHZ_SSC:
383 dev_err(dev, "PHY mode not implemented yet: %u\n", mode);
384 return ERR_PTR(-EINVAL);
385
386 default:
387 dev_err(dev, "invalid PHY mode %u\n", mode);
388 return ERR_PTR(-EINVAL);
389 };
390
391 return priv->phy;
392 }
393
394 static int ltq_vrx200_pcie_phy_probe(struct platform_device *pdev)
395 {
396 static const struct regmap_config regmap_config = {
397 .reg_bits = 8,
398 .val_bits = 16,
399 .reg_stride = 2,
400 .max_register = PCIE_PHY_RX1_A_CTRL,
401 };
402 struct ltq_vrx200_pcie_phy_priv *priv;
403 struct device *dev = &pdev->dev;
404 struct phy_provider *provider;
405 struct resource *res;
406 void __iomem *base;
407 int ret;
408
409 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
410 if (!priv)
411 return -ENOMEM;
412
413 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
414 base = devm_ioremap_resource(dev, res);
415 if (IS_ERR(base))
416 return PTR_ERR(base);
417
418 priv->phy_regmap = devm_regmap_init_mmio(dev, base, ®map_config);
419 if (IS_ERR(priv->phy_regmap))
420 return PTR_ERR(priv->phy_regmap);
421
422 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
423 "lantiq,rcu");
424 if (IS_ERR(priv->rcu_regmap))
425 return PTR_ERR(priv->rcu_regmap);
426
427 ret = device_property_read_u32(dev, "lantiq,rcu-endian-offset",
428 &priv->rcu_ahb_endian_offset);
429 if (ret) {
430 dev_err(dev,
431 "failed to parse the 'lantiq,rcu-endian-offset' property\n");
432 return ret;
433 }
434
435 ret = device_property_read_u32(dev, "lantiq,rcu-big-endian-mask",
436 &priv->rcu_ahb_endian_big_endian_mask);
437 if (ret) {
438 dev_err(dev,
439 "failed to parse the 'lantiq,rcu-big-endian-mask' property\n");
440 return ret;
441 }
442
443 priv->pdi_clk = devm_clk_get(dev, "pdi");
444 if (IS_ERR(priv->pdi_clk))
445 return PTR_ERR(priv->pdi_clk);
446
447 priv->phy_clk = devm_clk_get(dev, "phy");
448 if (IS_ERR(priv->phy_clk))
449 return PTR_ERR(priv->phy_clk);
450
451 priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
452 if (IS_ERR(priv->phy_reset))
453 return PTR_ERR(priv->phy_reset);
454
455 priv->pcie_reset = devm_reset_control_get_shared(dev, "pcie");
456 if (IS_ERR(priv->pcie_reset))
457 return PTR_ERR(priv->pcie_reset);
458
459 priv->dev = dev;
460
461 priv->phy = devm_phy_create(dev, dev->of_node,
462 <q_vrx200_pcie_phy_ops);
463 if (IS_ERR(priv->phy)) {
464 dev_err(dev, "failed to create PHY\n");
465 return PTR_ERR(priv->phy);
466 }
467
468 phy_set_drvdata(priv->phy, priv);
469 dev_set_drvdata(dev, priv);
470
471 provider = devm_of_phy_provider_register(dev,
472 ltq_vrx200_pcie_phy_xlate);
473
474 return PTR_ERR_OR_ZERO(provider);
475 }
476
477 static const struct of_device_id ltq_vrx200_pcie_phy_of_match[] = {
478 { .compatible = "lantiq,vrx200-pcie-phy", },
479 { .compatible = "lantiq,arx300-pcie-phy", },
480 { },
481 };
482 MODULE_DEVICE_TABLE(of, ltq_vrx200_pcie_phy_of_match);
483
484 static struct platform_driver ltq_vrx200_pcie_phy_driver = {
485 .probe = ltq_vrx200_pcie_phy_probe,
486 .driver = {
487 .name = "ltq-vrx200-pcie-phy",
488 .of_match_table = ltq_vrx200_pcie_phy_of_match,
489 }
490 };
491 module_platform_driver(ltq_vrx200_pcie_phy_driver);
492
493 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
494 MODULE_DESCRIPTION("Lantiq VRX200 and ARX300 PCIe PHY driver");
495 MODULE_LICENSE("GPL v2");