This source file includes following definitions.
- get_event_type
- event_uses_long_counter
- event_num_counters
- qcom_l3_cache__64bit_counter_start
- qcom_l3_cache__64bit_counter_stop
- qcom_l3_cache__64bit_counter_update
- qcom_l3_cache__32bit_counter_start
- qcom_l3_cache__32bit_counter_stop
- qcom_l3_cache__32bit_counter_update
- l3cache_event_get_ops
- qcom_l3_cache__init
- qcom_l3_cache__handle_irq
- qcom_l3_cache__pmu_enable
- qcom_l3_cache__pmu_disable
- qcom_l3_cache__validate_event_group
- qcom_l3_cache__event_init
- qcom_l3_cache__event_start
- qcom_l3_cache__event_stop
- qcom_l3_cache__event_add
- qcom_l3_cache__event_del
- qcom_l3_cache__event_read
- l3cache_pmu_format_show
- l3cache_pmu_event_show
- qcom_l3_cache_pmu_cpumask_show
- qcom_l3_cache_pmu_online_cpu
- qcom_l3_cache_pmu_offline_cpu
- qcom_l3_cache_pmu_probe
- register_qcom_l3_cache_pmu_driver
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16 #include <linux/acpi.h>
17 #include <linux/bitops.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/perf_event.h>
23 #include <linux/platform_device.h>
24
25
26
27
28
29
30 #define L3_NUM_COUNTERS 8
31
32 #define L3_EVTYPE_MASK 0xFF
33
34
35
36
37
38 #define L3_EVENT_LC_BIT 32
39
40
41
42
43
44
45 #define L3_HML3_PM_CR 0x000
46 #define L3_HML3_PM_EVCNTR(__cntr) (0x420 + ((__cntr) & 0x7) * 8)
47 #define L3_HML3_PM_CNTCTL(__cntr) (0x120 + ((__cntr) & 0x7) * 8)
48 #define L3_HML3_PM_EVTYPE(__cntr) (0x220 + ((__cntr) & 0x7) * 8)
49 #define L3_HML3_PM_FILTRA 0x300
50 #define L3_HML3_PM_FILTRB 0x308
51 #define L3_HML3_PM_FILTRC 0x310
52 #define L3_HML3_PM_FILTRAM 0x304
53 #define L3_HML3_PM_FILTRBM 0x30C
54 #define L3_HML3_PM_FILTRCM 0x314
55
56
57 #define L3_M_BC_CR 0x500
58 #define L3_M_BC_SATROLL_CR 0x504
59 #define L3_M_BC_CNTENSET 0x508
60 #define L3_M_BC_CNTENCLR 0x50C
61 #define L3_M_BC_INTENSET 0x510
62 #define L3_M_BC_INTENCLR 0x514
63 #define L3_M_BC_GANG 0x718
64 #define L3_M_BC_OVSR 0x740
65 #define L3_M_BC_IRQCTL 0x96C
66
67
68
69
70
71
72 #define PM_CR_RESET (0)
73
74
75 #define PMCNT_RESET (0)
76
77
78 #define EVSEL(__val) ((__val) & L3_EVTYPE_MASK)
79
80
81 #define PM_FLTR_RESET (0)
82
83
84 #define BC_RESET (1UL << 1)
85 #define BC_ENABLE (1UL << 0)
86
87
88 #define BC_SATROLL_CR_RESET (0)
89
90
91 #define PMCNTENSET(__cntr) (1UL << ((__cntr) & 0x7))
92
93
94 #define PMCNTENCLR(__cntr) (1UL << ((__cntr) & 0x7))
95 #define BC_CNTENCLR_RESET (0xFF)
96
97
98 #define PMINTENSET(__cntr) (1UL << ((__cntr) & 0x7))
99
100
101 #define PMINTENCLR(__cntr) (1UL << ((__cntr) & 0x7))
102 #define BC_INTENCLR_RESET (0xFF)
103
104
105 #define GANG_EN(__cntr) (1UL << ((__cntr) & 0x7))
106 #define BC_GANG_RESET (0)
107
108
109 #define PMOVSRCLR(__cntr) (1UL << ((__cntr) & 0x7))
110 #define PMOVSRCLR_RESET (0xFF)
111
112
113 #define PMIRQONMSBEN(__cntr) (1UL << ((__cntr) & 0x7))
114 #define BC_IRQCTL_RESET (0x0)
115
116
117
118
119
120 #define L3_EVENT_CYCLES 0x01
121 #define L3_EVENT_READ_HIT 0x20
122 #define L3_EVENT_READ_MISS 0x21
123 #define L3_EVENT_READ_HIT_D 0x22
124 #define L3_EVENT_READ_MISS_D 0x23
125 #define L3_EVENT_WRITE_HIT 0x24
126 #define L3_EVENT_WRITE_MISS 0x25
127
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132
133
134
135
136 static inline u32 get_event_type(struct perf_event *event)
137 {
138 return (event->attr.config) & L3_EVTYPE_MASK;
139 }
140
141 static inline bool event_uses_long_counter(struct perf_event *event)
142 {
143 return !!(event->attr.config & BIT_ULL(L3_EVENT_LC_BIT));
144 }
145
146 static inline int event_num_counters(struct perf_event *event)
147 {
148 return event_uses_long_counter(event) ? 2 : 1;
149 }
150
151
152
153
154 struct l3cache_pmu {
155 struct pmu pmu;
156 struct hlist_node node;
157 void __iomem *regs;
158 struct perf_event *events[L3_NUM_COUNTERS];
159 unsigned long used_mask[BITS_TO_LONGS(L3_NUM_COUNTERS)];
160 cpumask_t cpumask;
161 };
162
163 #define to_l3cache_pmu(p) (container_of(p, struct l3cache_pmu, pmu))
164
165
166
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168
169
170
171
172
173 struct l3cache_event_ops {
174
175 void (*start)(struct perf_event *event);
176
177 void (*stop)(struct perf_event *event, int flags);
178
179 void (*update)(struct perf_event *event);
180 };
181
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191
192
193 static void qcom_l3_cache__64bit_counter_start(struct perf_event *event)
194 {
195 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
196 int idx = event->hw.idx;
197 u32 evsel = get_event_type(event);
198 u32 gang;
199
200
201 gang = readl_relaxed(l3pmu->regs + L3_M_BC_GANG);
202 gang |= GANG_EN(idx + 1);
203 writel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG);
204
205
206 local64_set(&event->hw.prev_count, 0);
207 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
208 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
209
210
211
212
213
214 writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1));
215 writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
216
217
218 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1));
219 writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET);
220 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
221 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
222 }
223
224 static void qcom_l3_cache__64bit_counter_stop(struct perf_event *event,
225 int flags)
226 {
227 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
228 int idx = event->hw.idx;
229 u32 gang = readl_relaxed(l3pmu->regs + L3_M_BC_GANG);
230
231
232 writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
233 writel_relaxed(PMCNTENCLR(idx + 1), l3pmu->regs + L3_M_BC_CNTENCLR);
234
235
236 writel_relaxed(gang & ~GANG_EN(idx + 1), l3pmu->regs + L3_M_BC_GANG);
237 }
238
239 static void qcom_l3_cache__64bit_counter_update(struct perf_event *event)
240 {
241 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
242 int idx = event->hw.idx;
243 u32 hi, lo;
244 u64 prev, new;
245
246 do {
247 prev = local64_read(&event->hw.prev_count);
248 do {
249 hi = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
250 lo = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
251 } while (hi != readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1)));
252 new = ((u64)hi << 32) | lo;
253 } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
254
255 local64_add(new - prev, &event->count);
256 }
257
258 static const struct l3cache_event_ops event_ops_long = {
259 .start = qcom_l3_cache__64bit_counter_start,
260 .stop = qcom_l3_cache__64bit_counter_stop,
261 .update = qcom_l3_cache__64bit_counter_update,
262 };
263
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273
274 static void qcom_l3_cache__32bit_counter_start(struct perf_event *event)
275 {
276 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
277 int idx = event->hw.idx;
278 u32 evsel = get_event_type(event);
279 u32 irqctl = readl_relaxed(l3pmu->regs + L3_M_BC_IRQCTL);
280
281
282 writel_relaxed(irqctl | PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
283
284
285 local64_set(&event->hw.prev_count, 0);
286 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
287
288
289 writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
290
291
292 writel_relaxed(PMINTENSET(idx), l3pmu->regs + L3_M_BC_INTENSET);
293
294
295 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
296 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
297 }
298
299 static void qcom_l3_cache__32bit_counter_stop(struct perf_event *event,
300 int flags)
301 {
302 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
303 int idx = event->hw.idx;
304 u32 irqctl = readl_relaxed(l3pmu->regs + L3_M_BC_IRQCTL);
305
306
307 writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
308
309
310 writel_relaxed(PMINTENCLR(idx), l3pmu->regs + L3_M_BC_INTENCLR);
311
312
313 writel_relaxed(irqctl & ~PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
314 }
315
316 static void qcom_l3_cache__32bit_counter_update(struct perf_event *event)
317 {
318 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
319 int idx = event->hw.idx;
320 u32 prev, new;
321
322 do {
323 prev = local64_read(&event->hw.prev_count);
324 new = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
325 } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
326
327 local64_add(new - prev, &event->count);
328 }
329
330 static const struct l3cache_event_ops event_ops_std = {
331 .start = qcom_l3_cache__32bit_counter_start,
332 .stop = qcom_l3_cache__32bit_counter_stop,
333 .update = qcom_l3_cache__32bit_counter_update,
334 };
335
336
337 static
338 const struct l3cache_event_ops *l3cache_event_get_ops(struct perf_event *event)
339 {
340 if (event_uses_long_counter(event))
341 return &event_ops_long;
342 else
343 return &event_ops_std;
344 }
345
346
347
348
349
350 static inline void qcom_l3_cache__init(struct l3cache_pmu *l3pmu)
351 {
352 int i;
353
354 writel_relaxed(BC_RESET, l3pmu->regs + L3_M_BC_CR);
355
356
357
358
359
360 writel(BC_SATROLL_CR_RESET, l3pmu->regs + L3_M_BC_SATROLL_CR);
361
362 writel_relaxed(BC_CNTENCLR_RESET, l3pmu->regs + L3_M_BC_CNTENCLR);
363 writel_relaxed(BC_INTENCLR_RESET, l3pmu->regs + L3_M_BC_INTENCLR);
364 writel_relaxed(PMOVSRCLR_RESET, l3pmu->regs + L3_M_BC_OVSR);
365 writel_relaxed(BC_GANG_RESET, l3pmu->regs + L3_M_BC_GANG);
366 writel_relaxed(BC_IRQCTL_RESET, l3pmu->regs + L3_M_BC_IRQCTL);
367 writel_relaxed(PM_CR_RESET, l3pmu->regs + L3_HML3_PM_CR);
368
369 for (i = 0; i < L3_NUM_COUNTERS; ++i) {
370 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(i));
371 writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(i));
372 }
373
374 writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRA);
375 writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRAM);
376 writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRB);
377 writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRBM);
378 writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRC);
379 writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRCM);
380
381
382
383
384
385 writel(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
386 }
387
388 static irqreturn_t qcom_l3_cache__handle_irq(int irq_num, void *data)
389 {
390 struct l3cache_pmu *l3pmu = data;
391
392 long status = readl_relaxed(l3pmu->regs + L3_M_BC_OVSR);
393 int idx;
394
395 if (status == 0)
396 return IRQ_NONE;
397
398
399 writel_relaxed(status, l3pmu->regs + L3_M_BC_OVSR);
400
401 for_each_set_bit(idx, &status, L3_NUM_COUNTERS) {
402 struct perf_event *event;
403 const struct l3cache_event_ops *ops;
404
405 event = l3pmu->events[idx];
406 if (!event)
407 continue;
408
409
410
411
412
413
414
415 ops = l3cache_event_get_ops(event);
416 ops->update(event);
417 }
418
419 return IRQ_HANDLED;
420 }
421
422
423
424
425
426
427 static void qcom_l3_cache__pmu_enable(struct pmu *pmu)
428 {
429 struct l3cache_pmu *l3pmu = to_l3cache_pmu(pmu);
430
431
432 wmb();
433
434 writel_relaxed(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
435 }
436
437 static void qcom_l3_cache__pmu_disable(struct pmu *pmu)
438 {
439 struct l3cache_pmu *l3pmu = to_l3cache_pmu(pmu);
440
441 writel_relaxed(0, l3pmu->regs + L3_M_BC_CR);
442
443
444 wmb();
445 }
446
447
448
449
450
451 static bool qcom_l3_cache__validate_event_group(struct perf_event *event)
452 {
453 struct perf_event *leader = event->group_leader;
454 struct perf_event *sibling;
455 int counters = 0;
456
457 if (leader->pmu != event->pmu && !is_software_event(leader))
458 return false;
459
460 counters = event_num_counters(event);
461 counters += event_num_counters(leader);
462
463 for_each_sibling_event(sibling, leader) {
464 if (is_software_event(sibling))
465 continue;
466 if (sibling->pmu != event->pmu)
467 return false;
468 counters += event_num_counters(sibling);
469 }
470
471
472
473
474
475 return counters <= L3_NUM_COUNTERS;
476 }
477
478 static int qcom_l3_cache__event_init(struct perf_event *event)
479 {
480 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
481 struct hw_perf_event *hwc = &event->hw;
482
483
484
485
486 if (event->attr.type != event->pmu->type)
487 return -ENOENT;
488
489
490
491
492 if (hwc->sample_period)
493 return -EINVAL;
494
495
496
497
498
499 if (event->cpu < 0)
500 return -EINVAL;
501
502
503 if (!qcom_l3_cache__validate_event_group(event))
504 return -EINVAL;
505
506 hwc->idx = -1;
507
508
509
510
511
512
513
514
515
516
517
518
519 event->cpu = cpumask_first(&l3pmu->cpumask);
520
521 return 0;
522 }
523
524 static void qcom_l3_cache__event_start(struct perf_event *event, int flags)
525 {
526 struct hw_perf_event *hwc = &event->hw;
527 const struct l3cache_event_ops *ops = l3cache_event_get_ops(event);
528
529 hwc->state = 0;
530 ops->start(event);
531 }
532
533 static void qcom_l3_cache__event_stop(struct perf_event *event, int flags)
534 {
535 struct hw_perf_event *hwc = &event->hw;
536 const struct l3cache_event_ops *ops = l3cache_event_get_ops(event);
537
538 if (hwc->state & PERF_HES_STOPPED)
539 return;
540
541 ops->stop(event, flags);
542 if (flags & PERF_EF_UPDATE)
543 ops->update(event);
544 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
545 }
546
547 static int qcom_l3_cache__event_add(struct perf_event *event, int flags)
548 {
549 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
550 struct hw_perf_event *hwc = &event->hw;
551 int order = event_uses_long_counter(event) ? 1 : 0;
552 int idx;
553
554
555
556
557 idx = bitmap_find_free_region(l3pmu->used_mask, L3_NUM_COUNTERS, order);
558 if (idx < 0)
559
560 return -EAGAIN;
561
562 hwc->idx = idx;
563 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
564 l3pmu->events[idx] = event;
565
566 if (flags & PERF_EF_START)
567 qcom_l3_cache__event_start(event, 0);
568
569
570 perf_event_update_userpage(event);
571
572 return 0;
573 }
574
575 static void qcom_l3_cache__event_del(struct perf_event *event, int flags)
576 {
577 struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
578 struct hw_perf_event *hwc = &event->hw;
579 int order = event_uses_long_counter(event) ? 1 : 0;
580
581
582 qcom_l3_cache__event_stop(event, flags | PERF_EF_UPDATE);
583 l3pmu->events[hwc->idx] = NULL;
584 bitmap_release_region(l3pmu->used_mask, hwc->idx, order);
585
586
587 perf_event_update_userpage(event);
588 }
589
590 static void qcom_l3_cache__event_read(struct perf_event *event)
591 {
592 const struct l3cache_event_ops *ops = l3cache_event_get_ops(event);
593
594 ops->update(event);
595 }
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612 static ssize_t l3cache_pmu_format_show(struct device *dev,
613 struct device_attribute *attr, char *buf)
614 {
615 struct dev_ext_attribute *eattr;
616
617 eattr = container_of(attr, struct dev_ext_attribute, attr);
618 return sprintf(buf, "%s\n", (char *) eattr->var);
619 }
620
621 #define L3CACHE_PMU_FORMAT_ATTR(_name, _config) \
622 (&((struct dev_ext_attribute[]) { \
623 { .attr = __ATTR(_name, 0444, l3cache_pmu_format_show, NULL), \
624 .var = (void *) _config, } \
625 })[0].attr.attr)
626
627 static struct attribute *qcom_l3_cache_pmu_formats[] = {
628 L3CACHE_PMU_FORMAT_ATTR(event, "config:0-7"),
629 L3CACHE_PMU_FORMAT_ATTR(lc, "config:" __stringify(L3_EVENT_LC_BIT)),
630 NULL,
631 };
632
633 static struct attribute_group qcom_l3_cache_pmu_format_group = {
634 .name = "format",
635 .attrs = qcom_l3_cache_pmu_formats,
636 };
637
638
639
640 static ssize_t l3cache_pmu_event_show(struct device *dev,
641 struct device_attribute *attr, char *page)
642 {
643 struct perf_pmu_events_attr *pmu_attr;
644
645 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
646 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
647 }
648
649 #define L3CACHE_EVENT_ATTR(_name, _id) \
650 (&((struct perf_pmu_events_attr[]) { \
651 { .attr = __ATTR(_name, 0444, l3cache_pmu_event_show, NULL), \
652 .id = _id, } \
653 })[0].attr.attr)
654
655 static struct attribute *qcom_l3_cache_pmu_events[] = {
656 L3CACHE_EVENT_ATTR(cycles, L3_EVENT_CYCLES),
657 L3CACHE_EVENT_ATTR(read-hit, L3_EVENT_READ_HIT),
658 L3CACHE_EVENT_ATTR(read-miss, L3_EVENT_READ_MISS),
659 L3CACHE_EVENT_ATTR(read-hit-d-side, L3_EVENT_READ_HIT_D),
660 L3CACHE_EVENT_ATTR(read-miss-d-side, L3_EVENT_READ_MISS_D),
661 L3CACHE_EVENT_ATTR(write-hit, L3_EVENT_WRITE_HIT),
662 L3CACHE_EVENT_ATTR(write-miss, L3_EVENT_WRITE_MISS),
663 NULL
664 };
665
666 static struct attribute_group qcom_l3_cache_pmu_events_group = {
667 .name = "events",
668 .attrs = qcom_l3_cache_pmu_events,
669 };
670
671
672
673 static ssize_t qcom_l3_cache_pmu_cpumask_show(struct device *dev,
674 struct device_attribute *attr, char *buf)
675 {
676 struct l3cache_pmu *l3pmu = to_l3cache_pmu(dev_get_drvdata(dev));
677
678 return cpumap_print_to_pagebuf(true, buf, &l3pmu->cpumask);
679 }
680
681 static DEVICE_ATTR(cpumask, 0444, qcom_l3_cache_pmu_cpumask_show, NULL);
682
683 static struct attribute *qcom_l3_cache_pmu_cpumask_attrs[] = {
684 &dev_attr_cpumask.attr,
685 NULL,
686 };
687
688 static struct attribute_group qcom_l3_cache_pmu_cpumask_attr_group = {
689 .attrs = qcom_l3_cache_pmu_cpumask_attrs,
690 };
691
692
693
694
695 static const struct attribute_group *qcom_l3_cache_pmu_attr_grps[] = {
696 &qcom_l3_cache_pmu_format_group,
697 &qcom_l3_cache_pmu_events_group,
698 &qcom_l3_cache_pmu_cpumask_attr_group,
699 NULL,
700 };
701
702
703
704
705
706 static int qcom_l3_cache_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
707 {
708 struct l3cache_pmu *l3pmu = hlist_entry_safe(node, struct l3cache_pmu, node);
709
710
711 if (cpumask_empty(&l3pmu->cpumask))
712 cpumask_set_cpu(cpu, &l3pmu->cpumask);
713
714 return 0;
715 }
716
717 static int qcom_l3_cache_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
718 {
719 struct l3cache_pmu *l3pmu = hlist_entry_safe(node, struct l3cache_pmu, node);
720 unsigned int target;
721
722 if (!cpumask_test_and_clear_cpu(cpu, &l3pmu->cpumask))
723 return 0;
724 target = cpumask_any_but(cpu_online_mask, cpu);
725 if (target >= nr_cpu_ids)
726 return 0;
727 perf_pmu_migrate_context(&l3pmu->pmu, cpu, target);
728 cpumask_set_cpu(target, &l3pmu->cpumask);
729 return 0;
730 }
731
732 static int qcom_l3_cache_pmu_probe(struct platform_device *pdev)
733 {
734 struct l3cache_pmu *l3pmu;
735 struct acpi_device *acpi_dev;
736 struct resource *memrc;
737 int ret;
738 char *name;
739
740
741
742 acpi_dev = ACPI_COMPANION(&pdev->dev);
743 if (!acpi_dev)
744 return -ENODEV;
745
746 l3pmu = devm_kzalloc(&pdev->dev, sizeof(*l3pmu), GFP_KERNEL);
747 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "l3cache_%s_%s",
748 acpi_dev->parent->pnp.unique_id, acpi_dev->pnp.unique_id);
749 if (!l3pmu || !name)
750 return -ENOMEM;
751
752 l3pmu->pmu = (struct pmu) {
753 .task_ctx_nr = perf_invalid_context,
754
755 .pmu_enable = qcom_l3_cache__pmu_enable,
756 .pmu_disable = qcom_l3_cache__pmu_disable,
757 .event_init = qcom_l3_cache__event_init,
758 .add = qcom_l3_cache__event_add,
759 .del = qcom_l3_cache__event_del,
760 .start = qcom_l3_cache__event_start,
761 .stop = qcom_l3_cache__event_stop,
762 .read = qcom_l3_cache__event_read,
763
764 .attr_groups = qcom_l3_cache_pmu_attr_grps,
765 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
766 };
767
768 memrc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
769 l3pmu->regs = devm_ioremap_resource(&pdev->dev, memrc);
770 if (IS_ERR(l3pmu->regs)) {
771 dev_err(&pdev->dev, "Can't map PMU @%pa\n", &memrc->start);
772 return PTR_ERR(l3pmu->regs);
773 }
774
775 qcom_l3_cache__init(l3pmu);
776
777 ret = platform_get_irq(pdev, 0);
778 if (ret <= 0)
779 return ret;
780
781 ret = devm_request_irq(&pdev->dev, ret, qcom_l3_cache__handle_irq, 0,
782 name, l3pmu);
783 if (ret) {
784 dev_err(&pdev->dev, "Request for IRQ failed for slice @%pa\n",
785 &memrc->start);
786 return ret;
787 }
788
789
790 ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE, &l3pmu->node);
791 if (ret) {
792 dev_err(&pdev->dev, "Error %d registering hotplug", ret);
793 return ret;
794 }
795
796 ret = perf_pmu_register(&l3pmu->pmu, name, -1);
797 if (ret < 0) {
798 dev_err(&pdev->dev, "Failed to register L3 cache PMU (%d)\n", ret);
799 return ret;
800 }
801
802 dev_info(&pdev->dev, "Registered %s, type: %d\n", name, l3pmu->pmu.type);
803
804 return 0;
805 }
806
807 static const struct acpi_device_id qcom_l3_cache_pmu_acpi_match[] = {
808 { "QCOM8081", },
809 { }
810 };
811 MODULE_DEVICE_TABLE(acpi, qcom_l3_cache_pmu_acpi_match);
812
813 static struct platform_driver qcom_l3_cache_pmu_driver = {
814 .driver = {
815 .name = "qcom-l3cache-pmu",
816 .acpi_match_table = ACPI_PTR(qcom_l3_cache_pmu_acpi_match),
817 },
818 .probe = qcom_l3_cache_pmu_probe,
819 };
820
821 static int __init register_qcom_l3_cache_pmu_driver(void)
822 {
823 int ret;
824
825
826 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
827 "perf/qcom/l3cache:online",
828 qcom_l3_cache_pmu_online_cpu,
829 qcom_l3_cache_pmu_offline_cpu);
830 if (ret)
831 return ret;
832
833 return platform_driver_register(&qcom_l3_cache_pmu_driver);
834 }
835 device_initcall(register_qcom_l3_cache_pmu_driver);