root/drivers/perf/arm_pmu_acpi.c

DEFINITIONS

1. arm_pmu_acpi_register_irq
2. arm_pmu_acpi_unregister_irq
3. arm_spe_acpi_register_device
4. arm_spe_acpi_register_device
5. arm_pmu_acpi_parse_irqs
6. arm_pmu_acpi_find_alloc_pmu
7. pmu_irq_matches
8. arm_pmu_acpi_cpu_starting
9. arm_pmu_acpi_probe
10. arm_pmu_acpi_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ACPI probing code for ARM performance counters.
   4  *
   5  * Copyright (C) 2017 ARM Ltd.
   6  */
   7 
   8 #include <linux/acpi.h>
   9 #include <linux/cpumask.h>
  10 #include <linux/init.h>
  11 #include <linux/irq.h>
  12 #include <linux/irqdesc.h>
  13 #include <linux/percpu.h>
  14 #include <linux/perf/arm_pmu.h>
  15 
  16 #include <asm/cputype.h>
  17 
  18 static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);
  19 static DEFINE_PER_CPU(int, pmu_irqs);
  20 
  21 static int arm_pmu_acpi_register_irq(int cpu)
  22 {
  23         struct acpi_madt_generic_interrupt *gicc;
  24         int gsi, trigger;
  25 
  26         gicc = acpi_cpu_get_madt_gicc(cpu);
  27 
  28         gsi = gicc->performance_interrupt;
  29 
  30         /*
  31          * Per the ACPI spec, the MADT cannot describe a PMU that doesn't
  32          * have an interrupt. QEMU advertises this by using a GSI of zero,
  33          * which is not known to be valid on any hardware despite being
  34          * valid per the spec. Take the pragmatic approach and reject a
  35          * GSI of zero for now.
  36          */
  37         if (!gsi)
  38                 return 0;
  39 
  40         if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
  41                 trigger = ACPI_EDGE_SENSITIVE;
  42         else
  43                 trigger = ACPI_LEVEL_SENSITIVE;
  44 
  45         /*
  46          * Helpfully, the MADT GICC doesn't have a polarity flag for the
  47          * "performance interrupt". Luckily, on compliant GICs the polarity is
  48          * a fixed value in HW (for both SPIs and PPIs) that we cannot change
  49          * from SW.
  50          *
  51          * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This
  52          * may not match the real polarity, but that should not matter.
  53          *
  54          * Other interrupt controllers are not supported with ACPI.
  55          */
  56         return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
  57 }
  58 
  59 static void arm_pmu_acpi_unregister_irq(int cpu)
  60 {
  61         struct acpi_madt_generic_interrupt *gicc;
  62         int gsi;
  63 
  64         gicc = acpi_cpu_get_madt_gicc(cpu);
  65 
  66         gsi = gicc->performance_interrupt;
  67         if (gsi)
  68                 acpi_unregister_gsi(gsi);
  69 }
  70 
  71 #if IS_ENABLED(CONFIG_ARM_SPE_PMU)
  72 static struct resource spe_resources[] = {
  73         {
  74                 /* irq */
  75                 .flags          = IORESOURCE_IRQ,
  76         }
  77 };
  78 
  79 static struct platform_device spe_dev = {
  80         .name = ARMV8_SPE_PDEV_NAME,
  81         .id = -1,
  82         .resource = spe_resources,
  83         .num_resources = ARRAY_SIZE(spe_resources)
  84 };
  85 
  86 /*
  87  * For lack of a better place, hook the normal PMU MADT walk
  88  * and create a SPE device if we detect a recent MADT with
  89  * a homogeneous PPI mapping.
  90  */
  91 static void arm_spe_acpi_register_device(void)
  92 {
  93         int cpu, hetid, irq, ret;
  94         bool first = true;
  95         u16 gsi = 0;
  96 
  97         /*
  98          * Sanity check all the GICC tables for the same interrupt number.
  99          * For now, we only support homogeneous ACPI/SPE machines.
 100          */
 101         for_each_possible_cpu(cpu) {
 102                 struct acpi_madt_generic_interrupt *gicc;
 103 
 104                 gicc = acpi_cpu_get_madt_gicc(cpu);
 105                 if (gicc->header.length < ACPI_MADT_GICC_SPE)
 106                         return;
 107 
 108                 if (first) {
 109                         gsi = gicc->spe_interrupt;
 110                         if (!gsi)
 111                                 return;
 112                         hetid = find_acpi_cpu_topology_hetero_id(cpu);
 113                         first = false;
 114                 } else if ((gsi != gicc->spe_interrupt) ||
 115                            (hetid != find_acpi_cpu_topology_hetero_id(cpu))) {
 116                         pr_warn("ACPI: SPE must be homogeneous\n");
 117                         return;
 118                 }
 119         }
 120 
 121         irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE,
 122                                 ACPI_ACTIVE_HIGH);
 123         if (irq < 0) {
 124                 pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi);
 125                 return;
 126         }
 127 
 128         spe_resources[0].start = irq;
 129         ret = platform_device_register(&spe_dev);
 130         if (ret < 0) {
 131                 pr_warn("ACPI: SPE: Unable to register device\n");
 132                 acpi_unregister_gsi(gsi);
 133         }
 134 }
 135 #else
 136 static inline void arm_spe_acpi_register_device(void)
 137 {
 138 }
 139 #endif /* CONFIG_ARM_SPE_PMU */
 140 
 141 static int arm_pmu_acpi_parse_irqs(void)
 142 {
 143         int irq, cpu, irq_cpu, err;
 144 
 145         for_each_possible_cpu(cpu) {
 146                 irq = arm_pmu_acpi_register_irq(cpu);
 147                 if (irq < 0) {
 148                         err = irq;
 149                         pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",
 150                                 cpu, err);
 151                         goto out_err;
 152                 } else if (irq == 0) {
 153                         pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
 154                 }
 155 
 156                 /*
 157                  * Log and request the IRQ so the core arm_pmu code can manage
 158                  * it. We'll have to sanity-check IRQs later when we associate
 159                  * them with their PMUs.
 160                  */
 161                 per_cpu(pmu_irqs, cpu) = irq;
 162                 armpmu_request_irq(irq, cpu);
 163         }
 164 
 165         return 0;
 166 
 167 out_err:
 168         for_each_possible_cpu(cpu) {
 169                 irq = per_cpu(pmu_irqs, cpu);
 170                 if (!irq)
 171                         continue;
 172 
 173                 arm_pmu_acpi_unregister_irq(cpu);
 174 
 175                 /*
 176                  * Blat all copies of the IRQ so that we only unregister the
 177                  * corresponding GSI once (e.g. when we have PPIs).
 178                  */
 179                 for_each_possible_cpu(irq_cpu) {
 180                         if (per_cpu(pmu_irqs, irq_cpu) == irq)
 181                                 per_cpu(pmu_irqs, irq_cpu) = 0;
 182                 }
 183         }
 184 
 185         return err;
 186 }
 187 
 188 static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void)
 189 {
 190         unsigned long cpuid = read_cpuid_id();
 191         struct arm_pmu *pmu;
 192         int cpu;
 193 
 194         for_each_possible_cpu(cpu) {
 195                 pmu = per_cpu(probed_pmus, cpu);
 196                 if (!pmu || pmu->acpi_cpuid != cpuid)
 197                         continue;
 198 
 199                 return pmu;
 200         }
 201 
 202         pmu = armpmu_alloc_atomic();
 203         if (!pmu) {
 204                 pr_warn("Unable to allocate PMU for CPU%d\n",
 205                         smp_processor_id());
 206                 return NULL;
 207         }
 208 
 209         pmu->acpi_cpuid = cpuid;
 210 
 211         return pmu;
 212 }
 213 
 214 /*
 215  * Check whether the new IRQ is compatible with those already associated with
 216  * the PMU (e.g. we don't have mismatched PPIs).
 217  */
 218 static bool pmu_irq_matches(struct arm_pmu *pmu, int irq)
 219 {
 220         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 221         int cpu;
 222 
 223         if (!irq)
 224                 return true;
 225 
 226         for_each_cpu(cpu, &pmu->supported_cpus) {
 227                 int other_irq = per_cpu(hw_events->irq, cpu);
 228                 if (!other_irq)
 229                         continue;
 230 
 231                 if (irq == other_irq)
 232                         continue;
 233                 if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq))
 234                         continue;
 235 
 236                 pr_warn("mismatched PPIs detected\n");
 237                 return false;
 238         }
 239 
 240         return true;
 241 }
 242 
 243 /*
 244  * This must run before the common arm_pmu hotplug logic, so that we can
 245  * associate a CPU and its interrupt before the common code tries to manage the
 246  * affinity and so on.
 247  *
 248  * Note that hotplug events are serialized, so we cannot race with another CPU
 249  * coming up. The perf core won't open events while a hotplug event is in
 250  * progress.
 251  */
 252 static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
 253 {
 254         struct arm_pmu *pmu;
 255         struct pmu_hw_events __percpu *hw_events;
 256         int irq;
 257 
 258         /* If we've already probed this CPU, we have nothing to do */
 259         if (per_cpu(probed_pmus, cpu))
 260                 return 0;
 261 
 262         irq = per_cpu(pmu_irqs, cpu);
 263 
 264         pmu = arm_pmu_acpi_find_alloc_pmu();
 265         if (!pmu)
 266                 return -ENOMEM;
 267 
 268         per_cpu(probed_pmus, cpu) = pmu;
 269 
 270         if (pmu_irq_matches(pmu, irq)) {
 271                 hw_events = pmu->hw_events;
 272                 per_cpu(hw_events->irq, cpu) = irq;
 273         }
 274 
 275         cpumask_set_cpu(cpu, &pmu->supported_cpus);
 276 
 277         /*
 278          * Ideally, we'd probe the PMU here when we find the first matching
 279          * CPU. We can't do that for several reasons; see the comment in
 280          * arm_pmu_acpi_init().
 281          *
 282          * So for the time being, we're done.
 283          */
 284         return 0;
 285 }
 286 
 287 int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
 288 {
 289         int pmu_idx = 0;
 290         int cpu, ret;
 291 
 292         /*
 293          * Initialise and register the set of PMUs which we know about right
 294          * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we
 295          * could handle late hotplug, but this may lead to deadlock since we
 296          * might try to register a hotplug notifier instance from within a
 297          * hotplug notifier.
 298          *
 299          * There's also the problem of having access to the right init_fn,
 300          * without tying this too deeply into the "real" PMU driver.
 301          *
 302          * For the moment, as with the platform/DT case, we need at least one
 303          * of a PMU's CPUs to be online at probe time.
 304          */
 305         for_each_possible_cpu(cpu) {
 306                 struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
 307                 char *base_name;
 308 
 309                 if (!pmu || pmu->name)
 310                         continue;
 311 
 312                 ret = init_fn(pmu);
 313                 if (ret == -ENODEV) {
 314                         /* PMU not handled by this driver, or not present */
 315                         continue;
 316                 } else if (ret) {
 317                         pr_warn("Unable to initialise PMU for CPU%d\n", cpu);
 318                         return ret;
 319                 }
 320 
 321                 base_name = pmu->name;
 322                 pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
 323                 if (!pmu->name) {
 324                         pr_warn("Unable to allocate PMU name for CPU%d\n", cpu);
 325                         return -ENOMEM;
 326                 }
 327 
 328                 ret = armpmu_register(pmu);
 329                 if (ret) {
 330                         pr_warn("Failed to register PMU for CPU%d\n", cpu);
 331                         kfree(pmu->name);
 332                         return ret;
 333                 }
 334         }
 335 
 336         return 0;
 337 }
 338 
 339 static int arm_pmu_acpi_init(void)
 340 {
 341         int ret;
 342 
 343         if (acpi_disabled)
 344                 return 0;
 345 
 346         arm_spe_acpi_register_device();
 347 
 348         ret = arm_pmu_acpi_parse_irqs();
 349         if (ret)
 350                 return ret;
 351 
 352         ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_ACPI_STARTING,
 353                                 "perf/arm/pmu_acpi:starting",
 354                                 arm_pmu_acpi_cpu_starting, NULL);
 355 
 356         return ret;
 357 }
 358 subsys_initcall(arm_pmu_acpi_init)