drivers/bus/ti-sysc.c

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This source file includes following definitions.
sysc_write
sysc_read
sysc_opt_clks_needed
sysc_read_revision
sysc_read_sysconfig
sysc_read_sysstatus
sysc_add_named_clock_from_child
sysc_init_ext_opt_clock
sysc_get_one_clock
sysc_get_clocks
sysc_enable_main_clocks
sysc_disable_main_clocks
sysc_enable_opt_clocks
sysc_disable_opt_clocks
sysc_clkdm_deny_idle
sysc_clkdm_allow_idle
sysc_init_resets
sysc_parse_and_check_child_range
sysc_init_stdout_path
sysc_check_quirk_stdout
sysc_check_one_child
sysc_check_children
sysc_check_quirk_16bit
sysc_parse_one
sysc_parse_registers
sysc_check_registers
sysc_ioremap
sysc_map_and_check_registers
sysc_show_rev
sysc_show_reg
sysc_show_name
sysc_show_registers
sysc_enable_module
sysc_best_idle_mode
sysc_disable_module
sysc_runtime_suspend_legacy
sysc_runtime_resume_legacy
sysc_runtime_suspend
sysc_runtime_resume
sysc_noirq_suspend
sysc_noirq_resume
sysc_init_early_quirks
sysc_init_revision_quirks
sysc_pre_reset_quirk_hdq1w
sysc_module_enable_quirk_aess
sysc_clk_quirk_i2c
sysc_clk_enable_quirk_i2c
sysc_clk_disable_quirk_i2c
sysc_module_enable_quirk_sgx
sysc_reset_done_quirk_wdt
sysc_init_module_quirks
sysc_clockdomain_init
sysc_legacy_init
sysc_rstctrl_reset_deassert
sysc_reset
sysc_init_module
sysc_init_sysc_mask
sysc_init_idlemode
sysc_init_idlemodes
sysc_init_syss_mask
sysc_child_add_named_clock
sysc_child_add_clocks
sysc_child_to_parent
sysc_child_runtime_suspend
sysc_child_runtime_resume
sysc_child_suspend_noirq
sysc_child_resume_noirq
sysc_legacy_idle_quirk
sysc_notifier_call
sysc_parse_dts_quirks
sysc_init_dts_quirks
sysc_unprepare
sysc_init_pdata
sysc_init_match
ti_sysc_idle
sysc_probe
sysc_remove
sysc_init
sysc_exit
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ti-sysc.c - Texas Instruments sysc interconnect target driver
   4  */
   5 
   6 #include <linux/io.h>
   7 #include <linux/clk.h>
   8 #include <linux/clkdev.h>
   9 #include <linux/delay.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pm_domain.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/reset.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/slab.h>
  18 #include <linux/iopoll.h>
  19 
  20 #include <linux/platform_data/ti-sysc.h>
  21 
  22 #include <dt-bindings/bus/ti-sysc.h>
  23 
  24 #define MAX_MODULE_SOFTRESET_WAIT               10000
  25 
  26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
  27 
  28 enum sysc_clocks {
  29         SYSC_FCK,
  30         SYSC_ICK,
  31         SYSC_OPTFCK0,
  32         SYSC_OPTFCK1,
  33         SYSC_OPTFCK2,
  34         SYSC_OPTFCK3,
  35         SYSC_OPTFCK4,
  36         SYSC_OPTFCK5,
  37         SYSC_OPTFCK6,
  38         SYSC_OPTFCK7,
  39         SYSC_MAX_CLOCKS,
  40 };
  41 
  42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
  43         "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
  44         "opt5", "opt6", "opt7",
  45 };
  46 
  47 #define SYSC_IDLEMODE_MASK              3
  48 #define SYSC_CLOCKACTIVITY_MASK         3
  49 
  50 /**
  51  * struct sysc - TI sysc interconnect target module registers and capabilities
  52  * @dev: struct device pointer
  53  * @module_pa: physical address of the interconnect target module
  54  * @module_size: size of the interconnect target module
  55  * @module_va: virtual address of the interconnect target module
  56  * @offsets: register offsets from module base
  57  * @mdata: ti-sysc to hwmod translation data for a module
  58  * @clocks: clocks used by the interconnect target module
  59  * @clock_roles: clock role names for the found clocks
  60  * @nr_clocks: number of clocks used by the interconnect target module
  61  * @rsts: resets used by the interconnect target module
  62  * @legacy_mode: configured for legacy mode if set
  63  * @cap: interconnect target module capabilities
  64  * @cfg: interconnect target module configuration
  65  * @cookie: data used by legacy platform callbacks
  66  * @name: name if available
  67  * @revision: interconnect target module revision
  68  * @enabled: sysc runtime enabled status
  69  * @needs_resume: runtime resume needed on resume from suspend
  70  * @child_needs_resume: runtime resume needed for child on resume from suspend
  71  * @disable_on_idle: status flag used for disabling modules with resets
  72  * @idle_work: work structure used to perform delayed idle on a module
  73  * @clk_enable_quirk: module specific clock enable quirk
  74  * @clk_disable_quirk: module specific clock disable quirk
  75  * @reset_done_quirk: module specific reset done quirk
  76  * @module_enable_quirk: module specific enable quirk
  77  * @module_disable_quirk: module specific disable quirk
  78  */
  79 struct sysc {
  80         struct device *dev;
  81         u64 module_pa;
  82         u32 module_size;
  83         void __iomem *module_va;
  84         int offsets[SYSC_MAX_REGS];
  85         struct ti_sysc_module_data *mdata;
  86         struct clk **clocks;
  87         const char **clock_roles;
  88         int nr_clocks;
  89         struct reset_control *rsts;
  90         const char *legacy_mode;
  91         const struct sysc_capabilities *cap;
  92         struct sysc_config cfg;
  93         struct ti_sysc_cookie cookie;
  94         const char *name;
  95         u32 revision;
  96         unsigned int enabled:1;
  97         unsigned int needs_resume:1;
  98         unsigned int child_needs_resume:1;
  99         struct delayed_work idle_work;
 100         void (*clk_enable_quirk)(struct sysc *sysc);
 101         void (*clk_disable_quirk)(struct sysc *sysc);
 102         void (*reset_done_quirk)(struct sysc *sysc);
 103         void (*module_enable_quirk)(struct sysc *sysc);
 104         void (*module_disable_quirk)(struct sysc *sysc);
 105 };
 106 
 107 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
 108                                   bool is_child);
 109 
 110 static void sysc_write(struct sysc *ddata, int offset, u32 value)
 111 {
 112         if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
 113                 writew_relaxed(value & 0xffff, ddata->module_va + offset);
 114 
 115                 /* Only i2c revision has LO and HI register with stride of 4 */
 116                 if (ddata->offsets[SYSC_REVISION] >= 0 &&
 117                     offset == ddata->offsets[SYSC_REVISION]) {
 118                         u16 hi = value >> 16;
 119 
 120                         writew_relaxed(hi, ddata->module_va + offset + 4);
 121                 }
 122 
 123                 return;
 124         }
 125 
 126         writel_relaxed(value, ddata->module_va + offset);
 127 }
 128 
 129 static u32 sysc_read(struct sysc *ddata, int offset)
 130 {
 131         if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
 132                 u32 val;
 133 
 134                 val = readw_relaxed(ddata->module_va + offset);
 135 
 136                 /* Only i2c revision has LO and HI register with stride of 4 */
 137                 if (ddata->offsets[SYSC_REVISION] >= 0 &&
 138                     offset == ddata->offsets[SYSC_REVISION]) {
 139                         u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
 140 
 141                         val |= tmp << 16;
 142                 }
 143 
 144                 return val;
 145         }
 146 
 147         return readl_relaxed(ddata->module_va + offset);
 148 }
 149 
 150 static bool sysc_opt_clks_needed(struct sysc *ddata)
 151 {
 152         return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
 153 }
 154 
 155 static u32 sysc_read_revision(struct sysc *ddata)
 156 {
 157         int offset = ddata->offsets[SYSC_REVISION];
 158 
 159         if (offset < 0)
 160                 return 0;
 161 
 162         return sysc_read(ddata, offset);
 163 }
 164 
 165 static u32 sysc_read_sysconfig(struct sysc *ddata)
 166 {
 167         int offset = ddata->offsets[SYSC_SYSCONFIG];
 168 
 169         if (offset < 0)
 170                 return 0;
 171 
 172         return sysc_read(ddata, offset);
 173 }
 174 
 175 static u32 sysc_read_sysstatus(struct sysc *ddata)
 176 {
 177         int offset = ddata->offsets[SYSC_SYSSTATUS];
 178 
 179         if (offset < 0)
 180                 return 0;
 181 
 182         return sysc_read(ddata, offset);
 183 }
 184 
 185 static int sysc_add_named_clock_from_child(struct sysc *ddata,
 186                                            const char *name,
 187                                            const char *optfck_name)
 188 {
 189         struct device_node *np = ddata->dev->of_node;
 190         struct device_node *child;
 191         struct clk_lookup *cl;
 192         struct clk *clock;
 193         const char *n;
 194 
 195         if (name)
 196                 n = name;
 197         else
 198                 n = optfck_name;
 199 
 200         /* Does the clock alias already exist? */
 201         clock = of_clk_get_by_name(np, n);
 202         if (!IS_ERR(clock)) {
 203                 clk_put(clock);
 204 
 205                 return 0;
 206         }
 207 
 208         child = of_get_next_available_child(np, NULL);
 209         if (!child)
 210                 return -ENODEV;
 211 
 212         clock = devm_get_clk_from_child(ddata->dev, child, name);
 213         if (IS_ERR(clock))
 214                 return PTR_ERR(clock);
 215 
 216         /*
 217          * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
 218          * limit for clk_get(). If cl ever needs to be freed, it should be done
 219          * with clkdev_drop().
 220          */
 221         cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
 222         if (!cl)
 223                 return -ENOMEM;
 224 
 225         cl->con_id = n;
 226         cl->dev_id = dev_name(ddata->dev);
 227         cl->clk = clock;
 228         clkdev_add(cl);
 229 
 230         clk_put(clock);
 231 
 232         return 0;
 233 }
 234 
 235 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
 236 {
 237         const char *optfck_name;
 238         int error, index;
 239 
 240         if (ddata->nr_clocks < SYSC_OPTFCK0)
 241                 index = SYSC_OPTFCK0;
 242         else
 243                 index = ddata->nr_clocks;
 244 
 245         if (name)
 246                 optfck_name = name;
 247         else
 248                 optfck_name = clock_names[index];
 249 
 250         error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
 251         if (error)
 252                 return error;
 253 
 254         ddata->clock_roles[index] = optfck_name;
 255         ddata->nr_clocks++;
 256 
 257         return 0;
 258 }
 259 
 260 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
 261 {
 262         int error, i, index = -ENODEV;
 263 
 264         if (!strncmp(clock_names[SYSC_FCK], name, 3))
 265                 index = SYSC_FCK;
 266         else if (!strncmp(clock_names[SYSC_ICK], name, 3))
 267                 index = SYSC_ICK;
 268 
 269         if (index < 0) {
 270                 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
 271                         if (!ddata->clocks[i]) {
 272                                 index = i;
 273                                 break;
 274                         }
 275                 }
 276         }
 277 
 278         if (index < 0) {
 279                 dev_err(ddata->dev, "clock %s not added\n", name);
 280                 return index;
 281         }
 282 
 283         ddata->clocks[index] = devm_clk_get(ddata->dev, name);
 284         if (IS_ERR(ddata->clocks[index])) {
 285                 dev_err(ddata->dev, "clock get error for %s: %li\n",
 286                         name, PTR_ERR(ddata->clocks[index]));
 287 
 288                 return PTR_ERR(ddata->clocks[index]);
 289         }
 290 
 291         error = clk_prepare(ddata->clocks[index]);
 292         if (error) {
 293                 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
 294                         name, error);
 295 
 296                 return error;
 297         }
 298 
 299         return 0;
 300 }
 301 
 302 static int sysc_get_clocks(struct sysc *ddata)
 303 {
 304         struct device_node *np = ddata->dev->of_node;
 305         struct property *prop;
 306         const char *name;
 307         int nr_fck = 0, nr_ick = 0, i, error = 0;
 308 
 309         ddata->clock_roles = devm_kcalloc(ddata->dev,
 310                                           SYSC_MAX_CLOCKS,
 311                                           sizeof(*ddata->clock_roles),
 312                                           GFP_KERNEL);
 313         if (!ddata->clock_roles)
 314                 return -ENOMEM;
 315 
 316         of_property_for_each_string(np, "clock-names", prop, name) {
 317                 if (!strncmp(clock_names[SYSC_FCK], name, 3))
 318                         nr_fck++;
 319                 if (!strncmp(clock_names[SYSC_ICK], name, 3))
 320                         nr_ick++;
 321                 ddata->clock_roles[ddata->nr_clocks] = name;
 322                 ddata->nr_clocks++;
 323         }
 324 
 325         if (ddata->nr_clocks < 1)
 326                 return 0;
 327 
 328         if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
 329                 error = sysc_init_ext_opt_clock(ddata, NULL);
 330                 if (error)
 331                         return error;
 332         }
 333 
 334         if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
 335                 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
 336 
 337                 return -EINVAL;
 338         }
 339 
 340         if (nr_fck > 1 || nr_ick > 1) {
 341                 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
 342 
 343                 return -EINVAL;
 344         }
 345 
 346         /* Always add a slot for main clocks fck and ick even if unused */
 347         if (!nr_fck)
 348                 ddata->nr_clocks++;
 349         if (!nr_ick)
 350                 ddata->nr_clocks++;
 351 
 352         ddata->clocks = devm_kcalloc(ddata->dev,
 353                                      ddata->nr_clocks, sizeof(*ddata->clocks),
 354                                      GFP_KERNEL);
 355         if (!ddata->clocks)
 356                 return -ENOMEM;
 357 
 358         for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
 359                 const char *name = ddata->clock_roles[i];
 360 
 361                 if (!name)
 362                         continue;
 363 
 364                 error = sysc_get_one_clock(ddata, name);
 365                 if (error)
 366                         return error;
 367         }
 368 
 369         return 0;
 370 }
 371 
 372 static int sysc_enable_main_clocks(struct sysc *ddata)
 373 {
 374         struct clk *clock;
 375         int i, error;
 376 
 377         if (!ddata->clocks)
 378                 return 0;
 379 
 380         for (i = 0; i < SYSC_OPTFCK0; i++) {
 381                 clock = ddata->clocks[i];
 382 
 383                 /* Main clocks may not have ick */
 384                 if (IS_ERR_OR_NULL(clock))
 385                         continue;
 386 
 387                 error = clk_enable(clock);
 388                 if (error)
 389                         goto err_disable;
 390         }
 391 
 392         return 0;
 393 
 394 err_disable:
 395         for (i--; i >= 0; i--) {
 396                 clock = ddata->clocks[i];
 397 
 398                 /* Main clocks may not have ick */
 399                 if (IS_ERR_OR_NULL(clock))
 400                         continue;
 401 
 402                 clk_disable(clock);
 403         }
 404 
 405         return error;
 406 }
 407 
 408 static void sysc_disable_main_clocks(struct sysc *ddata)
 409 {
 410         struct clk *clock;
 411         int i;
 412 
 413         if (!ddata->clocks)
 414                 return;
 415 
 416         for (i = 0; i < SYSC_OPTFCK0; i++) {
 417                 clock = ddata->clocks[i];
 418                 if (IS_ERR_OR_NULL(clock))
 419                         continue;
 420 
 421                 clk_disable(clock);
 422         }
 423 }
 424 
 425 static int sysc_enable_opt_clocks(struct sysc *ddata)
 426 {
 427         struct clk *clock;
 428         int i, error;
 429 
 430         if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
 431                 return 0;
 432 
 433         for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
 434                 clock = ddata->clocks[i];
 435 
 436                 /* Assume no holes for opt clocks */
 437                 if (IS_ERR_OR_NULL(clock))
 438                         return 0;
 439 
 440                 error = clk_enable(clock);
 441                 if (error)
 442                         goto err_disable;
 443         }
 444 
 445         return 0;
 446 
 447 err_disable:
 448         for (i--; i >= 0; i--) {
 449                 clock = ddata->clocks[i];
 450                 if (IS_ERR_OR_NULL(clock))
 451                         continue;
 452 
 453                 clk_disable(clock);
 454         }
 455 
 456         return error;
 457 }
 458 
 459 static void sysc_disable_opt_clocks(struct sysc *ddata)
 460 {
 461         struct clk *clock;
 462         int i;
 463 
 464         if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
 465                 return;
 466 
 467         for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
 468                 clock = ddata->clocks[i];
 469 
 470                 /* Assume no holes for opt clocks */
 471                 if (IS_ERR_OR_NULL(clock))
 472                         return;
 473 
 474                 clk_disable(clock);
 475         }
 476 }
 477 
 478 static void sysc_clkdm_deny_idle(struct sysc *ddata)
 479 {
 480         struct ti_sysc_platform_data *pdata;
 481 
 482         if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
 483                 return;
 484 
 485         pdata = dev_get_platdata(ddata->dev);
 486         if (pdata && pdata->clkdm_deny_idle)
 487                 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
 488 }
 489 
 490 static void sysc_clkdm_allow_idle(struct sysc *ddata)
 491 {
 492         struct ti_sysc_platform_data *pdata;
 493 
 494         if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
 495                 return;
 496 
 497         pdata = dev_get_platdata(ddata->dev);
 498         if (pdata && pdata->clkdm_allow_idle)
 499                 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
 500 }
 501 
 502 /**
 503  * sysc_init_resets - init rstctrl reset line if configured
 504  * @ddata: device driver data
 505  *
 506  * See sysc_rstctrl_reset_deassert().
 507  */
 508 static int sysc_init_resets(struct sysc *ddata)
 509 {
 510         ddata->rsts =
 511                 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
 512         if (IS_ERR(ddata->rsts))
 513                 return PTR_ERR(ddata->rsts);
 514 
 515         return 0;
 516 }
 517 
 518 /**
 519  * sysc_parse_and_check_child_range - parses module IO region from ranges
 520  * @ddata: device driver data
 521  *
 522  * In general we only need rev, syss, and sysc registers and not the whole
 523  * module range. But we do want the offsets for these registers from the
 524  * module base. This allows us to check them against the legacy hwmod
 525  * platform data. Let's also check the ranges are configured properly.
 526  */
 527 static int sysc_parse_and_check_child_range(struct sysc *ddata)
 528 {
 529         struct device_node *np = ddata->dev->of_node;
 530         const __be32 *ranges;
 531         u32 nr_addr, nr_size;
 532         int len, error;
 533 
 534         ranges = of_get_property(np, "ranges", &len);
 535         if (!ranges) {
 536                 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
 537 
 538                 return -ENOENT;
 539         }
 540 
 541         len /= sizeof(*ranges);
 542 
 543         if (len < 3) {
 544                 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
 545 
 546                 return -EINVAL;
 547         }
 548 
 549         error = of_property_read_u32(np, "#address-cells", &nr_addr);
 550         if (error)
 551                 return -ENOENT;
 552 
 553         error = of_property_read_u32(np, "#size-cells", &nr_size);
 554         if (error)
 555                 return -ENOENT;
 556 
 557         if (nr_addr != 1 || nr_size != 1) {
 558                 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
 559 
 560                 return -EINVAL;
 561         }
 562 
 563         ranges++;
 564         ddata->module_pa = of_translate_address(np, ranges++);
 565         ddata->module_size = be32_to_cpup(ranges);
 566 
 567         return 0;
 568 }
 569 
 570 static struct device_node *stdout_path;
 571 
 572 static void sysc_init_stdout_path(struct sysc *ddata)
 573 {
 574         struct device_node *np = NULL;
 575         const char *uart;
 576 
 577         if (IS_ERR(stdout_path))
 578                 return;
 579 
 580         if (stdout_path)
 581                 return;
 582 
 583         np = of_find_node_by_path("/chosen");
 584         if (!np)
 585                 goto err;
 586 
 587         uart = of_get_property(np, "stdout-path", NULL);
 588         if (!uart)
 589                 goto err;
 590 
 591         np = of_find_node_by_path(uart);
 592         if (!np)
 593                 goto err;
 594 
 595         stdout_path = np;
 596 
 597         return;
 598 
 599 err:
 600         stdout_path = ERR_PTR(-ENODEV);
 601 }
 602 
 603 static void sysc_check_quirk_stdout(struct sysc *ddata,
 604                                     struct device_node *np)
 605 {
 606         sysc_init_stdout_path(ddata);
 607         if (np != stdout_path)
 608                 return;
 609 
 610         ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
 611                                 SYSC_QUIRK_NO_RESET_ON_INIT;
 612 }
 613 
 614 /**
 615  * sysc_check_one_child - check child configuration
 616  * @ddata: device driver data
 617  * @np: child device node
 618  *
 619  * Let's avoid messy situations where we have new interconnect target
 620  * node but children have "ti,hwmods". These belong to the interconnect
 621  * target node and are managed by this driver.
 622  */
 623 static void sysc_check_one_child(struct sysc *ddata,
 624                                  struct device_node *np)
 625 {
 626         const char *name;
 627 
 628         name = of_get_property(np, "ti,hwmods", NULL);
 629         if (name)
 630                 dev_warn(ddata->dev, "really a child ti,hwmods property?");
 631 
 632         sysc_check_quirk_stdout(ddata, np);
 633         sysc_parse_dts_quirks(ddata, np, true);
 634 }
 635 
 636 static void sysc_check_children(struct sysc *ddata)
 637 {
 638         struct device_node *child;
 639 
 640         for_each_child_of_node(ddata->dev->of_node, child)
 641                 sysc_check_one_child(ddata, child);
 642 }
 643 
 644 /*
 645  * So far only I2C uses 16-bit read access with clockactivity with revision
 646  * in two registers with stride of 4. We can detect this based on the rev
 647  * register size to configure things far enough to be able to properly read
 648  * the revision register.
 649  */
 650 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
 651 {
 652         if (resource_size(res) == 8)
 653                 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
 654 }
 655 
 656 /**
 657  * sysc_parse_one - parses the interconnect target module registers
 658  * @ddata: device driver data
 659  * @reg: register to parse
 660  */
 661 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
 662 {
 663         struct resource *res;
 664         const char *name;
 665 
 666         switch (reg) {
 667         case SYSC_REVISION:
 668         case SYSC_SYSCONFIG:
 669         case SYSC_SYSSTATUS:
 670                 name = reg_names[reg];
 671                 break;
 672         default:
 673                 return -EINVAL;
 674         }
 675 
 676         res = platform_get_resource_byname(to_platform_device(ddata->dev),
 677                                            IORESOURCE_MEM, name);
 678         if (!res) {
 679                 ddata->offsets[reg] = -ENODEV;
 680 
 681                 return 0;
 682         }
 683 
 684         ddata->offsets[reg] = res->start - ddata->module_pa;
 685         if (reg == SYSC_REVISION)
 686                 sysc_check_quirk_16bit(ddata, res);
 687 
 688         return 0;
 689 }
 690 
 691 static int sysc_parse_registers(struct sysc *ddata)
 692 {
 693         int i, error;
 694 
 695         for (i = 0; i < SYSC_MAX_REGS; i++) {
 696                 error = sysc_parse_one(ddata, i);
 697                 if (error)
 698                         return error;
 699         }
 700 
 701         return 0;
 702 }
 703 
 704 /**
 705  * sysc_check_registers - check for misconfigured register overlaps
 706  * @ddata: device driver data
 707  */
 708 static int sysc_check_registers(struct sysc *ddata)
 709 {
 710         int i, j, nr_regs = 0, nr_matches = 0;
 711 
 712         for (i = 0; i < SYSC_MAX_REGS; i++) {
 713                 if (ddata->offsets[i] < 0)
 714                         continue;
 715 
 716                 if (ddata->offsets[i] > (ddata->module_size - 4)) {
 717                         dev_err(ddata->dev, "register outside module range");
 718 
 719                                 return -EINVAL;
 720                 }
 721 
 722                 for (j = 0; j < SYSC_MAX_REGS; j++) {
 723                         if (ddata->offsets[j] < 0)
 724                                 continue;
 725 
 726                         if (ddata->offsets[i] == ddata->offsets[j])
 727                                 nr_matches++;
 728                 }
 729                 nr_regs++;
 730         }
 731 
 732         if (nr_matches > nr_regs) {
 733                 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
 734                         nr_regs, nr_matches);
 735 
 736                 return -EINVAL;
 737         }
 738 
 739         return 0;
 740 }
 741 
 742 /**
 743  * syc_ioremap - ioremap register space for the interconnect target module
 744  * @ddata: device driver data
 745  *
 746  * Note that the interconnect target module registers can be anywhere
 747  * within the interconnect target module range. For example, SGX has
 748  * them at offset 0x1fc00 in the 32MB module address space. And cpsw
 749  * has them at offset 0x1200 in the CPSW_WR child. Usually the
 750  * the interconnect target module registers are at the beginning of
 751  * the module range though.
 752  */
 753 static int sysc_ioremap(struct sysc *ddata)
 754 {
 755         int size;
 756 
 757         if (ddata->offsets[SYSC_REVISION] < 0 &&
 758             ddata->offsets[SYSC_SYSCONFIG] < 0 &&
 759             ddata->offsets[SYSC_SYSSTATUS] < 0) {
 760                 size = ddata->module_size;
 761         } else {
 762                 size = max3(ddata->offsets[SYSC_REVISION],
 763                             ddata->offsets[SYSC_SYSCONFIG],
 764                             ddata->offsets[SYSC_SYSSTATUS]);
 765 
 766                 if (size < SZ_1K)
 767                         size = SZ_1K;
 768 
 769                 if ((size + sizeof(u32)) > ddata->module_size)
 770                         size = ddata->module_size;
 771         }
 772 
 773         ddata->module_va = devm_ioremap(ddata->dev,
 774                                         ddata->module_pa,
 775                                         size + sizeof(u32));
 776         if (!ddata->module_va)
 777                 return -EIO;
 778 
 779         return 0;
 780 }
 781 
 782 /**
 783  * sysc_map_and_check_registers - ioremap and check device registers
 784  * @ddata: device driver data
 785  */
 786 static int sysc_map_and_check_registers(struct sysc *ddata)
 787 {
 788         int error;
 789 
 790         error = sysc_parse_and_check_child_range(ddata);
 791         if (error)
 792                 return error;
 793 
 794         sysc_check_children(ddata);
 795 
 796         error = sysc_parse_registers(ddata);
 797         if (error)
 798                 return error;
 799 
 800         error = sysc_ioremap(ddata);
 801         if (error)
 802                 return error;
 803 
 804         error = sysc_check_registers(ddata);
 805         if (error)
 806                 return error;
 807 
 808         return 0;
 809 }
 810 
 811 /**
 812  * sysc_show_rev - read and show interconnect target module revision
 813  * @bufp: buffer to print the information to
 814  * @ddata: device driver data
 815  */
 816 static int sysc_show_rev(char *bufp, struct sysc *ddata)
 817 {
 818         int len;
 819 
 820         if (ddata->offsets[SYSC_REVISION] < 0)
 821                 return sprintf(bufp, ":NA");
 822 
 823         len = sprintf(bufp, ":%08x", ddata->revision);
 824 
 825         return len;
 826 }
 827 
 828 static int sysc_show_reg(struct sysc *ddata,
 829                          char *bufp, enum sysc_registers reg)
 830 {
 831         if (ddata->offsets[reg] < 0)
 832                 return sprintf(bufp, ":NA");
 833 
 834         return sprintf(bufp, ":%x", ddata->offsets[reg]);
 835 }
 836 
 837 static int sysc_show_name(char *bufp, struct sysc *ddata)
 838 {
 839         if (!ddata->name)
 840                 return 0;
 841 
 842         return sprintf(bufp, ":%s", ddata->name);
 843 }
 844 
 845 /**
 846  * sysc_show_registers - show information about interconnect target module
 847  * @ddata: device driver data
 848  */
 849 static void sysc_show_registers(struct sysc *ddata)
 850 {
 851         char buf[128];
 852         char *bufp = buf;
 853         int i;
 854 
 855         for (i = 0; i < SYSC_MAX_REGS; i++)
 856                 bufp += sysc_show_reg(ddata, bufp, i);
 857 
 858         bufp += sysc_show_rev(bufp, ddata);
 859         bufp += sysc_show_name(bufp, ddata);
 860 
 861         dev_dbg(ddata->dev, "%llx:%x%s\n",
 862                 ddata->module_pa, ddata->module_size,
 863                 buf);
 864 }
 865 
 866 #define SYSC_IDLE_MASK  (SYSC_NR_IDLEMODES - 1)
 867 #define SYSC_CLOCACT_ICK        2
 868 
 869 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
 870 static int sysc_enable_module(struct device *dev)
 871 {
 872         struct sysc *ddata;
 873         const struct sysc_regbits *regbits;
 874         u32 reg, idlemodes, best_mode;
 875 
 876         ddata = dev_get_drvdata(dev);
 877         if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
 878                 return 0;
 879 
 880         regbits = ddata->cap->regbits;
 881         reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
 882 
 883         /* Set CLOCKACTIVITY, we only use it for ick */
 884         if (regbits->clkact_shift >= 0 &&
 885             (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
 886              ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
 887                 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
 888 
 889         /* Set SIDLE mode */
 890         idlemodes = ddata->cfg.sidlemodes;
 891         if (!idlemodes || regbits->sidle_shift < 0)
 892                 goto set_midle;
 893 
 894         if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
 895                                  SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
 896                 best_mode = SYSC_IDLE_NO;
 897         } else {
 898                 best_mode = fls(ddata->cfg.sidlemodes) - 1;
 899                 if (best_mode > SYSC_IDLE_MASK) {
 900                         dev_err(dev, "%s: invalid sidlemode\n", __func__);
 901                         return -EINVAL;
 902                 }
 903 
 904                 /* Set WAKEUP */
 905                 if (regbits->enwkup_shift >= 0 &&
 906                     ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
 907                         reg |= BIT(regbits->enwkup_shift);
 908         }
 909 
 910         reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
 911         reg |= best_mode << regbits->sidle_shift;
 912         sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 913 
 914 set_midle:
 915         /* Set MIDLE mode */
 916         idlemodes = ddata->cfg.midlemodes;
 917         if (!idlemodes || regbits->midle_shift < 0)
 918                 goto set_autoidle;
 919 
 920         best_mode = fls(ddata->cfg.midlemodes) - 1;
 921         if (best_mode > SYSC_IDLE_MASK) {
 922                 dev_err(dev, "%s: invalid midlemode\n", __func__);
 923                 return -EINVAL;
 924         }
 925 
 926         if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
 927                 best_mode = SYSC_IDLE_NO;
 928 
 929         reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
 930         reg |= best_mode << regbits->midle_shift;
 931         sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 932 
 933 set_autoidle:
 934         /* Autoidle bit must enabled separately if available */
 935         if (regbits->autoidle_shift >= 0 &&
 936             ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
 937                 reg |= 1 << regbits->autoidle_shift;
 938                 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 939         }
 940 
 941         if (ddata->module_enable_quirk)
 942                 ddata->module_enable_quirk(ddata);
 943 
 944         return 0;
 945 }
 946 
 947 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
 948 {
 949         if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
 950                 *best_mode = SYSC_IDLE_SMART_WKUP;
 951         else if (idlemodes & BIT(SYSC_IDLE_SMART))
 952                 *best_mode = SYSC_IDLE_SMART;
 953         else if (idlemodes & BIT(SYSC_IDLE_FORCE))
 954                 *best_mode = SYSC_IDLE_FORCE;
 955         else
 956                 return -EINVAL;
 957 
 958         return 0;
 959 }
 960 
 961 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
 962 static int sysc_disable_module(struct device *dev)
 963 {
 964         struct sysc *ddata;
 965         const struct sysc_regbits *regbits;
 966         u32 reg, idlemodes, best_mode;
 967         int ret;
 968 
 969         ddata = dev_get_drvdata(dev);
 970         if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
 971                 return 0;
 972 
 973         if (ddata->module_disable_quirk)
 974                 ddata->module_disable_quirk(ddata);
 975 
 976         regbits = ddata->cap->regbits;
 977         reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
 978 
 979         /* Set MIDLE mode */
 980         idlemodes = ddata->cfg.midlemodes;
 981         if (!idlemodes || regbits->midle_shift < 0)
 982                 goto set_sidle;
 983 
 984         ret = sysc_best_idle_mode(idlemodes, &best_mode);
 985         if (ret) {
 986                 dev_err(dev, "%s: invalid midlemode\n", __func__);
 987                 return ret;
 988         }
 989 
 990         if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
 991             ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
 992                 best_mode = SYSC_IDLE_FORCE;
 993 
 994         reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
 995         reg |= best_mode << regbits->midle_shift;
 996         sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 997 
 998 set_sidle:
 999         /* Set SIDLE mode */
1000         idlemodes = ddata->cfg.sidlemodes;
1001         if (!idlemodes || regbits->sidle_shift < 0)
1002                 return 0;
1003 
1004         if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1005                 best_mode = SYSC_IDLE_FORCE;
1006         } else {
1007                 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1008                 if (ret) {
1009                         dev_err(dev, "%s: invalid sidlemode\n", __func__);
1010                         return ret;
1011                 }
1012         }
1013 
1014         reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1015         reg |= best_mode << regbits->sidle_shift;
1016         if (regbits->autoidle_shift >= 0 &&
1017             ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1018                 reg |= 1 << regbits->autoidle_shift;
1019         sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1020 
1021         return 0;
1022 }
1023 
1024 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1025                                                       struct sysc *ddata)
1026 {
1027         struct ti_sysc_platform_data *pdata;
1028         int error;
1029 
1030         pdata = dev_get_platdata(ddata->dev);
1031         if (!pdata)
1032                 return 0;
1033 
1034         if (!pdata->idle_module)
1035                 return -ENODEV;
1036 
1037         error = pdata->idle_module(dev, &ddata->cookie);
1038         if (error)
1039                 dev_err(dev, "%s: could not idle: %i\n",
1040                         __func__, error);
1041 
1042         reset_control_assert(ddata->rsts);
1043 
1044         return 0;
1045 }
1046 
1047 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1048                                                      struct sysc *ddata)
1049 {
1050         struct ti_sysc_platform_data *pdata;
1051         int error;
1052 
1053         reset_control_deassert(ddata->rsts);
1054 
1055         pdata = dev_get_platdata(ddata->dev);
1056         if (!pdata)
1057                 return 0;
1058 
1059         if (!pdata->enable_module)
1060                 return -ENODEV;
1061 
1062         error = pdata->enable_module(dev, &ddata->cookie);
1063         if (error)
1064                 dev_err(dev, "%s: could not enable: %i\n",
1065                         __func__, error);
1066 
1067         return 0;
1068 }
1069 
1070 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1071 {
1072         struct sysc *ddata;
1073         int error = 0;
1074 
1075         ddata = dev_get_drvdata(dev);
1076 
1077         if (!ddata->enabled)
1078                 return 0;
1079 
1080         sysc_clkdm_deny_idle(ddata);
1081 
1082         if (ddata->legacy_mode) {
1083                 error = sysc_runtime_suspend_legacy(dev, ddata);
1084                 if (error)
1085                         goto err_allow_idle;
1086         } else {
1087                 error = sysc_disable_module(dev);
1088                 if (error)
1089                         goto err_allow_idle;
1090         }
1091 
1092         sysc_disable_main_clocks(ddata);
1093 
1094         if (sysc_opt_clks_needed(ddata))
1095                 sysc_disable_opt_clocks(ddata);
1096 
1097         ddata->enabled = false;
1098 
1099 err_allow_idle:
1100         reset_control_assert(ddata->rsts);
1101 
1102         sysc_clkdm_allow_idle(ddata);
1103 
1104         return error;
1105 }
1106 
1107 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1108 {
1109         struct sysc *ddata;
1110         int error = 0;
1111 
1112         ddata = dev_get_drvdata(dev);
1113 
1114         if (ddata->enabled)
1115                 return 0;
1116 
1117 
1118         sysc_clkdm_deny_idle(ddata);
1119 
1120         reset_control_deassert(ddata->rsts);
1121 
1122         if (sysc_opt_clks_needed(ddata)) {
1123                 error = sysc_enable_opt_clocks(ddata);
1124                 if (error)
1125                         goto err_allow_idle;
1126         }
1127 
1128         error = sysc_enable_main_clocks(ddata);
1129         if (error)
1130                 goto err_opt_clocks;
1131 
1132         if (ddata->legacy_mode) {
1133                 error = sysc_runtime_resume_legacy(dev, ddata);
1134                 if (error)
1135                         goto err_main_clocks;
1136         } else {
1137                 error = sysc_enable_module(dev);
1138                 if (error)
1139                         goto err_main_clocks;
1140         }
1141 
1142         ddata->enabled = true;
1143 
1144         sysc_clkdm_allow_idle(ddata);
1145 
1146         return 0;
1147 
1148 err_main_clocks:
1149         sysc_disable_main_clocks(ddata);
1150 err_opt_clocks:
1151         if (sysc_opt_clks_needed(ddata))
1152                 sysc_disable_opt_clocks(ddata);
1153 err_allow_idle:
1154         sysc_clkdm_allow_idle(ddata);
1155 
1156         return error;
1157 }
1158 
1159 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1160 {
1161         struct sysc *ddata;
1162 
1163         ddata = dev_get_drvdata(dev);
1164 
1165         if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1166                 return 0;
1167 
1168         return pm_runtime_force_suspend(dev);
1169 }
1170 
1171 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1172 {
1173         struct sysc *ddata;
1174 
1175         ddata = dev_get_drvdata(dev);
1176 
1177         if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1178                 return 0;
1179 
1180         return pm_runtime_force_resume(dev);
1181 }
1182 
1183 static const struct dev_pm_ops sysc_pm_ops = {
1184         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1185         SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1186                            sysc_runtime_resume,
1187                            NULL)
1188 };
1189 
1190 /* Module revision register based quirks */
1191 struct sysc_revision_quirk {
1192         const char *name;
1193         u32 base;
1194         int rev_offset;
1195         int sysc_offset;
1196         int syss_offset;
1197         u32 revision;
1198         u32 revision_mask;
1199         u32 quirks;
1200 };
1201 
1202 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss,          \
1203                    optrev_val, optrevmask, optquirkmask)                \
1204         {                                                               \
1205                 .name = (optname),                                      \
1206                 .base = (optbase),                                      \
1207                 .rev_offset = (optrev),                                 \
1208                 .sysc_offset = (optsysc),                               \
1209                 .syss_offset = (optsyss),                               \
1210                 .revision = (optrev_val),                               \
1211                 .revision_mask = (optrevmask),                          \
1212                 .quirks = (optquirkmask),                               \
1213         }
1214 
1215 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1216         /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1217         SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1218                    SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1219         SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1220                    SYSC_QUIRK_LEGACY_IDLE),
1221         SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1222                    SYSC_QUIRK_LEGACY_IDLE),
1223         SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1224                    SYSC_QUIRK_LEGACY_IDLE),
1225         SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1226                    SYSC_QUIRK_LEGACY_IDLE),
1227         SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1228                    SYSC_QUIRK_LEGACY_IDLE),
1229         SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1230                    0),
1231         /* Some timers on omap4 and later */
1232         SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
1233                    0),
1234         SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
1235                    0),
1236         SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1237                    SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1238         SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1239                    SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1240         /* Uarts on omap4 and later */
1241         SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1242                    SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1243         SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1244                    SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1245 
1246         /* Quirks that need to be set based on the module address */
1247         SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1248                    SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1249                    SYSC_QUIRK_SWSUP_SIDLE),
1250 
1251         /* Quirks that need to be set based on detected module */
1252         SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff,
1253                    SYSC_MODULE_QUIRK_AESS),
1254         SYSC_QUIRK("dcan", 0x48480000, 0x20, -1, -1, 0xa3170504, 0xffffffff,
1255                    SYSC_QUIRK_CLKDM_NOAUTO),
1256         SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -1, 0x500a0200, 0xffffffff,
1257                    SYSC_QUIRK_CLKDM_NOAUTO),
1258         SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -1, 0x500a0200, 0xffffffff,
1259                    SYSC_QUIRK_CLKDM_NOAUTO),
1260         SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1261                    SYSC_MODULE_QUIRK_HDQ1W),
1262         SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1263                    SYSC_MODULE_QUIRK_HDQ1W),
1264         SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1265                    SYSC_MODULE_QUIRK_I2C),
1266         SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1267                    SYSC_MODULE_QUIRK_I2C),
1268         SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1269                    SYSC_MODULE_QUIRK_I2C),
1270         SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1271                    SYSC_MODULE_QUIRK_I2C),
1272         SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1273         SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1274                    SYSC_MODULE_QUIRK_SGX),
1275         SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1276                    0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1277         SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff,
1278                    SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1279         SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1280                    SYSC_MODULE_QUIRK_WDT),
1281         /* Watchdog on am3 and am4 */
1282         SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1283                    SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1284 
1285 #ifdef DEBUG
1286         SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
1287         SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
1288         SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
1289         SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1290         SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1291                    0xffff00f0, 0),
1292         SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1293         SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
1294         SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1295         SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1296         SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1297         SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1298         SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
1299         SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1300         SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
1301         SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1302         SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
1303         SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
1304         SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1305         SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
1306         SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
1307         SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1308         SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1309         SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1310         SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
1311         SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1312         SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
1313         SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
1314         SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
1315         SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
1316         SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1317         SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
1318         SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1319         SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1320         SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
1321         SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
1322         SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
1323         SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1324         SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1325         SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1326         SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1327         SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1328         SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1329         SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
1330         SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1331         SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
1332         SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1333         SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1334         SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1335         SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1336         SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
1337 #endif
1338 };
1339 
1340 /*
1341  * Early quirks based on module base and register offsets only that are
1342  * needed before the module revision can be read
1343  */
1344 static void sysc_init_early_quirks(struct sysc *ddata)
1345 {
1346         const struct sysc_revision_quirk *q;
1347         int i;
1348 
1349         for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1350                 q = &sysc_revision_quirks[i];
1351 
1352                 if (!q->base)
1353                         continue;
1354 
1355                 if (q->base != ddata->module_pa)
1356                         continue;
1357 
1358                 if (q->rev_offset >= 0 &&
1359                     q->rev_offset != ddata->offsets[SYSC_REVISION])
1360                         continue;
1361 
1362                 if (q->sysc_offset >= 0 &&
1363                     q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1364                         continue;
1365 
1366                 if (q->syss_offset >= 0 &&
1367                     q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1368                         continue;
1369 
1370                 ddata->name = q->name;
1371                 ddata->cfg.quirks |= q->quirks;
1372         }
1373 }
1374 
1375 /* Quirks that also consider the revision register value */
1376 static void sysc_init_revision_quirks(struct sysc *ddata)
1377 {
1378         const struct sysc_revision_quirk *q;
1379         int i;
1380 
1381         for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1382                 q = &sysc_revision_quirks[i];
1383 
1384                 if (q->base && q->base != ddata->module_pa)
1385                         continue;
1386 
1387                 if (q->rev_offset >= 0 &&
1388                     q->rev_offset != ddata->offsets[SYSC_REVISION])
1389                         continue;
1390 
1391                 if (q->sysc_offset >= 0 &&
1392                     q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1393                         continue;
1394 
1395                 if (q->syss_offset >= 0 &&
1396                     q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1397                         continue;
1398 
1399                 if (q->revision == ddata->revision ||
1400                     (q->revision & q->revision_mask) ==
1401                     (ddata->revision & q->revision_mask)) {
1402                         ddata->name = q->name;
1403                         ddata->cfg.quirks |= q->quirks;
1404                 }
1405         }
1406 }
1407 
1408 /* 1-wire needs module's internal clocks enabled for reset */
1409 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1410 {
1411         int offset = 0x0c;      /* HDQ_CTRL_STATUS */
1412         u16 val;
1413 
1414         val = sysc_read(ddata, offset);
1415         val |= BIT(5);
1416         sysc_write(ddata, offset, val);
1417 }
1418 
1419 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1420 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1421 {
1422         int offset = 0x7c;      /* AESS_AUTO_GATING_ENABLE */
1423 
1424         sysc_write(ddata, offset, 1);
1425 }
1426 
1427 /* I2C needs extra enable bit toggling for reset */
1428 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1429 {
1430         int offset;
1431         u16 val;
1432 
1433         /* I2C_CON, omap2/3 is different from omap4 and later */
1434         if ((ddata->revision & 0xffffff00) == 0x001f0000)
1435                 offset = 0x24;
1436         else
1437                 offset = 0xa4;
1438 
1439         /* I2C_EN */
1440         val = sysc_read(ddata, offset);
1441         if (enable)
1442                 val |= BIT(15);
1443         else
1444                 val &= ~BIT(15);
1445         sysc_write(ddata, offset, val);
1446 }
1447 
1448 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1449 {
1450         sysc_clk_quirk_i2c(ddata, true);
1451 }
1452 
1453 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1454 {
1455         sysc_clk_quirk_i2c(ddata, false);
1456 }
1457 
1458 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1459 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1460 {
1461         int offset = 0xff08;    /* OCP_DEBUG_CONFIG */
1462         u32 val = BIT(31);      /* THALIA_INT_BYPASS */
1463 
1464         sysc_write(ddata, offset, val);
1465 }
1466 
1467 /* Watchdog timer needs a disable sequence after reset */
1468 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1469 {
1470         int wps, spr, error;
1471         u32 val;
1472 
1473         wps = 0x34;
1474         spr = 0x48;
1475 
1476         sysc_write(ddata, spr, 0xaaaa);
1477         error = readl_poll_timeout(ddata->module_va + wps, val,
1478                                    !(val & 0x10), 100,
1479                                    MAX_MODULE_SOFTRESET_WAIT);
1480         if (error)
1481                 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1482 
1483         sysc_write(ddata, spr, 0x5555);
1484         error = readl_poll_timeout(ddata->module_va + wps, val,
1485                                    !(val & 0x10), 100,
1486                                    MAX_MODULE_SOFTRESET_WAIT);
1487         if (error)
1488                 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1489 }
1490 
1491 static void sysc_init_module_quirks(struct sysc *ddata)
1492 {
1493         if (ddata->legacy_mode || !ddata->name)
1494                 return;
1495 
1496         if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1497                 ddata->clk_disable_quirk = sysc_pre_reset_quirk_hdq1w;
1498 
1499                 return;
1500         }
1501 
1502         if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1503                 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1504                 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1505 
1506                 return;
1507         }
1508 
1509         if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1510                 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1511 
1512         if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1513                 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1514 
1515         if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1516                 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1517                 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1518         }
1519 }
1520 
1521 static int sysc_clockdomain_init(struct sysc *ddata)
1522 {
1523         struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1524         struct clk *fck = NULL, *ick = NULL;
1525         int error;
1526 
1527         if (!pdata || !pdata->init_clockdomain)
1528                 return 0;
1529 
1530         switch (ddata->nr_clocks) {
1531         case 2:
1532                 ick = ddata->clocks[SYSC_ICK];
1533                 /* fallthrough */
1534         case 1:
1535                 fck = ddata->clocks[SYSC_FCK];
1536                 break;
1537         case 0:
1538                 return 0;
1539         }
1540 
1541         error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1542         if (!error || error == -ENODEV)
1543                 return 0;
1544 
1545         return error;
1546 }
1547 
1548 /*
1549  * Note that pdata->init_module() typically does a reset first. After
1550  * pdata->init_module() is done, PM runtime can be used for the interconnect
1551  * target module.
1552  */
1553 static int sysc_legacy_init(struct sysc *ddata)
1554 {
1555         struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1556         int error;
1557 
1558         if (!pdata || !pdata->init_module)
1559                 return 0;
1560 
1561         error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1562         if (error == -EEXIST)
1563                 error = 0;
1564 
1565         return error;
1566 }
1567 
1568 /**
1569  * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1570  * @ddata: device driver data
1571  * @reset: reset before deassert
1572  *
1573  * A module can have both OCP softreset control and external rstctrl.
1574  * If more complicated rstctrl resets are needed, please handle these
1575  * directly from the child device driver and map only the module reset
1576  * for the parent interconnect target module device.
1577  *
1578  * Automatic reset of the module on init can be skipped with the
1579  * "ti,no-reset-on-init" device tree property.
1580  */
1581 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1582 {
1583         int error;
1584 
1585         if (!ddata->rsts)
1586                 return 0;
1587 
1588         if (reset) {
1589                 error = reset_control_assert(ddata->rsts);
1590                 if (error)
1591                         return error;
1592         }
1593 
1594         reset_control_deassert(ddata->rsts);
1595 
1596         return 0;
1597 }
1598 
1599 /*
1600  * Note that the caller must ensure the interconnect target module is enabled
1601  * before calling reset. Otherwise reset will not complete.
1602  */
1603 static int sysc_reset(struct sysc *ddata)
1604 {
1605         int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
1606         u32 sysc_mask, syss_done;
1607 
1608         sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1609         syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1610 
1611         if (ddata->legacy_mode || sysc_offset < 0 ||
1612             ddata->cap->regbits->srst_shift < 0 ||
1613             ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1614                 return 0;
1615 
1616         sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1617 
1618         if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1619                 syss_done = 0;
1620         else
1621                 syss_done = ddata->cfg.syss_mask;
1622 
1623         if (ddata->clk_disable_quirk)
1624                 ddata->clk_disable_quirk(ddata);
1625 
1626         sysc_val = sysc_read_sysconfig(ddata);
1627         sysc_val |= sysc_mask;
1628         sysc_write(ddata, sysc_offset, sysc_val);
1629 
1630         if (ddata->cfg.srst_udelay)
1631                 usleep_range(ddata->cfg.srst_udelay,
1632                              ddata->cfg.srst_udelay * 2);
1633 
1634         if (ddata->clk_enable_quirk)
1635                 ddata->clk_enable_quirk(ddata);
1636 
1637         /* Poll on reset status */
1638         if (syss_offset >= 0) {
1639                 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1640                                            (rstval & ddata->cfg.syss_mask) ==
1641                                            syss_done,
1642                                            100, MAX_MODULE_SOFTRESET_WAIT);
1643 
1644         } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1645                 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1646                                            !(rstval & sysc_mask),
1647                                            100, MAX_MODULE_SOFTRESET_WAIT);
1648         }
1649 
1650         if (ddata->reset_done_quirk)
1651                 ddata->reset_done_quirk(ddata);
1652 
1653         return error;
1654 }
1655 
1656 /*
1657  * At this point the module is configured enough to read the revision but
1658  * module may not be completely configured yet to use PM runtime. Enable
1659  * all clocks directly during init to configure the quirks needed for PM
1660  * runtime based on the revision register.
1661  */
1662 static int sysc_init_module(struct sysc *ddata)
1663 {
1664         int error = 0;
1665         bool manage_clocks = true;
1666 
1667         error = sysc_rstctrl_reset_deassert(ddata, false);
1668         if (error)
1669                 return error;
1670 
1671         if (ddata->cfg.quirks &
1672             (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1673                 manage_clocks = false;
1674 
1675         error = sysc_clockdomain_init(ddata);
1676         if (error)
1677                 return error;
1678 
1679         sysc_clkdm_deny_idle(ddata);
1680 
1681         /*
1682          * Always enable clocks. The bootloader may or may not have enabled
1683          * the related clocks.
1684          */
1685         error = sysc_enable_opt_clocks(ddata);
1686         if (error)
1687                 return error;
1688 
1689         error = sysc_enable_main_clocks(ddata);
1690         if (error)
1691                 goto err_opt_clocks;
1692 
1693         if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1694                 error = sysc_rstctrl_reset_deassert(ddata, true);
1695                 if (error)
1696                         goto err_main_clocks;
1697         }
1698 
1699         ddata->revision = sysc_read_revision(ddata);
1700         sysc_init_revision_quirks(ddata);
1701         sysc_init_module_quirks(ddata);
1702 
1703         if (ddata->legacy_mode) {
1704                 error = sysc_legacy_init(ddata);
1705                 if (error)
1706                         goto err_main_clocks;
1707         }
1708 
1709         if (!ddata->legacy_mode) {
1710                 error = sysc_enable_module(ddata->dev);
1711                 if (error)
1712                         goto err_main_clocks;
1713         }
1714 
1715         error = sysc_reset(ddata);
1716         if (error)
1717                 dev_err(ddata->dev, "Reset failed with %d\n", error);
1718 
1719         if (!ddata->legacy_mode && manage_clocks)
1720                 sysc_disable_module(ddata->dev);
1721 
1722 err_main_clocks:
1723         if (manage_clocks)
1724                 sysc_disable_main_clocks(ddata);
1725 err_opt_clocks:
1726         /* No re-enable of clockdomain autoidle to prevent module autoidle */
1727         if (manage_clocks) {
1728                 sysc_disable_opt_clocks(ddata);
1729                 sysc_clkdm_allow_idle(ddata);
1730         }
1731 
1732         return error;
1733 }
1734 
1735 static int sysc_init_sysc_mask(struct sysc *ddata)
1736 {
1737         struct device_node *np = ddata->dev->of_node;
1738         int error;
1739         u32 val;
1740 
1741         error = of_property_read_u32(np, "ti,sysc-mask", &val);
1742         if (error)
1743                 return 0;
1744 
1745         ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1746 
1747         return 0;
1748 }
1749 
1750 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1751                               const char *name)
1752 {
1753         struct device_node *np = ddata->dev->of_node;
1754         struct property *prop;
1755         const __be32 *p;
1756         u32 val;
1757 
1758         of_property_for_each_u32(np, name, prop, p, val) {
1759                 if (val >= SYSC_NR_IDLEMODES) {
1760                         dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1761                         return -EINVAL;
1762                 }
1763                 *idlemodes |=  (1 << val);
1764         }
1765 
1766         return 0;
1767 }
1768 
1769 static int sysc_init_idlemodes(struct sysc *ddata)
1770 {
1771         int error;
1772 
1773         error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1774                                    "ti,sysc-midle");
1775         if (error)
1776                 return error;
1777 
1778         error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1779                                    "ti,sysc-sidle");
1780         if (error)
1781                 return error;
1782 
1783         return 0;
1784 }
1785 
1786 /*
1787  * Only some devices on omap4 and later have SYSCONFIG reset done
1788  * bit. We can detect this if there is no SYSSTATUS at all, or the
1789  * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1790  * have multiple bits for the child devices like OHCI and EHCI.
1791  * Depends on SYSC being parsed first.
1792  */
1793 static int sysc_init_syss_mask(struct sysc *ddata)
1794 {
1795         struct device_node *np = ddata->dev->of_node;
1796         int error;
1797         u32 val;
1798 
1799         error = of_property_read_u32(np, "ti,syss-mask", &val);
1800         if (error) {
1801                 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1802                      ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1803                     (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1804                         ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1805 
1806                 return 0;
1807         }
1808 
1809         if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1810                 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1811 
1812         ddata->cfg.syss_mask = val;
1813 
1814         return 0;
1815 }
1816 
1817 /*
1818  * Many child device drivers need to have fck and opt clocks available
1819  * to get the clock rate for device internal configuration etc.
1820  */
1821 static int sysc_child_add_named_clock(struct sysc *ddata,
1822                                       struct device *child,
1823                                       const char *name)
1824 {
1825         struct clk *clk;
1826         struct clk_lookup *l;
1827         int error = 0;
1828 
1829         if (!name)
1830                 return 0;
1831 
1832         clk = clk_get(child, name);
1833         if (!IS_ERR(clk)) {
1834                 clk_put(clk);
1835 
1836                 return -EEXIST;
1837         }
1838 
1839         clk = clk_get(ddata->dev, name);
1840         if (IS_ERR(clk))
1841                 return -ENODEV;
1842 
1843         l = clkdev_create(clk, name, dev_name(child));
1844         if (!l)
1845                 error = -ENOMEM;
1846 
1847         clk_put(clk);
1848 
1849         return error;
1850 }
1851 
1852 static int sysc_child_add_clocks(struct sysc *ddata,
1853                                  struct device *child)
1854 {
1855         int i, error;
1856 
1857         for (i = 0; i < ddata->nr_clocks; i++) {
1858                 error = sysc_child_add_named_clock(ddata,
1859                                                    child,
1860                                                    ddata->clock_roles[i]);
1861                 if (error && error != -EEXIST) {
1862                         dev_err(ddata->dev, "could not add child clock %s: %i\n",
1863                                 ddata->clock_roles[i], error);
1864 
1865                         return error;
1866                 }
1867         }
1868 
1869         return 0;
1870 }
1871 
1872 static struct device_type sysc_device_type = {
1873 };
1874 
1875 static struct sysc *sysc_child_to_parent(struct device *dev)
1876 {
1877         struct device *parent = dev->parent;
1878 
1879         if (!parent || parent->type != &sysc_device_type)
1880                 return NULL;
1881 
1882         return dev_get_drvdata(parent);
1883 }
1884 
1885 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1886 {
1887         struct sysc *ddata;
1888         int error;
1889 
1890         ddata = sysc_child_to_parent(dev);
1891 
1892         error = pm_generic_runtime_suspend(dev);
1893         if (error)
1894                 return error;
1895 
1896         if (!ddata->enabled)
1897                 return 0;
1898 
1899         return sysc_runtime_suspend(ddata->dev);
1900 }
1901 
1902 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1903 {
1904         struct sysc *ddata;
1905         int error;
1906 
1907         ddata = sysc_child_to_parent(dev);
1908 
1909         if (!ddata->enabled) {
1910                 error = sysc_runtime_resume(ddata->dev);
1911                 if (error < 0)
1912                         dev_err(ddata->dev,
1913                                 "%s error: %i\n", __func__, error);
1914         }
1915 
1916         return pm_generic_runtime_resume(dev);
1917 }
1918 
1919 #ifdef CONFIG_PM_SLEEP
1920 static int sysc_child_suspend_noirq(struct device *dev)
1921 {
1922         struct sysc *ddata;
1923         int error;
1924 
1925         ddata = sysc_child_to_parent(dev);
1926 
1927         dev_dbg(ddata->dev, "%s %s\n", __func__,
1928                 ddata->name ? ddata->name : "");
1929 
1930         error = pm_generic_suspend_noirq(dev);
1931         if (error) {
1932                 dev_err(dev, "%s error at %i: %i\n",
1933                         __func__, __LINE__, error);
1934 
1935                 return error;
1936         }
1937 
1938         if (!pm_runtime_status_suspended(dev)) {
1939                 error = pm_generic_runtime_suspend(dev);
1940                 if (error) {
1941                         dev_dbg(dev, "%s busy at %i: %i\n",
1942                                 __func__, __LINE__, error);
1943 
1944                         return 0;
1945                 }
1946 
1947                 error = sysc_runtime_suspend(ddata->dev);
1948                 if (error) {
1949                         dev_err(dev, "%s error at %i: %i\n",
1950                                 __func__, __LINE__, error);
1951 
1952                         return error;
1953                 }
1954 
1955                 ddata->child_needs_resume = true;
1956         }
1957 
1958         return 0;
1959 }
1960 
1961 static int sysc_child_resume_noirq(struct device *dev)
1962 {
1963         struct sysc *ddata;
1964         int error;
1965 
1966         ddata = sysc_child_to_parent(dev);
1967 
1968         dev_dbg(ddata->dev, "%s %s\n", __func__,
1969                 ddata->name ? ddata->name : "");
1970 
1971         if (ddata->child_needs_resume) {
1972                 ddata->child_needs_resume = false;
1973 
1974                 error = sysc_runtime_resume(ddata->dev);
1975                 if (error)
1976                         dev_err(ddata->dev,
1977                                 "%s runtime resume error: %i\n",
1978                                 __func__, error);
1979 
1980                 error = pm_generic_runtime_resume(dev);
1981                 if (error)
1982                         dev_err(ddata->dev,
1983                                 "%s generic runtime resume: %i\n",
1984                                 __func__, error);
1985         }
1986 
1987         return pm_generic_resume_noirq(dev);
1988 }
1989 #endif
1990 
1991 static struct dev_pm_domain sysc_child_pm_domain = {
1992         .ops = {
1993                 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1994                                    sysc_child_runtime_resume,
1995                                    NULL)
1996                 USE_PLATFORM_PM_SLEEP_OPS
1997                 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1998                                               sysc_child_resume_noirq)
1999         }
2000 };
2001 
2002 /**
2003  * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2004  * @ddata: device driver data
2005  * @child: child device driver
2006  *
2007  * Allow idle for child devices as done with _od_runtime_suspend().
2008  * Otherwise many child devices will not idle because of the permanent
2009  * parent usecount set in pm_runtime_irq_safe().
2010  *
2011  * Note that the long term solution is to just modify the child device
2012  * drivers to not set pm_runtime_irq_safe() and then this can be just
2013  * dropped.
2014  */
2015 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2016 {
2017         if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2018                 dev_pm_domain_set(child, &sysc_child_pm_domain);
2019 }
2020 
2021 static int sysc_notifier_call(struct notifier_block *nb,
2022                               unsigned long event, void *device)
2023 {
2024         struct device *dev = device;
2025         struct sysc *ddata;
2026         int error;
2027 
2028         ddata = sysc_child_to_parent(dev);
2029         if (!ddata)
2030                 return NOTIFY_DONE;
2031 
2032         switch (event) {
2033         case BUS_NOTIFY_ADD_DEVICE:
2034                 error = sysc_child_add_clocks(ddata, dev);
2035                 if (error)
2036                         return error;
2037                 sysc_legacy_idle_quirk(ddata, dev);
2038                 break;
2039         default:
2040                 break;
2041         }
2042 
2043         return NOTIFY_DONE;
2044 }
2045 
2046 static struct notifier_block sysc_nb = {
2047         .notifier_call = sysc_notifier_call,
2048 };
2049 
2050 /* Device tree configured quirks */
2051 struct sysc_dts_quirk {
2052         const char *name;
2053         u32 mask;
2054 };
2055 
2056 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2057         { .name = "ti,no-idle-on-init",
2058           .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2059         { .name = "ti,no-reset-on-init",
2060           .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2061         { .name = "ti,no-idle",
2062           .mask = SYSC_QUIRK_NO_IDLE, },
2063 };
2064 
2065 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2066                                   bool is_child)
2067 {
2068         const struct property *prop;
2069         int i, len;
2070 
2071         for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2072                 const char *name = sysc_dts_quirks[i].name;
2073 
2074                 prop = of_get_property(np, name, &len);
2075                 if (!prop)
2076                         continue;
2077 
2078                 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2079                 if (is_child) {
2080                         dev_warn(ddata->dev,
2081                                  "dts flag should be at module level for %s\n",
2082                                  name);
2083                 }
2084         }
2085 }
2086 
2087 static int sysc_init_dts_quirks(struct sysc *ddata)
2088 {
2089         struct device_node *np = ddata->dev->of_node;
2090         int error;
2091         u32 val;
2092 
2093         ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2094 
2095         sysc_parse_dts_quirks(ddata, np, false);
2096         error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2097         if (!error) {
2098                 if (val > 255) {
2099                         dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2100                                  val);
2101                 }
2102 
2103                 ddata->cfg.srst_udelay = (u8)val;
2104         }
2105 
2106         return 0;
2107 }
2108 
2109 static void sysc_unprepare(struct sysc *ddata)
2110 {
2111         int i;
2112 
2113         if (!ddata->clocks)
2114                 return;
2115 
2116         for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2117                 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2118                         clk_unprepare(ddata->clocks[i]);
2119         }
2120 }
2121 
2122 /*
2123  * Common sysc register bits found on omap2, also known as type1
2124  */
2125 static const struct sysc_regbits sysc_regbits_omap2 = {
2126         .dmadisable_shift = -ENODEV,
2127         .midle_shift = 12,
2128         .sidle_shift = 3,
2129         .clkact_shift = 8,
2130         .emufree_shift = 5,
2131         .enwkup_shift = 2,
2132         .srst_shift = 1,
2133         .autoidle_shift = 0,
2134 };
2135 
2136 static const struct sysc_capabilities sysc_omap2 = {
2137         .type = TI_SYSC_OMAP2,
2138         .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2139                      SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2140                      SYSC_OMAP2_AUTOIDLE,
2141         .regbits = &sysc_regbits_omap2,
2142 };
2143 
2144 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2145 static const struct sysc_capabilities sysc_omap2_timer = {
2146         .type = TI_SYSC_OMAP2_TIMER,
2147         .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2148                      SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2149                      SYSC_OMAP2_AUTOIDLE,
2150         .regbits = &sysc_regbits_omap2,
2151         .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2152 };
2153 
2154 /*
2155  * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2156  * with different sidle position
2157  */
2158 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2159         .dmadisable_shift = -ENODEV,
2160         .midle_shift = -ENODEV,
2161         .sidle_shift = 4,
2162         .clkact_shift = -ENODEV,
2163         .enwkup_shift = -ENODEV,
2164         .srst_shift = 1,
2165         .autoidle_shift = 0,
2166         .emufree_shift = -ENODEV,
2167 };
2168 
2169 static const struct sysc_capabilities sysc_omap3_sham = {
2170         .type = TI_SYSC_OMAP3_SHAM,
2171         .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2172         .regbits = &sysc_regbits_omap3_sham,
2173 };
2174 
2175 /*
2176  * AES register bits found on omap3 and later, a variant of
2177  * sysc_regbits_omap2 with different sidle position
2178  */
2179 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2180         .dmadisable_shift = -ENODEV,
2181         .midle_shift = -ENODEV,
2182         .sidle_shift = 6,
2183         .clkact_shift = -ENODEV,
2184         .enwkup_shift = -ENODEV,
2185         .srst_shift = 1,
2186         .autoidle_shift = 0,
2187         .emufree_shift = -ENODEV,
2188 };
2189 
2190 static const struct sysc_capabilities sysc_omap3_aes = {
2191         .type = TI_SYSC_OMAP3_AES,
2192         .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2193         .regbits = &sysc_regbits_omap3_aes,
2194 };
2195 
2196 /*
2197  * Common sysc register bits found on omap4, also known as type2
2198  */
2199 static const struct sysc_regbits sysc_regbits_omap4 = {
2200         .dmadisable_shift = 16,
2201         .midle_shift = 4,
2202         .sidle_shift = 2,
2203         .clkact_shift = -ENODEV,
2204         .enwkup_shift = -ENODEV,
2205         .emufree_shift = 1,
2206         .srst_shift = 0,
2207         .autoidle_shift = -ENODEV,
2208 };
2209 
2210 static const struct sysc_capabilities sysc_omap4 = {
2211         .type = TI_SYSC_OMAP4,
2212         .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2213                      SYSC_OMAP4_SOFTRESET,
2214         .regbits = &sysc_regbits_omap4,
2215 };
2216 
2217 static const struct sysc_capabilities sysc_omap4_timer = {
2218         .type = TI_SYSC_OMAP4_TIMER,
2219         .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2220                      SYSC_OMAP4_SOFTRESET,
2221         .regbits = &sysc_regbits_omap4,
2222 };
2223 
2224 /*
2225  * Common sysc register bits found on omap4, also known as type3
2226  */
2227 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2228         .dmadisable_shift = -ENODEV,
2229         .midle_shift = 2,
2230         .sidle_shift = 0,
2231         .clkact_shift = -ENODEV,
2232         .enwkup_shift = -ENODEV,
2233         .srst_shift = -ENODEV,
2234         .emufree_shift = -ENODEV,
2235         .autoidle_shift = -ENODEV,
2236 };
2237 
2238 static const struct sysc_capabilities sysc_omap4_simple = {
2239         .type = TI_SYSC_OMAP4_SIMPLE,
2240         .regbits = &sysc_regbits_omap4_simple,
2241 };
2242 
2243 /*
2244  * SmartReflex sysc found on omap34xx
2245  */
2246 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2247         .dmadisable_shift = -ENODEV,
2248         .midle_shift = -ENODEV,
2249         .sidle_shift = -ENODEV,
2250         .clkact_shift = 20,
2251         .enwkup_shift = -ENODEV,
2252         .srst_shift = -ENODEV,
2253         .emufree_shift = -ENODEV,
2254         .autoidle_shift = -ENODEV,
2255 };
2256 
2257 static const struct sysc_capabilities sysc_34xx_sr = {
2258         .type = TI_SYSC_OMAP34XX_SR,
2259         .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2260         .regbits = &sysc_regbits_omap34xx_sr,
2261         .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2262                       SYSC_QUIRK_LEGACY_IDLE,
2263 };
2264 
2265 /*
2266  * SmartReflex sysc found on omap36xx and later
2267  */
2268 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2269         .dmadisable_shift = -ENODEV,
2270         .midle_shift = -ENODEV,
2271         .sidle_shift = 24,
2272         .clkact_shift = -ENODEV,
2273         .enwkup_shift = 26,
2274         .srst_shift = -ENODEV,
2275         .emufree_shift = -ENODEV,
2276         .autoidle_shift = -ENODEV,
2277 };
2278 
2279 static const struct sysc_capabilities sysc_36xx_sr = {
2280         .type = TI_SYSC_OMAP36XX_SR,
2281         .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2282         .regbits = &sysc_regbits_omap36xx_sr,
2283         .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2284 };
2285 
2286 static const struct sysc_capabilities sysc_omap4_sr = {
2287         .type = TI_SYSC_OMAP4_SR,
2288         .regbits = &sysc_regbits_omap36xx_sr,
2289         .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2290 };
2291 
2292 /*
2293  * McASP register bits found on omap4 and later
2294  */
2295 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2296         .dmadisable_shift = -ENODEV,
2297         .midle_shift = -ENODEV,
2298         .sidle_shift = 0,
2299         .clkact_shift = -ENODEV,
2300         .enwkup_shift = -ENODEV,
2301         .srst_shift = -ENODEV,
2302         .emufree_shift = -ENODEV,
2303         .autoidle_shift = -ENODEV,
2304 };
2305 
2306 static const struct sysc_capabilities sysc_omap4_mcasp = {
2307         .type = TI_SYSC_OMAP4_MCASP,
2308         .regbits = &sysc_regbits_omap4_mcasp,
2309         .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2310 };
2311 
2312 /*
2313  * McASP found on dra7 and later
2314  */
2315 static const struct sysc_capabilities sysc_dra7_mcasp = {
2316         .type = TI_SYSC_OMAP4_SIMPLE,
2317         .regbits = &sysc_regbits_omap4_simple,
2318         .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2319 };
2320 
2321 /*
2322  * FS USB host found on omap4 and later
2323  */
2324 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2325         .dmadisable_shift = -ENODEV,
2326         .midle_shift = -ENODEV,
2327         .sidle_shift = 24,
2328         .clkact_shift = -ENODEV,
2329         .enwkup_shift = 26,
2330         .srst_shift = -ENODEV,
2331         .emufree_shift = -ENODEV,
2332         .autoidle_shift = -ENODEV,
2333 };
2334 
2335 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2336         .type = TI_SYSC_OMAP4_USB_HOST_FS,
2337         .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2338         .regbits = &sysc_regbits_omap4_usb_host_fs,
2339 };
2340 
2341 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2342         .dmadisable_shift = -ENODEV,
2343         .midle_shift = -ENODEV,
2344         .sidle_shift = -ENODEV,
2345         .clkact_shift = -ENODEV,
2346         .enwkup_shift = 4,
2347         .srst_shift = 0,
2348         .emufree_shift = -ENODEV,
2349         .autoidle_shift = -ENODEV,
2350 };
2351 
2352 static const struct sysc_capabilities sysc_dra7_mcan = {
2353         .type = TI_SYSC_DRA7_MCAN,
2354         .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2355         .regbits = &sysc_regbits_dra7_mcan,
2356         .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2357 };
2358 
2359 static int sysc_init_pdata(struct sysc *ddata)
2360 {
2361         struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2362         struct ti_sysc_module_data *mdata;
2363 
2364         if (!pdata)
2365                 return 0;
2366 
2367         mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2368         if (!mdata)
2369                 return -ENOMEM;
2370 
2371         if (ddata->legacy_mode) {
2372                 mdata->name = ddata->legacy_mode;
2373                 mdata->module_pa = ddata->module_pa;
2374                 mdata->module_size = ddata->module_size;
2375                 mdata->offsets = ddata->offsets;
2376                 mdata->nr_offsets = SYSC_MAX_REGS;
2377                 mdata->cap = ddata->cap;
2378                 mdata->cfg = &ddata->cfg;
2379         }
2380 
2381         ddata->mdata = mdata;
2382 
2383         return 0;
2384 }
2385 
2386 static int sysc_init_match(struct sysc *ddata)
2387 {
2388         const struct sysc_capabilities *cap;
2389 
2390         cap = of_device_get_match_data(ddata->dev);
2391         if (!cap)
2392                 return -EINVAL;
2393 
2394         ddata->cap = cap;
2395         if (ddata->cap)
2396                 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2397 
2398         return 0;
2399 }
2400 
2401 static void ti_sysc_idle(struct work_struct *work)
2402 {
2403         struct sysc *ddata;
2404 
2405         ddata = container_of(work, struct sysc, idle_work.work);
2406 
2407         /*
2408          * One time decrement of clock usage counts if left on from init.
2409          * Note that we disable opt clocks unconditionally in this case
2410          * as they are enabled unconditionally during init without
2411          * considering sysc_opt_clks_needed() at that point.
2412          */
2413         if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2414                                  SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2415                 sysc_disable_main_clocks(ddata);
2416                 sysc_disable_opt_clocks(ddata);
2417                 sysc_clkdm_allow_idle(ddata);
2418         }
2419 
2420         /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2421         if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2422                 return;
2423 
2424         /*
2425          * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2426          * and SYSC_QUIRK_NO_RESET_ON_INIT
2427          */
2428         if (pm_runtime_active(ddata->dev))
2429                 pm_runtime_put_sync(ddata->dev);
2430 }
2431 
2432 static const struct of_device_id sysc_match_table[] = {
2433         { .compatible = "simple-bus", },
2434         { /* sentinel */ },
2435 };
2436 
2437 static int sysc_probe(struct platform_device *pdev)
2438 {
2439         struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2440         struct sysc *ddata;
2441         int error;
2442 
2443         ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2444         if (!ddata)
2445                 return -ENOMEM;
2446 
2447         ddata->dev = &pdev->dev;
2448         platform_set_drvdata(pdev, ddata);
2449 
2450         error = sysc_init_match(ddata);
2451         if (error)
2452                 return error;
2453 
2454         error = sysc_init_dts_quirks(ddata);
2455         if (error)
2456                 return error;
2457 
2458         error = sysc_map_and_check_registers(ddata);
2459         if (error)
2460                 return error;
2461 
2462         error = sysc_init_sysc_mask(ddata);
2463         if (error)
2464                 return error;
2465 
2466         error = sysc_init_idlemodes(ddata);
2467         if (error)
2468                 return error;
2469 
2470         error = sysc_init_syss_mask(ddata);
2471         if (error)
2472                 return error;
2473 
2474         error = sysc_init_pdata(ddata);
2475         if (error)
2476                 return error;
2477 
2478         sysc_init_early_quirks(ddata);
2479 
2480         error = sysc_get_clocks(ddata);
2481         if (error)
2482                 return error;
2483 
2484         error = sysc_init_resets(ddata);
2485         if (error)
2486                 goto unprepare;
2487 
2488         error = sysc_init_module(ddata);
2489         if (error)
2490                 goto unprepare;
2491 
2492         pm_runtime_enable(ddata->dev);
2493         error = pm_runtime_get_sync(ddata->dev);
2494         if (error < 0) {
2495                 pm_runtime_put_noidle(ddata->dev);
2496                 pm_runtime_disable(ddata->dev);
2497                 goto unprepare;
2498         }
2499 
2500         /* Balance reset counts */
2501         if (ddata->rsts)
2502                 reset_control_assert(ddata->rsts);
2503 
2504         sysc_show_registers(ddata);
2505 
2506         ddata->dev->type = &sysc_device_type;
2507         error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2508                                      pdata ? pdata->auxdata : NULL,
2509                                      ddata->dev);
2510         if (error)
2511                 goto err;
2512 
2513         INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2514 
2515         /* At least earlycon won't survive without deferred idle */
2516         if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2517                                  SYSC_QUIRK_NO_IDLE_ON_INIT |
2518                                  SYSC_QUIRK_NO_RESET_ON_INIT)) {
2519                 schedule_delayed_work(&ddata->idle_work, 3000);
2520         } else {
2521                 pm_runtime_put(&pdev->dev);
2522         }
2523 
2524         return 0;
2525 
2526 err:
2527         pm_runtime_put_sync(&pdev->dev);
2528         pm_runtime_disable(&pdev->dev);
2529 unprepare:
2530         sysc_unprepare(ddata);
2531 
2532         return error;
2533 }
2534 
2535 static int sysc_remove(struct platform_device *pdev)
2536 {
2537         struct sysc *ddata = platform_get_drvdata(pdev);
2538         int error;
2539 
2540         cancel_delayed_work_sync(&ddata->idle_work);
2541 
2542         error = pm_runtime_get_sync(ddata->dev);
2543         if (error < 0) {
2544                 pm_runtime_put_noidle(ddata->dev);
2545                 pm_runtime_disable(ddata->dev);
2546                 goto unprepare;
2547         }
2548 
2549         of_platform_depopulate(&pdev->dev);
2550 
2551         pm_runtime_put_sync(&pdev->dev);
2552         pm_runtime_disable(&pdev->dev);
2553         reset_control_assert(ddata->rsts);
2554 
2555 unprepare:
2556         sysc_unprepare(ddata);
2557 
2558         return 0;
2559 }
2560 
2561 static const struct of_device_id sysc_match[] = {
2562         { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2563         { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2564         { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2565         { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2566         { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2567         { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2568         { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2569         { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2570         { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2571         { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2572         { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2573         { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2574         { .compatible = "ti,sysc-usb-host-fs",
2575           .data = &sysc_omap4_usb_host_fs, },
2576         { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2577         {  },
2578 };
2579 MODULE_DEVICE_TABLE(of, sysc_match);
2580 
2581 static struct platform_driver sysc_driver = {
2582         .probe          = sysc_probe,
2583         .remove         = sysc_remove,
2584         .driver         = {
2585                 .name   = "ti-sysc",
2586                 .of_match_table = sysc_match,
2587                 .pm = &sysc_pm_ops,
2588         },
2589 };
2590 
2591 static int __init sysc_init(void)
2592 {
2593         bus_register_notifier(&platform_bus_type, &sysc_nb);
2594 
2595         return platform_driver_register(&sysc_driver);
2596 }
2597 module_init(sysc_init);
2598 
2599 static void __exit sysc_exit(void)
2600 {
2601         bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2602         platform_driver_unregister(&sysc_driver);
2603 }
2604 module_exit(sysc_exit);
2605 
2606 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2607 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/bus/ti-sysc.c

DEFINITIONS
