drivers/bus/mvebu-mbus.c

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This source file includes following definitions.
mv_mbus_dram_info
mv_mbus_dram_info_nooverlap
mvebu_mbus_window_is_remappable
mvebu_mbus_read_window
mvebu_mbus_disable_window
mvebu_mbus_window_is_free
mvebu_mbus_window_conflicts
mvebu_mbus_find_window
mvebu_mbus_setup_window
mvebu_mbus_alloc_window
mvebu_sdram_debug_show_orion
mvebu_sdram_debug_show_dove
mvebu_sdram_debug_show
mvebu_sdram_debug_open
mvebu_devs_debug_show
mvebu_devs_debug_open
generic_mbus_win_cfg_offset
armada_370_xp_mbus_win_cfg_offset
mv78xx0_mbus_win_cfg_offset
generic_mbus_win_remap_2_offset
generic_mbus_win_remap_4_offset
generic_mbus_win_remap_8_offset
armada_xp_mbus_win_remap_offset
mvebu_mbus_find_bridge_hole
mvebu_mbus_setup_cpu_target_nooverlap
mvebu_mbus_default_setup_cpu_target
mvebu_mbus_default_save_cpu_target
mvebu_mbus_dove_setup_cpu_target
mvebu_mbus_dove_save_cpu_target
mvebu_mbus_save_cpu_target
mvebu_mbus_add_window_remap_by_id
mvebu_mbus_add_window_by_id
mvebu_mbus_del_window
mvebu_mbus_get_pcie_mem_aperture
mvebu_mbus_get_pcie_io_aperture
mvebu_mbus_get_dram_win_info
mvebu_mbus_get_io_win_info
mvebu_mbus_debugfs_init
mvebu_mbus_suspend
mvebu_mbus_resume
mvebu_mbus_common_init
mvebu_mbus_init
mbus_dt_setup_win
mbus_parse_ranges
mbus_dt_setup
mvebu_mbus_get_pcie_resources
mvebu_mbus_dt_init
   1 /*
   2  * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
   3  * 370/XP, Dove, Orion5x and MV78xx0)
   4  *
   5  * This file is licensed under the terms of the GNU General Public
   6  * License version 2.  This program is licensed "as is" without any
   7  * warranty of any kind, whether express or implied.
   8  *
   9  * The Marvell EBU SoCs have a configurable physical address space:
  10  * the physical address at which certain devices (PCIe, NOR, NAND,
  11  * etc.) sit can be configured. The configuration takes place through
  12  * two sets of registers:
  13  *
  14  * - One to configure the access of the CPU to the devices. Depending
  15  *   on the families, there are between 8 and 20 configurable windows,
  16  *   each can be use to create a physical memory window that maps to a
  17  *   specific device. Devices are identified by a tuple (target,
  18  *   attribute).
  19  *
  20  * - One to configure the access to the CPU to the SDRAM. There are
  21  *   either 2 (for Dove) or 4 (for other families) windows to map the
  22  *   SDRAM into the physical address space.
  23  *
  24  * This driver:
  25  *
  26  * - Reads out the SDRAM address decoding windows at initialization
  27  *   time, and fills the mvebu_mbus_dram_info structure with these
  28  *   informations. The exported function mv_mbus_dram_info() allow
  29  *   device drivers to get those informations related to the SDRAM
  30  *   address decoding windows. This is because devices also have their
  31  *   own windows (configured through registers that are part of each
  32  *   device register space), and therefore the drivers for Marvell
  33  *   devices have to configure those device -> SDRAM windows to ensure
  34  *   that DMA works properly.
  35  *
  36  * - Provides an API for platform code or device drivers to
  37  *   dynamically add or remove address decoding windows for the CPU ->
  38  *   device accesses. This API is mvebu_mbus_add_window_by_id(),
  39  *   mvebu_mbus_add_window_remap_by_id() and
  40  *   mvebu_mbus_del_window().
  41  *
  42  * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
  43  *   see the list of CPU -> SDRAM windows and their configuration
  44  *   (file 'sdram') and the list of CPU -> devices windows and their
  45  *   configuration (file 'devices').
  46  */
  47 
  48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  49 
  50 #include <linux/kernel.h>
  51 #include <linux/module.h>
  52 #include <linux/init.h>
  53 #include <linux/mbus.h>
  54 #include <linux/io.h>
  55 #include <linux/ioport.h>
  56 #include <linux/of.h>
  57 #include <linux/of_address.h>
  58 #include <linux/debugfs.h>
  59 #include <linux/log2.h>
  60 #include <linux/memblock.h>
  61 #include <linux/syscore_ops.h>
  62 
  63 /*
  64  * DDR target is the same on all platforms.
  65  */
  66 #define TARGET_DDR              0
  67 
  68 /*
  69  * CPU Address Decode Windows registers
  70  */
  71 #define WIN_CTRL_OFF            0x0000
  72 #define   WIN_CTRL_ENABLE       BIT(0)
  73 /* Only on HW I/O coherency capable platforms */
  74 #define   WIN_CTRL_SYNCBARRIER  BIT(1)
  75 #define   WIN_CTRL_TGT_MASK     0xf0
  76 #define   WIN_CTRL_TGT_SHIFT    4
  77 #define   WIN_CTRL_ATTR_MASK    0xff00
  78 #define   WIN_CTRL_ATTR_SHIFT   8
  79 #define   WIN_CTRL_SIZE_MASK    0xffff0000
  80 #define   WIN_CTRL_SIZE_SHIFT   16
  81 #define WIN_BASE_OFF            0x0004
  82 #define   WIN_BASE_LOW          0xffff0000
  83 #define   WIN_BASE_HIGH         0xf
  84 #define WIN_REMAP_LO_OFF        0x0008
  85 #define   WIN_REMAP_LOW         0xffff0000
  86 #define WIN_REMAP_HI_OFF        0x000c
  87 
  88 #define UNIT_SYNC_BARRIER_OFF   0x84
  89 #define   UNIT_SYNC_BARRIER_ALL 0xFFFF
  90 
  91 #define ATTR_HW_COHERENCY       (0x1 << 4)
  92 
  93 #define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
  94 #define  DDR_BASE_CS_HIGH_MASK  0xf
  95 #define  DDR_BASE_CS_LOW_MASK   0xff000000
  96 #define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
  97 #define  DDR_SIZE_ENABLED       BIT(0)
  98 #define  DDR_SIZE_CS_MASK       0x1c
  99 #define  DDR_SIZE_CS_SHIFT      2
 100 #define  DDR_SIZE_MASK          0xff000000
 101 
 102 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
 103 
 104 /* Relative to mbusbridge_base */
 105 #define MBUS_BRIDGE_CTRL_OFF    0x0
 106 #define MBUS_BRIDGE_BASE_OFF    0x4
 107 
 108 /* Maximum number of windows, for all known platforms */
 109 #define MBUS_WINS_MAX           20
 110 
 111 struct mvebu_mbus_state;
 112 
 113 struct mvebu_mbus_soc_data {
 114         unsigned int num_wins;
 115         bool has_mbus_bridge;
 116         unsigned int (*win_cfg_offset)(const int win);
 117         unsigned int (*win_remap_offset)(const int win);
 118         void (*setup_cpu_target)(struct mvebu_mbus_state *s);
 119         int (*save_cpu_target)(struct mvebu_mbus_state *s,
 120                                u32 __iomem *store_addr);
 121         int (*show_cpu_target)(struct mvebu_mbus_state *s,
 122                                struct seq_file *seq, void *v);
 123 };
 124 
 125 /*
 126  * Used to store the state of one MBus window accross suspend/resume.
 127  */
 128 struct mvebu_mbus_win_data {
 129         u32 ctrl;
 130         u32 base;
 131         u32 remap_lo;
 132         u32 remap_hi;
 133 };
 134 
 135 struct mvebu_mbus_state {
 136         void __iomem *mbuswins_base;
 137         void __iomem *sdramwins_base;
 138         void __iomem *mbusbridge_base;
 139         phys_addr_t sdramwins_phys_base;
 140         struct dentry *debugfs_root;
 141         struct dentry *debugfs_sdram;
 142         struct dentry *debugfs_devs;
 143         struct resource pcie_mem_aperture;
 144         struct resource pcie_io_aperture;
 145         const struct mvebu_mbus_soc_data *soc;
 146         int hw_io_coherency;
 147 
 148         /* Used during suspend/resume */
 149         u32 mbus_bridge_ctrl;
 150         u32 mbus_bridge_base;
 151         struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
 152 };
 153 
 154 static struct mvebu_mbus_state mbus_state;
 155 
 156 /*
 157  * We provide two variants of the mv_mbus_dram_info() function:
 158  *
 159  * - The normal one, where the described DRAM ranges may overlap with
 160  *   the I/O windows, but for which the DRAM ranges are guaranteed to
 161  *   have a power of two size. Such ranges are suitable for the DMA
 162  *   masters that only DMA between the RAM and the device, which is
 163  *   actually all devices except the crypto engines.
 164  *
 165  * - The 'nooverlap' one, where the described DRAM ranges are
 166  *   guaranteed to not overlap with the I/O windows, but for which the
 167  *   DRAM ranges will not have power of two sizes. They will only be
 168  *   aligned on a 64 KB boundary, and have a size multiple of 64
 169  *   KB. Such ranges are suitable for the DMA masters that DMA between
 170  *   the crypto SRAM (which is mapped through an I/O window) and a
 171  *   device. This is the case for the crypto engines.
 172  */
 173 
 174 static struct mbus_dram_target_info mvebu_mbus_dram_info;
 175 static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
 176 
 177 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
 178 {
 179         return &mvebu_mbus_dram_info;
 180 }
 181 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 182 
 183 const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
 184 {
 185         return &mvebu_mbus_dram_info_nooverlap;
 186 }
 187 EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
 188 
 189 /* Checks whether the given window has remap capability */
 190 static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
 191                                             const int win)
 192 {
 193         return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
 194 }
 195 
 196 /*
 197  * Functions to manipulate the address decoding windows
 198  */
 199 
 200 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
 201                                    int win, int *enabled, u64 *base,
 202                                    u32 *size, u8 *target, u8 *attr,
 203                                    u64 *remap)
 204 {
 205         void __iomem *addr = mbus->mbuswins_base +
 206                 mbus->soc->win_cfg_offset(win);
 207         u32 basereg = readl(addr + WIN_BASE_OFF);
 208         u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
 209 
 210         if (!(ctrlreg & WIN_CTRL_ENABLE)) {
 211                 *enabled = 0;
 212                 return;
 213         }
 214 
 215         *enabled = 1;
 216         *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
 217         *base |= (basereg & WIN_BASE_LOW);
 218         *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
 219 
 220         if (target)
 221                 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
 222 
 223         if (attr)
 224                 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
 225 
 226         if (remap) {
 227                 if (mvebu_mbus_window_is_remappable(mbus, win)) {
 228                         u32 remap_low, remap_hi;
 229                         void __iomem *addr_rmp = mbus->mbuswins_base +
 230                                 mbus->soc->win_remap_offset(win);
 231                         remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
 232                         remap_hi  = readl(addr_rmp + WIN_REMAP_HI_OFF);
 233                         *remap = ((u64)remap_hi << 32) | remap_low;
 234                 } else
 235                         *remap = 0;
 236         }
 237 }
 238 
 239 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
 240                                       int win)
 241 {
 242         void __iomem *addr;
 243 
 244         addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
 245         writel(0, addr + WIN_BASE_OFF);
 246         writel(0, addr + WIN_CTRL_OFF);
 247 
 248         if (mvebu_mbus_window_is_remappable(mbus, win)) {
 249                 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
 250                 writel(0, addr + WIN_REMAP_LO_OFF);
 251                 writel(0, addr + WIN_REMAP_HI_OFF);
 252         }
 253 }
 254 
 255 /* Checks whether the given window number is available */
 256 
 257 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
 258                                      const int win)
 259 {
 260         void __iomem *addr = mbus->mbuswins_base +
 261                 mbus->soc->win_cfg_offset(win);
 262         u32 ctrl = readl(addr + WIN_CTRL_OFF);
 263 
 264         return !(ctrl & WIN_CTRL_ENABLE);
 265 }
 266 
 267 /*
 268  * Checks whether the given (base, base+size) area doesn't overlap an
 269  * existing region
 270  */
 271 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
 272                                        phys_addr_t base, size_t size,
 273                                        u8 target, u8 attr)
 274 {
 275         u64 end = (u64)base + size;
 276         int win;
 277 
 278         for (win = 0; win < mbus->soc->num_wins; win++) {
 279                 u64 wbase, wend;
 280                 u32 wsize;
 281                 u8 wtarget, wattr;
 282                 int enabled;
 283 
 284                 mvebu_mbus_read_window(mbus, win,
 285                                        &enabled, &wbase, &wsize,
 286                                        &wtarget, &wattr, NULL);
 287 
 288                 if (!enabled)
 289                         continue;
 290 
 291                 wend = wbase + wsize;
 292 
 293                 /*
 294                  * Check if the current window overlaps with the
 295                  * proposed physical range
 296                  */
 297                 if ((u64)base < wend && end > wbase)
 298                         return 0;
 299         }
 300 
 301         return 1;
 302 }
 303 
 304 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
 305                                   phys_addr_t base, size_t size)
 306 {
 307         int win;
 308 
 309         for (win = 0; win < mbus->soc->num_wins; win++) {
 310                 u64 wbase;
 311                 u32 wsize;
 312                 int enabled;
 313 
 314                 mvebu_mbus_read_window(mbus, win,
 315                                        &enabled, &wbase, &wsize,
 316                                        NULL, NULL, NULL);
 317 
 318                 if (!enabled)
 319                         continue;
 320 
 321                 if (base == wbase && size == wsize)
 322                         return win;
 323         }
 324 
 325         return -ENODEV;
 326 }
 327 
 328 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
 329                                    int win, phys_addr_t base, size_t size,
 330                                    phys_addr_t remap, u8 target,
 331                                    u8 attr)
 332 {
 333         void __iomem *addr = mbus->mbuswins_base +
 334                 mbus->soc->win_cfg_offset(win);
 335         u32 ctrl, remap_addr;
 336 
 337         if (!is_power_of_2(size)) {
 338                 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
 339                 return -EINVAL;
 340         }
 341 
 342         if ((base & (phys_addr_t)(size - 1)) != 0) {
 343                 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
 344                      size);
 345                 return -EINVAL;
 346         }
 347 
 348         ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
 349                 (attr << WIN_CTRL_ATTR_SHIFT)    |
 350                 (target << WIN_CTRL_TGT_SHIFT)   |
 351                 WIN_CTRL_ENABLE;
 352         if (mbus->hw_io_coherency)
 353                 ctrl |= WIN_CTRL_SYNCBARRIER;
 354 
 355         writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
 356         writel(ctrl, addr + WIN_CTRL_OFF);
 357 
 358         if (mvebu_mbus_window_is_remappable(mbus, win)) {
 359                 void __iomem *addr_rmp = mbus->mbuswins_base +
 360                         mbus->soc->win_remap_offset(win);
 361 
 362                 if (remap == MVEBU_MBUS_NO_REMAP)
 363                         remap_addr = base;
 364                 else
 365                         remap_addr = remap;
 366                 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
 367                 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
 368         }
 369 
 370         return 0;
 371 }
 372 
 373 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
 374                                    phys_addr_t base, size_t size,
 375                                    phys_addr_t remap, u8 target,
 376                                    u8 attr)
 377 {
 378         int win;
 379 
 380         if (remap == MVEBU_MBUS_NO_REMAP) {
 381                 for (win = 0; win < mbus->soc->num_wins; win++) {
 382                         if (mvebu_mbus_window_is_remappable(mbus, win))
 383                                 continue;
 384 
 385                         if (mvebu_mbus_window_is_free(mbus, win))
 386                                 return mvebu_mbus_setup_window(mbus, win, base,
 387                                                                size, remap,
 388                                                                target, attr);
 389                 }
 390         }
 391 
 392         for (win = 0; win < mbus->soc->num_wins; win++) {
 393                 /* Skip window if need remap but is not supported */
 394                 if ((remap != MVEBU_MBUS_NO_REMAP) &&
 395                     !mvebu_mbus_window_is_remappable(mbus, win))
 396                         continue;
 397 
 398                 if (mvebu_mbus_window_is_free(mbus, win))
 399                         return mvebu_mbus_setup_window(mbus, win, base, size,
 400                                                        remap, target, attr);
 401         }
 402 
 403         return -ENOMEM;
 404 }
 405 
 406 /*
 407  * Debugfs debugging
 408  */
 409 
 410 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
 411 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
 412                                         struct seq_file *seq, void *v)
 413 {
 414         int i;
 415 
 416         for (i = 0; i < 4; i++) {
 417                 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
 418                 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
 419                 u64 base;
 420                 u32 size;
 421 
 422                 if (!(sizereg & DDR_SIZE_ENABLED)) {
 423                         seq_printf(seq, "[%d] disabled\n", i);
 424                         continue;
 425                 }
 426 
 427                 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
 428                 base |= basereg & DDR_BASE_CS_LOW_MASK;
 429                 size = (sizereg | ~DDR_SIZE_MASK);
 430 
 431                 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
 432                            i, (unsigned long long)base,
 433                            (unsigned long long)base + size + 1,
 434                            (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
 435         }
 436 
 437         return 0;
 438 }
 439 
 440 /* Special function for Dove */
 441 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
 442                                        struct seq_file *seq, void *v)
 443 {
 444         int i;
 445 
 446         for (i = 0; i < 2; i++) {
 447                 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
 448                 u64 base;
 449                 u32 size;
 450 
 451                 if (!(map & 1)) {
 452                         seq_printf(seq, "[%d] disabled\n", i);
 453                         continue;
 454                 }
 455 
 456                 base = map & 0xff800000;
 457                 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
 458 
 459                 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
 460                            i, (unsigned long long)base,
 461                            (unsigned long long)base + size, i);
 462         }
 463 
 464         return 0;
 465 }
 466 
 467 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
 468 {
 469         struct mvebu_mbus_state *mbus = &mbus_state;
 470         return mbus->soc->show_cpu_target(mbus, seq, v);
 471 }
 472 
 473 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
 474 {
 475         return single_open(file, mvebu_sdram_debug_show, inode->i_private);
 476 }
 477 
 478 static const struct file_operations mvebu_sdram_debug_fops = {
 479         .open = mvebu_sdram_debug_open,
 480         .read = seq_read,
 481         .llseek = seq_lseek,
 482         .release = single_release,
 483 };
 484 
 485 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
 486 {
 487         struct mvebu_mbus_state *mbus = &mbus_state;
 488         int win;
 489 
 490         for (win = 0; win < mbus->soc->num_wins; win++) {
 491                 u64 wbase, wremap;
 492                 u32 wsize;
 493                 u8 wtarget, wattr;
 494                 int enabled;
 495 
 496                 mvebu_mbus_read_window(mbus, win,
 497                                        &enabled, &wbase, &wsize,
 498                                        &wtarget, &wattr, &wremap);
 499 
 500                 if (!enabled) {
 501                         seq_printf(seq, "[%02d] disabled\n", win);
 502                         continue;
 503                 }
 504 
 505                 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
 506                            win, (unsigned long long)wbase,
 507                            (unsigned long long)(wbase + wsize), wtarget, wattr);
 508 
 509                 if (!is_power_of_2(wsize) ||
 510                     ((wbase & (u64)(wsize - 1)) != 0))
 511                         seq_puts(seq, " (Invalid base/size!!)");
 512 
 513                 if (mvebu_mbus_window_is_remappable(mbus, win)) {
 514                         seq_printf(seq, " (remap %016llx)\n",
 515                                    (unsigned long long)wremap);
 516                 } else
 517                         seq_printf(seq, "\n");
 518         }
 519 
 520         return 0;
 521 }
 522 
 523 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
 524 {
 525         return single_open(file, mvebu_devs_debug_show, inode->i_private);
 526 }
 527 
 528 static const struct file_operations mvebu_devs_debug_fops = {
 529         .open = mvebu_devs_debug_open,
 530         .read = seq_read,
 531         .llseek = seq_lseek,
 532         .release = single_release,
 533 };
 534 
 535 /*
 536  * SoC-specific functions and definitions
 537  */
 538 
 539 static unsigned int generic_mbus_win_cfg_offset(int win)
 540 {
 541         return win << 4;
 542 }
 543 
 544 static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
 545 {
 546         /* The register layout is a bit annoying and the below code
 547          * tries to cope with it.
 548          * - At offset 0x0, there are the registers for the first 8
 549          *   windows, with 4 registers of 32 bits per window (ctrl,
 550          *   base, remap low, remap high)
 551          * - Then at offset 0x80, there is a hole of 0x10 bytes for
 552          *   the internal registers base address and internal units
 553          *   sync barrier register.
 554          * - Then at offset 0x90, there the registers for 12
 555          *   windows, with only 2 registers of 32 bits per window
 556          *   (ctrl, base).
 557          */
 558         if (win < 8)
 559                 return win << 4;
 560         else
 561                 return 0x90 + ((win - 8) << 3);
 562 }
 563 
 564 static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
 565 {
 566         if (win < 8)
 567                 return win << 4;
 568         else
 569                 return 0x900 + ((win - 8) << 4);
 570 }
 571 
 572 static unsigned int generic_mbus_win_remap_2_offset(int win)
 573 {
 574         if (win < 2)
 575                 return generic_mbus_win_cfg_offset(win);
 576         else
 577                 return MVEBU_MBUS_NO_REMAP;
 578 }
 579 
 580 static unsigned int generic_mbus_win_remap_4_offset(int win)
 581 {
 582         if (win < 4)
 583                 return generic_mbus_win_cfg_offset(win);
 584         else
 585                 return MVEBU_MBUS_NO_REMAP;
 586 }
 587 
 588 static unsigned int generic_mbus_win_remap_8_offset(int win)
 589 {
 590         if (win < 8)
 591                 return generic_mbus_win_cfg_offset(win);
 592         else
 593                 return MVEBU_MBUS_NO_REMAP;
 594 }
 595 
 596 static unsigned int armada_xp_mbus_win_remap_offset(int win)
 597 {
 598         if (win < 8)
 599                 return generic_mbus_win_cfg_offset(win);
 600         else if (win == 13)
 601                 return 0xF0 - WIN_REMAP_LO_OFF;
 602         else
 603                 return MVEBU_MBUS_NO_REMAP;
 604 }
 605 
 606 /*
 607  * Use the memblock information to find the MBus bridge hole in the
 608  * physical address space.
 609  */
 610 static void __init
 611 mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
 612 {
 613         struct memblock_region *r;
 614         uint64_t s = 0;
 615 
 616         for_each_memblock(memory, r) {
 617                 /*
 618                  * This part of the memory is above 4 GB, so we don't
 619                  * care for the MBus bridge hole.
 620                  */
 621                 if (r->base >= 0x100000000ULL)
 622                         continue;
 623 
 624                 /*
 625                  * The MBus bridge hole is at the end of the RAM under
 626                  * the 4 GB limit.
 627                  */
 628                 if (r->base + r->size > s)
 629                         s = r->base + r->size;
 630         }
 631 
 632         *start = s;
 633         *end = 0x100000000ULL;
 634 }
 635 
 636 /*
 637  * This function fills in the mvebu_mbus_dram_info_nooverlap data
 638  * structure, by looking at the mvebu_mbus_dram_info data, and
 639  * removing the parts of it that overlap with I/O windows.
 640  */
 641 static void __init
 642 mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
 643 {
 644         uint64_t mbus_bridge_base, mbus_bridge_end;
 645         int cs_nooverlap = 0;
 646         int i;
 647 
 648         mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
 649 
 650         for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
 651                 struct mbus_dram_window *w;
 652                 u64 base, size, end;
 653 
 654                 w = &mvebu_mbus_dram_info.cs[i];
 655                 base = w->base;
 656                 size = w->size;
 657                 end = base + size;
 658 
 659                 /*
 660                  * The CS is fully enclosed inside the MBus bridge
 661                  * area, so ignore it.
 662                  */
 663                 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
 664                         continue;
 665 
 666                 /*
 667                  * Beginning of CS overlaps with end of MBus, raise CS
 668                  * base address, and shrink its size.
 669                  */
 670                 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
 671                         size -= mbus_bridge_end - base;
 672                         base = mbus_bridge_end;
 673                 }
 674 
 675                 /*
 676                  * End of CS overlaps with beginning of MBus, shrink
 677                  * CS size.
 678                  */
 679                 if (base < mbus_bridge_base && end > mbus_bridge_base)
 680                         size -= end - mbus_bridge_base;
 681 
 682                 w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
 683                 w->cs_index = i;
 684                 w->mbus_attr = 0xf & ~(1 << i);
 685                 if (mbus->hw_io_coherency)
 686                         w->mbus_attr |= ATTR_HW_COHERENCY;
 687                 w->base = base;
 688                 w->size = size;
 689         }
 690 
 691         mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
 692         mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
 693 }
 694 
 695 static void __init
 696 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
 697 {
 698         int i;
 699         int cs;
 700 
 701         mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 702 
 703         for (i = 0, cs = 0; i < 4; i++) {
 704                 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
 705                 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
 706 
 707                 /*
 708                  * We only take care of entries for which the chip
 709                  * select is enabled, and that don't have high base
 710                  * address bits set (devices can only access the first
 711                  * 32 bits of the memory).
 712                  */
 713                 if ((size & DDR_SIZE_ENABLED) &&
 714                     !(base & DDR_BASE_CS_HIGH_MASK)) {
 715                         struct mbus_dram_window *w;
 716 
 717                         w = &mvebu_mbus_dram_info.cs[cs++];
 718                         w->cs_index = i;
 719                         w->mbus_attr = 0xf & ~(1 << i);
 720                         if (mbus->hw_io_coherency)
 721                                 w->mbus_attr |= ATTR_HW_COHERENCY;
 722                         w->base = base & DDR_BASE_CS_LOW_MASK;
 723                         w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
 724                 }
 725         }
 726         mvebu_mbus_dram_info.num_cs = cs;
 727 }
 728 
 729 static int
 730 mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
 731                                    u32 __iomem *store_addr)
 732 {
 733         int i;
 734 
 735         for (i = 0; i < 4; i++) {
 736                 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
 737                 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
 738 
 739                 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
 740                        store_addr++);
 741                 writel(base, store_addr++);
 742                 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
 743                        store_addr++);
 744                 writel(size, store_addr++);
 745         }
 746 
 747         /* We've written 16 words to the store address */
 748         return 16;
 749 }
 750 
 751 static void __init
 752 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
 753 {
 754         int i;
 755         int cs;
 756 
 757         mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 758 
 759         for (i = 0, cs = 0; i < 2; i++) {
 760                 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
 761 
 762                 /*
 763                  * Chip select enabled?
 764                  */
 765                 if (map & 1) {
 766                         struct mbus_dram_window *w;
 767 
 768                         w = &mvebu_mbus_dram_info.cs[cs++];
 769                         w->cs_index = i;
 770                         w->mbus_attr = 0; /* CS address decoding done inside */
 771                                           /* the DDR controller, no need to  */
 772                                           /* provide attributes */
 773                         w->base = map & 0xff800000;
 774                         w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
 775                 }
 776         }
 777 
 778         mvebu_mbus_dram_info.num_cs = cs;
 779 }
 780 
 781 static int
 782 mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
 783                                 u32 __iomem *store_addr)
 784 {
 785         int i;
 786 
 787         for (i = 0; i < 2; i++) {
 788                 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
 789 
 790                 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
 791                        store_addr++);
 792                 writel(map, store_addr++);
 793         }
 794 
 795         /* We've written 4 words to the store address */
 796         return 4;
 797 }
 798 
 799 int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
 800 {
 801         return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
 802 }
 803 
 804 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
 805         .num_wins            = 20,
 806         .has_mbus_bridge     = true,
 807         .win_cfg_offset      = armada_370_xp_mbus_win_cfg_offset,
 808         .win_remap_offset    = generic_mbus_win_remap_8_offset,
 809         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 810         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 811         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
 812 };
 813 
 814 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
 815         .num_wins            = 20,
 816         .has_mbus_bridge     = true,
 817         .win_cfg_offset      = armada_370_xp_mbus_win_cfg_offset,
 818         .win_remap_offset    = armada_xp_mbus_win_remap_offset,
 819         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 820         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 821         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
 822 };
 823 
 824 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
 825         .num_wins            = 8,
 826         .win_cfg_offset      = generic_mbus_win_cfg_offset,
 827         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
 828         .win_remap_offset    = generic_mbus_win_remap_4_offset,
 829         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 830         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 831 };
 832 
 833 static const struct mvebu_mbus_soc_data dove_mbus_data = {
 834         .num_wins            = 8,
 835         .win_cfg_offset      = generic_mbus_win_cfg_offset,
 836         .save_cpu_target     = mvebu_mbus_dove_save_cpu_target,
 837         .win_remap_offset    = generic_mbus_win_remap_4_offset,
 838         .setup_cpu_target    = mvebu_mbus_dove_setup_cpu_target,
 839         .show_cpu_target     = mvebu_sdram_debug_show_dove,
 840 };
 841 
 842 /*
 843  * Some variants of Orion5x have 4 remappable windows, some other have
 844  * only two of them.
 845  */
 846 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
 847         .num_wins            = 8,
 848         .win_cfg_offset      = generic_mbus_win_cfg_offset,
 849         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
 850         .win_remap_offset    = generic_mbus_win_remap_4_offset,
 851         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 852         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 853 };
 854 
 855 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
 856         .num_wins            = 8,
 857         .win_cfg_offset      = generic_mbus_win_cfg_offset,
 858         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
 859         .win_remap_offset    = generic_mbus_win_remap_2_offset,
 860         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 861         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 862 };
 863 
 864 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
 865         .num_wins            = 14,
 866         .win_cfg_offset      = mv78xx0_mbus_win_cfg_offset,
 867         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
 868         .win_remap_offset    = generic_mbus_win_remap_8_offset,
 869         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
 870         .show_cpu_target     = mvebu_sdram_debug_show_orion,
 871 };
 872 
 873 static const struct of_device_id of_mvebu_mbus_ids[] = {
 874         { .compatible = "marvell,armada370-mbus",
 875           .data = &armada_370_mbus_data, },
 876         { .compatible = "marvell,armada375-mbus",
 877           .data = &armada_xp_mbus_data, },
 878         { .compatible = "marvell,armada380-mbus",
 879           .data = &armada_xp_mbus_data, },
 880         { .compatible = "marvell,armadaxp-mbus",
 881           .data = &armada_xp_mbus_data, },
 882         { .compatible = "marvell,kirkwood-mbus",
 883           .data = &kirkwood_mbus_data, },
 884         { .compatible = "marvell,dove-mbus",
 885           .data = &dove_mbus_data, },
 886         { .compatible = "marvell,orion5x-88f5281-mbus",
 887           .data = &orion5x_4win_mbus_data, },
 888         { .compatible = "marvell,orion5x-88f5182-mbus",
 889           .data = &orion5x_2win_mbus_data, },
 890         { .compatible = "marvell,orion5x-88f5181-mbus",
 891           .data = &orion5x_2win_mbus_data, },
 892         { .compatible = "marvell,orion5x-88f6183-mbus",
 893           .data = &orion5x_4win_mbus_data, },
 894         { .compatible = "marvell,mv78xx0-mbus",
 895           .data = &mv78xx0_mbus_data, },
 896         { },
 897 };
 898 
 899 /*
 900  * Public API of the driver
 901  */
 902 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
 903                                       unsigned int attribute,
 904                                       phys_addr_t base, size_t size,
 905                                       phys_addr_t remap)
 906 {
 907         struct mvebu_mbus_state *s = &mbus_state;
 908 
 909         if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
 910                 pr_err("cannot add window '%x:%x', conflicts with another window\n",
 911                        target, attribute);
 912                 return -EINVAL;
 913         }
 914 
 915         return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
 916 }
 917 
 918 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
 919                                 phys_addr_t base, size_t size)
 920 {
 921         return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
 922                                                  size, MVEBU_MBUS_NO_REMAP);
 923 }
 924 
 925 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
 926 {
 927         int win;
 928 
 929         win = mvebu_mbus_find_window(&mbus_state, base, size);
 930         if (win < 0)
 931                 return win;
 932 
 933         mvebu_mbus_disable_window(&mbus_state, win);
 934         return 0;
 935 }
 936 
 937 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
 938 {
 939         if (!res)
 940                 return;
 941         *res = mbus_state.pcie_mem_aperture;
 942 }
 943 
 944 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
 945 {
 946         if (!res)
 947                 return;
 948         *res = mbus_state.pcie_io_aperture;
 949 }
 950 
 951 int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
 952 {
 953         const struct mbus_dram_target_info *dram;
 954         int i;
 955 
 956         /* Get dram info */
 957         dram = mv_mbus_dram_info();
 958         if (!dram) {
 959                 pr_err("missing DRAM information\n");
 960                 return -ENODEV;
 961         }
 962 
 963         /* Try to find matching DRAM window for phyaddr */
 964         for (i = 0; i < dram->num_cs; i++) {
 965                 const struct mbus_dram_window *cs = dram->cs + i;
 966 
 967                 if (cs->base <= phyaddr &&
 968                         phyaddr <= (cs->base + cs->size - 1)) {
 969                         *target = dram->mbus_dram_target_id;
 970                         *attr = cs->mbus_attr;
 971                         return 0;
 972                 }
 973         }
 974 
 975         pr_err("invalid dram address %pa\n", &phyaddr);
 976         return -EINVAL;
 977 }
 978 EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
 979 
 980 int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
 981                                u8 *attr)
 982 {
 983         int win;
 984 
 985         for (win = 0; win < mbus_state.soc->num_wins; win++) {
 986                 u64 wbase;
 987                 int enabled;
 988 
 989                 mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
 990                                        size, target, attr, NULL);
 991 
 992                 if (!enabled)
 993                         continue;
 994 
 995                 if (wbase <= phyaddr && phyaddr <= wbase + *size)
 996                         return win;
 997         }
 998 
 999         return -EINVAL;
1000 }
1001 EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
1002 
1003 static __init int mvebu_mbus_debugfs_init(void)
1004 {
1005         struct mvebu_mbus_state *s = &mbus_state;
1006 
1007         /*
1008          * If no base has been initialized, doesn't make sense to
1009          * register the debugfs entries. We may be on a multiplatform
1010          * kernel that isn't running a Marvell EBU SoC.
1011          */
1012         if (!s->mbuswins_base)
1013                 return 0;
1014 
1015         s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
1016         if (s->debugfs_root) {
1017                 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
1018                                                        s->debugfs_root, NULL,
1019                                                        &mvebu_sdram_debug_fops);
1020                 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
1021                                                       s->debugfs_root, NULL,
1022                                                       &mvebu_devs_debug_fops);
1023         }
1024 
1025         return 0;
1026 }
1027 fs_initcall(mvebu_mbus_debugfs_init);
1028 
1029 static int mvebu_mbus_suspend(void)
1030 {
1031         struct mvebu_mbus_state *s = &mbus_state;
1032         int win;
1033 
1034         if (!s->mbusbridge_base)
1035                 return -ENODEV;
1036 
1037         for (win = 0; win < s->soc->num_wins; win++) {
1038                 void __iomem *addr = s->mbuswins_base +
1039                         s->soc->win_cfg_offset(win);
1040                 void __iomem *addr_rmp;
1041 
1042                 s->wins[win].base = readl(addr + WIN_BASE_OFF);
1043                 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
1044 
1045                 if (!mvebu_mbus_window_is_remappable(s, win))
1046                         continue;
1047 
1048                 addr_rmp = s->mbuswins_base +
1049                         s->soc->win_remap_offset(win);
1050 
1051                 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
1052                 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
1053         }
1054 
1055         s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
1056                                     MBUS_BRIDGE_CTRL_OFF);
1057         s->mbus_bridge_base = readl(s->mbusbridge_base +
1058                                     MBUS_BRIDGE_BASE_OFF);
1059 
1060         return 0;
1061 }
1062 
1063 static void mvebu_mbus_resume(void)
1064 {
1065         struct mvebu_mbus_state *s = &mbus_state;
1066         int win;
1067 
1068         writel(s->mbus_bridge_ctrl,
1069                s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
1070         writel(s->mbus_bridge_base,
1071                s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
1072 
1073         for (win = 0; win < s->soc->num_wins; win++) {
1074                 void __iomem *addr = s->mbuswins_base +
1075                         s->soc->win_cfg_offset(win);
1076                 void __iomem *addr_rmp;
1077 
1078                 writel(s->wins[win].base, addr + WIN_BASE_OFF);
1079                 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
1080 
1081                 if (!mvebu_mbus_window_is_remappable(s, win))
1082                         continue;
1083 
1084                 addr_rmp = s->mbuswins_base +
1085                         s->soc->win_remap_offset(win);
1086 
1087                 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
1088                 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
1089         }
1090 }
1091 
1092 static struct syscore_ops mvebu_mbus_syscore_ops = {
1093         .suspend        = mvebu_mbus_suspend,
1094         .resume         = mvebu_mbus_resume,
1095 };
1096 
1097 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
1098                                          phys_addr_t mbuswins_phys_base,
1099                                          size_t mbuswins_size,
1100                                          phys_addr_t sdramwins_phys_base,
1101                                          size_t sdramwins_size,
1102                                          phys_addr_t mbusbridge_phys_base,
1103                                          size_t mbusbridge_size,
1104                                          bool is_coherent)
1105 {
1106         int win;
1107 
1108         mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
1109         if (!mbus->mbuswins_base)
1110                 return -ENOMEM;
1111 
1112         mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
1113         if (!mbus->sdramwins_base) {
1114                 iounmap(mbus_state.mbuswins_base);
1115                 return -ENOMEM;
1116         }
1117 
1118         mbus->sdramwins_phys_base = sdramwins_phys_base;
1119 
1120         if (mbusbridge_phys_base) {
1121                 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
1122                                                 mbusbridge_size);
1123                 if (!mbus->mbusbridge_base) {
1124                         iounmap(mbus->sdramwins_base);
1125                         iounmap(mbus->mbuswins_base);
1126                         return -ENOMEM;
1127                 }
1128         } else
1129                 mbus->mbusbridge_base = NULL;
1130 
1131         for (win = 0; win < mbus->soc->num_wins; win++)
1132                 mvebu_mbus_disable_window(mbus, win);
1133 
1134         mbus->soc->setup_cpu_target(mbus);
1135         mvebu_mbus_setup_cpu_target_nooverlap(mbus);
1136 
1137         if (is_coherent)
1138                 writel(UNIT_SYNC_BARRIER_ALL,
1139                        mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
1140 
1141         register_syscore_ops(&mvebu_mbus_syscore_ops);
1142 
1143         return 0;
1144 }
1145 
1146 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
1147                            size_t mbuswins_size,
1148                            phys_addr_t sdramwins_phys_base,
1149                            size_t sdramwins_size)
1150 {
1151         const struct of_device_id *of_id;
1152 
1153         for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
1154                 if (!strcmp(of_id->compatible, soc))
1155                         break;
1156 
1157         if (!of_id->compatible[0]) {
1158                 pr_err("could not find a matching SoC family\n");
1159                 return -ENODEV;
1160         }
1161 
1162         mbus_state.soc = of_id->data;
1163 
1164         return mvebu_mbus_common_init(&mbus_state,
1165                         mbuswins_phys_base,
1166                         mbuswins_size,
1167                         sdramwins_phys_base,
1168                         sdramwins_size, 0, 0, false);
1169 }
1170 
1171 #ifdef CONFIG_OF
1172 /*
1173  * The window IDs in the ranges DT property have the following format:
1174  *  - bits 28 to 31: MBus custom field
1175  *  - bits 24 to 27: window target ID
1176  *  - bits 16 to 23: window attribute ID
1177  *  - bits  0 to 15: unused
1178  */
1179 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1180 #define TARGET(id) (((id) & 0x0F000000) >> 24)
1181 #define ATTR(id)   (((id) & 0x00FF0000) >> 16)
1182 
1183 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1184                                     u32 base, u32 size,
1185                                     u8 target, u8 attr)
1186 {
1187         if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1188                 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1189                        target, attr);
1190                 return -EBUSY;
1191         }
1192 
1193         if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1194                                     target, attr)) {
1195                 pr_err("cannot add window '%04x:%04x', too many windows\n",
1196                        target, attr);
1197                 return -ENOMEM;
1198         }
1199         return 0;
1200 }
1201 
1202 static int __init
1203 mbus_parse_ranges(struct device_node *node,
1204                   int *addr_cells, int *c_addr_cells, int *c_size_cells,
1205                   int *cell_count, const __be32 **ranges_start,
1206                   const __be32 **ranges_end)
1207 {
1208         const __be32 *prop;
1209         int ranges_len, tuple_len;
1210 
1211         /* Allow a node with no 'ranges' property */
1212         *ranges_start = of_get_property(node, "ranges", &ranges_len);
1213         if (*ranges_start == NULL) {
1214                 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
1215                 *ranges_start = *ranges_end = NULL;
1216                 return 0;
1217         }
1218         *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
1219 
1220         *addr_cells = of_n_addr_cells(node);
1221 
1222         prop = of_get_property(node, "#address-cells", NULL);
1223         *c_addr_cells = be32_to_cpup(prop);
1224 
1225         prop = of_get_property(node, "#size-cells", NULL);
1226         *c_size_cells = be32_to_cpup(prop);
1227 
1228         *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
1229         tuple_len = (*cell_count) * sizeof(__be32);
1230 
1231         if (ranges_len % tuple_len) {
1232                 pr_warn("malformed ranges entry '%pOFn'\n", node);
1233                 return -EINVAL;
1234         }
1235         return 0;
1236 }
1237 
1238 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1239                                 struct device_node *np)
1240 {
1241         int addr_cells, c_addr_cells, c_size_cells;
1242         int i, ret, cell_count;
1243         const __be32 *r, *ranges_start, *ranges_end;
1244 
1245         ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1246                                 &c_size_cells, &cell_count,
1247                                 &ranges_start, &ranges_end);
1248         if (ret < 0)
1249                 return ret;
1250 
1251         for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1252                 u32 windowid, base, size;
1253                 u8 target, attr;
1254 
1255                 /*
1256                  * An entry with a non-zero custom field do not
1257                  * correspond to a static window, so skip it.
1258                  */
1259                 windowid = of_read_number(r, 1);
1260                 if (CUSTOM(windowid))
1261                         continue;
1262 
1263                 target = TARGET(windowid);
1264                 attr = ATTR(windowid);
1265 
1266                 base = of_read_number(r + c_addr_cells, addr_cells);
1267                 size = of_read_number(r + c_addr_cells + addr_cells,
1268                                       c_size_cells);
1269                 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1270                 if (ret < 0)
1271                         return ret;
1272         }
1273         return 0;
1274 }
1275 
1276 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1277                                                  struct resource *mem,
1278                                                  struct resource *io)
1279 {
1280         u32 reg[2];
1281         int ret;
1282 
1283         /*
1284          * These are optional, so we make sure that resource_size(x) will
1285          * return 0.
1286          */
1287         memset(mem, 0, sizeof(struct resource));
1288         mem->end = -1;
1289         memset(io, 0, sizeof(struct resource));
1290         io->end = -1;
1291 
1292         ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1293         if (!ret) {
1294                 mem->start = reg[0];
1295                 mem->end = mem->start + reg[1] - 1;
1296                 mem->flags = IORESOURCE_MEM;
1297         }
1298 
1299         ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1300         if (!ret) {
1301                 io->start = reg[0];
1302                 io->end = io->start + reg[1] - 1;
1303                 io->flags = IORESOURCE_IO;
1304         }
1305 }
1306 
1307 int __init mvebu_mbus_dt_init(bool is_coherent)
1308 {
1309         struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1310         struct device_node *np, *controller;
1311         const struct of_device_id *of_id;
1312         const __be32 *prop;
1313         int ret;
1314 
1315         np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1316         if (!np) {
1317                 pr_err("could not find a matching SoC family\n");
1318                 return -ENODEV;
1319         }
1320 
1321         mbus_state.soc = of_id->data;
1322 
1323         prop = of_get_property(np, "controller", NULL);
1324         if (!prop) {
1325                 pr_err("required 'controller' property missing\n");
1326                 return -EINVAL;
1327         }
1328 
1329         controller = of_find_node_by_phandle(be32_to_cpup(prop));
1330         if (!controller) {
1331                 pr_err("could not find an 'mbus-controller' node\n");
1332                 return -ENODEV;
1333         }
1334 
1335         if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1336                 pr_err("cannot get MBUS register address\n");
1337                 return -EINVAL;
1338         }
1339 
1340         if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1341                 pr_err("cannot get SDRAM register address\n");
1342                 return -EINVAL;
1343         }
1344 
1345         /*
1346          * Set the resource to 0 so that it can be left unmapped by
1347          * mvebu_mbus_common_init() if the DT doesn't carry the
1348          * necessary information. This is needed to preserve backward
1349          * compatibility.
1350          */
1351         memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1352 
1353         if (mbus_state.soc->has_mbus_bridge) {
1354                 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1355                         pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1356         }
1357 
1358         mbus_state.hw_io_coherency = is_coherent;
1359 
1360         /* Get optional pcie-{mem,io}-aperture properties */
1361         mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1362                                           &mbus_state.pcie_io_aperture);
1363 
1364         ret = mvebu_mbus_common_init(&mbus_state,
1365                                      mbuswins_res.start,
1366                                      resource_size(&mbuswins_res),
1367                                      sdramwins_res.start,
1368                                      resource_size(&sdramwins_res),
1369                                      mbusbridge_res.start,
1370                                      resource_size(&mbusbridge_res),
1371                                      is_coherent);
1372         if (ret)
1373                 return ret;
1374 
1375         /* Setup statically declared windows in the DT */
1376         return mbus_dt_setup(&mbus_state, np);
1377 }
1378 #endif
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root/drivers/bus/mvebu-mbus.c

DEFINITIONS
