1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2000-2008 LSI Corporation.
4 *
5 *
6 * Name: mpi_ioc.h
7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
8 * Creation Date: August 11, 2000
9 *
10 * mpi_ioc.h Version: 01.05.16
11 *
12 * Version History
13 * ---------------
14 *
15 * Date Version Description
16 * -------- -------- ------------------------------------------------------
17 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
18 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure.
19 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY.
20 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure.
21 * Added _MSG_EVENT_ACK_REPLY structure.
22 * Added _MSG_FW_DOWNLOAD_REPLY structure.
23 * Added _MSG_TOOLBOX_REPLY structure.
24 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure.
25 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI,
26 * _LINK_STATUS, _LOOP_STATE and _LOGOUT.
27 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in
28 * _MSG_EVENT_ACK_REPLY structure to match specification.
29 * 11-02-00 01.01.01 Original release for post 1.0 work.
30 * Added a value for Manufacturer to WhoInit.
31 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and
32 * removed toolbox message.
33 * 01-09-01 01.01.03 Added event enabled and disabled defines.
34 * Added structures for FwHeader and DataHeader.
35 * Added ImageType to FwUpload reply.
36 * 02-20-01 01.01.04 Started using MPI_POINTER.
37 * 02-27-01 01.01.05 Added event for RAID status change and its event data.
38 * Added IocNumber field to MSG_IOC_FACTS_REPLY.
39 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER.
40 * Added structure offset comments.
41 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE.
42 * 08-08-01 01.02.01 Original release for v1.2 work.
43 * New format for FWVersion and ProductId in
44 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER.
45 * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and
46 * related structure and defines.
47 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED.
48 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE.
49 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with
50 * IOCExceptions and changed DataImageSize to reserved.
51 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and
52 * MPI_FW_UPLOAD_ITYPE_NVDATA.
53 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID.
54 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field.
55 * 03-14-02 01.02.05 Added HeaderVersion field to MSG_IOC_FACTS_REPLY.
56 * 05-31-02 01.02.06 Added define for
57 * MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID.
58 * Added AliasIndex to EVENT_DATA_LOGOUT structure.
59 * 04-01-03 01.02.07 Added defines for MPI_FW_HEADER_SIGNATURE_.
60 * 06-26-03 01.02.08 Added new values to the product family defines.
61 * 04-29-04 01.02.09 Added IOCCapabilities field to MSG_IOC_FACTS_REPLY and
62 * added related defines.
63 * 05-11-04 01.03.01 Original release for MPI v1.3.
64 * 08-19-04 01.05.01 Added four new fields to MSG_IOC_INIT.
65 * Added three new fields to MSG_IOC_FACTS_REPLY.
66 * Defined four new bits for the IOCCapabilities field of
67 * the IOCFacts reply.
68 * Added two new PortTypes for the PortFacts reply.
69 * Added six new events along with their EventData
70 * structures.
71 * Added a new MsgFlag to the FwDownload request to
72 * indicate last segment.
73 * Defined a new image type of boot loader.
74 * Added FW family codes for SAS product families.
75 * 10-05-04 01.05.02 Added ReplyFifoHostSignalingAddr field to
76 * MSG_IOC_FACTS_REPLY.
77 * 12-07-04 01.05.03 Added more defines for SAS Discovery Error event.
78 * 12-09-04 01.05.04 Added Unsupported device to SAS Device event.
79 * 01-15-05 01.05.05 Added event data for SAS SES Event.
80 * 02-09-05 01.05.06 Added MPI_FW_UPLOAD_ITYPE_FW_BACKUP define.
81 * 02-22-05 01.05.07 Added Host Page Buffer Persistent flag to IOC Facts
82 * Reply and IOC Init Request.
83 * 03-11-05 01.05.08 Added family code for 1068E family.
84 * Removed IOCFacts Reply EEDP Capability bit.
85 * 06-24-05 01.05.09 Added 5 new IOCFacts Reply IOCCapabilities bits.
86 * Added Max SATA Targets to SAS Discovery Error event.
87 * 08-30-05 01.05.10 Added 4 new events and their event data structures.
88 * Added new ReasonCode value for SAS Device Status Change
89 * event.
90 * Added new family code for FC949E.
91 * 03-27-06 01.05.11 Added MPI_IOCFACTS_CAPABILITY_TLR.
92 * Added additional Reason Codes and more event data fields
93 * to EVENT_DATA_SAS_DEVICE_STATUS_CHANGE.
94 * Added EVENT_DATA_SAS_BROADCAST_PRIMITIVE structure and
95 * new event.
96 * Added MPI_EVENT_SAS_SMP_ERROR and event data structure.
97 * Added MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE and event
98 * data structure.
99 * Added MPI_EVENT_SAS_INIT_TABLE_OVERFLOW and event
100 * data structure.
101 * Added MPI_EXT_IMAGE_TYPE_INITIALIZATION.
102 * 10-11-06 01.05.12 Added MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED.
103 * Added MaxInitiators field to PortFacts reply.
104 * Added SAS Device Status Change ReasonCode for
105 * asynchronous notificaiton.
106 * Added MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE and event
107 * data structure.
108 * Added new ImageType values for FWDownload and FWUpload
109 * requests.
110 * 02-28-07 01.05.13 Added MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT for SAS
111 * Broadcast Event Data (replacing _RESERVED2).
112 * For Discovery Error Event Data DiscoveryStatus field,
113 * replaced _MULTPL_PATHS with _UNSUPPORTED_DEVICE and
114 * added _MULTI_PORT_DOMAIN.
115 * 05-24-07 01.05.14 Added Common Boot Block type to FWDownload Request.
116 * Added Common Boot Block type to FWUpload Request.
117 * 08-07-07 01.05.15 Added MPI_EVENT_SAS_INIT_RC_REMOVED define.
118 * Added MPI_EVENT_IR2_RC_DUAL_PORT_ADDED and
119 * MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED for IR2 event data.
120 * Added SASAddress field to SAS Initiator Device Table
121 * Overflow event data structure.
122 * 03-28-08 01.05.16 Added two new ReasonCode values to SAS Device Status
123 * Change Event data to indicate completion of internally
124 * generated task management.
125 * Added MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE define.
126 * Added MPI_EVENT_SAS_INIT_RC_INACCESSIBLE define.
127 * --------------------------------------------------------------------------
128 */
129
130 #ifndef MPI_IOC_H
131 #define MPI_IOC_H
132
133
134 /*****************************************************************************
135 *
136 * I O C M e s s a g e s
137 *
138 *****************************************************************************/
139
140 /****************************************************************************/
141 /* IOCInit message */
142 /****************************************************************************/
143
144 typedef struct _MSG_IOC_INIT
145 {
146 U8 WhoInit; /* 00h */
147 U8 Reserved; /* 01h */
148 U8 ChainOffset; /* 02h */
149 U8 Function; /* 03h */
150 U8 Flags; /* 04h */
151 U8 MaxDevices; /* 05h */
152 U8 MaxBuses; /* 06h */
153 U8 MsgFlags; /* 07h */
154 U32 MsgContext; /* 08h */
155 U16 ReplyFrameSize; /* 0Ch */
156 U8 Reserved1[2]; /* 0Eh */
157 U32 HostMfaHighAddr; /* 10h */
158 U32 SenseBufferHighAddr; /* 14h */
159 U32 ReplyFifoHostSignalingAddr; /* 18h */
160 SGE_SIMPLE_UNION HostPageBufferSGE; /* 1Ch */
161 U16 MsgVersion; /* 28h */
162 U16 HeaderVersion; /* 2Ah */
163 } MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT,
164 IOCInit_t, MPI_POINTER pIOCInit_t;
165
166 /* WhoInit values */
167 #define MPI_WHOINIT_NO_ONE (0x00)
168 #define MPI_WHOINIT_SYSTEM_BIOS (0x01)
169 #define MPI_WHOINIT_ROM_BIOS (0x02)
170 #define MPI_WHOINIT_PCI_PEER (0x03)
171 #define MPI_WHOINIT_HOST_DRIVER (0x04)
172 #define MPI_WHOINIT_MANUFACTURER (0x05)
173
174 /* Flags values */
175 #define MPI_IOCINIT_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04)
176 #define MPI_IOCINIT_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02)
177 #define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01)
178
179 /* MsgVersion */
180 #define MPI_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
181 #define MPI_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
182 #define MPI_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
183 #define MPI_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
184
185 /* HeaderVersion */
186 #define MPI_IOCINIT_HEADERVERSION_UNIT_MASK (0xFF00)
187 #define MPI_IOCINIT_HEADERVERSION_UNIT_SHIFT (8)
188 #define MPI_IOCINIT_HEADERVERSION_DEV_MASK (0x00FF)
189 #define MPI_IOCINIT_HEADERVERSION_DEV_SHIFT (0)
190
191
192 typedef struct _MSG_IOC_INIT_REPLY
193 {
194 U8 WhoInit; /* 00h */
195 U8 Reserved; /* 01h */
196 U8 MsgLength; /* 02h */
197 U8 Function; /* 03h */
198 U8 Flags; /* 04h */
199 U8 MaxDevices; /* 05h */
200 U8 MaxBuses; /* 06h */
201 U8 MsgFlags; /* 07h */
202 U32 MsgContext; /* 08h */
203 U16 Reserved2; /* 0Ch */
204 U16 IOCStatus; /* 0Eh */
205 U32 IOCLogInfo; /* 10h */
206 } MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY,
207 IOCInitReply_t, MPI_POINTER pIOCInitReply_t;
208
209
210
211 /****************************************************************************/
212 /* IOC Facts message */
213 /****************************************************************************/
214
215 typedef struct _MSG_IOC_FACTS
216 {
217 U8 Reserved[2]; /* 00h */
218 U8 ChainOffset; /* 01h */
219 U8 Function; /* 02h */
220 U8 Reserved1[3]; /* 03h */
221 U8 MsgFlags; /* 04h */
222 U32 MsgContext; /* 08h */
223 } MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS,
224 IOCFacts_t, MPI_POINTER pIOCFacts_t;
225
226 typedef struct _MPI_FW_VERSION_STRUCT
227 {
228 U8 Dev; /* 00h */
229 U8 Unit; /* 01h */
230 U8 Minor; /* 02h */
231 U8 Major; /* 03h */
232 } MPI_FW_VERSION_STRUCT;
233
234 typedef union _MPI_FW_VERSION
235 {
236 MPI_FW_VERSION_STRUCT Struct;
237 U32 Word;
238 } MPI_FW_VERSION;
239
240 /* IOC Facts Reply */
241 typedef struct _MSG_IOC_FACTS_REPLY
242 {
243 U16 MsgVersion; /* 00h */
244 U8 MsgLength; /* 02h */
245 U8 Function; /* 03h */
246 U16 HeaderVersion; /* 04h */
247 U8 IOCNumber; /* 06h */
248 U8 MsgFlags; /* 07h */
249 U32 MsgContext; /* 08h */
250 U16 IOCExceptions; /* 0Ch */
251 U16 IOCStatus; /* 0Eh */
252 U32 IOCLogInfo; /* 10h */
253 U8 MaxChainDepth; /* 14h */
254 U8 WhoInit; /* 15h */
255 U8 BlockSize; /* 16h */
256 U8 Flags; /* 17h */
257 U16 ReplyQueueDepth; /* 18h */
258 U16 RequestFrameSize; /* 1Ah */
259 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */
260 U16 ProductID; /* 1Eh */
261 U32 CurrentHostMfaHighAddr; /* 20h */
262 U16 GlobalCredits; /* 24h */
263 U8 NumberOfPorts; /* 26h */
264 U8 EventState; /* 27h */
265 U32 CurrentSenseBufferHighAddr; /* 28h */
266 U16 CurReplyFrameSize; /* 2Ch */
267 U8 MaxDevices; /* 2Eh */
268 U8 MaxBuses; /* 2Fh */
269 U32 FWImageSize; /* 30h */
270 U32 IOCCapabilities; /* 34h */
271 MPI_FW_VERSION FWVersion; /* 38h */
272 U16 HighPriorityQueueDepth; /* 3Ch */
273 U16 Reserved2; /* 3Eh */
274 SGE_SIMPLE_UNION HostPageBufferSGE; /* 40h */
275 U32 ReplyFifoHostSignalingAddr; /* 4Ch */
276 } MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY,
277 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t;
278
279 #define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
280 #define MPI_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
281 #define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
282 #define MPI_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
283
284 #define MPI_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
285 #define MPI_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
286 #define MPI_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
287 #define MPI_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
288
289 #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
290 #define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
291 #define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
292 #define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL (0x0008)
293 #define MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
294
295 #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01)
296 #define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02)
297 #define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04)
298
299 #define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00)
300 #define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01)
301
302 #define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q (0x00000001)
303 #define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL (0x00000002)
304 #define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING (0x00000004)
305 #define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
306 #define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
307 #define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
308 #define MPI_IOCFACTS_CAPABILITY_EEDP (0x00000040)
309 #define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL (0x00000080)
310 #define MPI_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
311 #define MPI_IOCFACTS_CAPABILITY_SCSIIO32 (0x00000200)
312 #define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16 (0x00000400)
313 #define MPI_IOCFACTS_CAPABILITY_TLR (0x00000800)
314
315
316 /*****************************************************************************
317 *
318 * P o r t M e s s a g e s
319 *
320 *****************************************************************************/
321
322 /****************************************************************************/
323 /* Port Facts message and Reply */
324 /****************************************************************************/
325
326 typedef struct _MSG_PORT_FACTS
327 {
328 U8 Reserved[2]; /* 00h */
329 U8 ChainOffset; /* 02h */
330 U8 Function; /* 03h */
331 U8 Reserved1[2]; /* 04h */
332 U8 PortNumber; /* 06h */
333 U8 MsgFlags; /* 07h */
334 U32 MsgContext; /* 08h */
335 } MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS,
336 PortFacts_t, MPI_POINTER pPortFacts_t;
337
338 typedef struct _MSG_PORT_FACTS_REPLY
339 {
340 U16 Reserved; /* 00h */
341 U8 MsgLength; /* 02h */
342 U8 Function; /* 03h */
343 U16 Reserved1; /* 04h */
344 U8 PortNumber; /* 06h */
345 U8 MsgFlags; /* 07h */
346 U32 MsgContext; /* 08h */
347 U16 Reserved2; /* 0Ch */
348 U16 IOCStatus; /* 0Eh */
349 U32 IOCLogInfo; /* 10h */
350 U8 Reserved3; /* 14h */
351 U8 PortType; /* 15h */
352 U16 MaxDevices; /* 16h */
353 U16 PortSCSIID; /* 18h */
354 U16 ProtocolFlags; /* 1Ah */
355 U16 MaxPostedCmdBuffers; /* 1Ch */
356 U16 MaxPersistentIDs; /* 1Eh */
357 U16 MaxLanBuckets; /* 20h */
358 U8 MaxInitiators; /* 22h */
359 U8 Reserved4; /* 23h */
360 U32 Reserved5; /* 24h */
361 } MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY,
362 PortFactsReply_t, MPI_POINTER pPortFactsReply_t;
363
364
365 /* PortTypes values */
366
367 #define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00)
368 #define MPI_PORTFACTS_PORTTYPE_SCSI (0x01)
369 #define MPI_PORTFACTS_PORTTYPE_FC (0x10)
370 #define MPI_PORTFACTS_PORTTYPE_ISCSI (0x20)
371 #define MPI_PORTFACTS_PORTTYPE_SAS (0x30)
372
373 /* ProtocolFlags values */
374
375 #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01)
376 #define MPI_PORTFACTS_PROTOCOL_LAN (0x02)
377 #define MPI_PORTFACTS_PROTOCOL_TARGET (0x04)
378 #define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08)
379
380
381 /****************************************************************************/
382 /* Port Enable Message */
383 /****************************************************************************/
384
385 typedef struct _MSG_PORT_ENABLE
386 {
387 U8 Reserved[2]; /* 00h */
388 U8 ChainOffset; /* 02h */
389 U8 Function; /* 03h */
390 U8 Reserved1[2]; /* 04h */
391 U8 PortNumber; /* 06h */
392 U8 MsgFlags; /* 07h */
393 U32 MsgContext; /* 08h */
394 } MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE,
395 PortEnable_t, MPI_POINTER pPortEnable_t;
396
397 typedef struct _MSG_PORT_ENABLE_REPLY
398 {
399 U8 Reserved[2]; /* 00h */
400 U8 MsgLength; /* 02h */
401 U8 Function; /* 03h */
402 U8 Reserved1[2]; /* 04h */
403 U8 PortNumber; /* 05h */
404 U8 MsgFlags; /* 07h */
405 U32 MsgContext; /* 08h */
406 U16 Reserved2; /* 0Ch */
407 U16 IOCStatus; /* 0Eh */
408 U32 IOCLogInfo; /* 10h */
409 } MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY,
410 PortEnableReply_t, MPI_POINTER pPortEnableReply_t;
411
412
413 /*****************************************************************************
414 *
415 * E v e n t M e s s a g e s
416 *
417 *****************************************************************************/
418
419 /****************************************************************************/
420 /* Event Notification messages */
421 /****************************************************************************/
422
423 typedef struct _MSG_EVENT_NOTIFY
424 {
425 U8 Switch; /* 00h */
426 U8 Reserved; /* 01h */
427 U8 ChainOffset; /* 02h */
428 U8 Function; /* 03h */
429 U8 Reserved1[3]; /* 04h */
430 U8 MsgFlags; /* 07h */
431 U32 MsgContext; /* 08h */
432 } MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY,
433 EventNotification_t, MPI_POINTER pEventNotification_t;
434
435 /* Event Notification Reply */
436
437 typedef struct _MSG_EVENT_NOTIFY_REPLY
438 {
439 U16 EventDataLength; /* 00h */
440 U8 MsgLength; /* 02h */
441 U8 Function; /* 03h */
442 U8 Reserved1[2]; /* 04h */
443 U8 AckRequired; /* 06h */
444 U8 MsgFlags; /* 07h */
445 U32 MsgContext; /* 08h */
446 U8 Reserved2[2]; /* 0Ch */
447 U16 IOCStatus; /* 0Eh */
448 U32 IOCLogInfo; /* 10h */
449 U32 Event; /* 14h */
450 U32 EventContext; /* 18h */
451 U32 Data[1]; /* 1Ch */
452 } MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY,
453 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t;
454
455 /* Event Acknowledge */
456
457 typedef struct _MSG_EVENT_ACK
458 {
459 U8 Reserved[2]; /* 00h */
460 U8 ChainOffset; /* 02h */
461 U8 Function; /* 03h */
462 U8 Reserved1[3]; /* 04h */
463 U8 MsgFlags; /* 07h */
464 U32 MsgContext; /* 08h */
465 U32 Event; /* 0Ch */
466 U32 EventContext; /* 10h */
467 } MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK,
468 EventAck_t, MPI_POINTER pEventAck_t;
469
470 typedef struct _MSG_EVENT_ACK_REPLY
471 {
472 U8 Reserved[2]; /* 00h */
473 U8 MsgLength; /* 02h */
474 U8 Function; /* 03h */
475 U8 Reserved1[3]; /* 04h */
476 U8 MsgFlags; /* 07h */
477 U32 MsgContext; /* 08h */
478 U16 Reserved2; /* 0Ch */
479 U16 IOCStatus; /* 0Eh */
480 U32 IOCLogInfo; /* 10h */
481 } MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY,
482 EventAckReply_t, MPI_POINTER pEventAckReply_t;
483
484 /* Switch */
485
486 #define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00)
487 #define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01)
488
489 /* Event */
490
491 #define MPI_EVENT_NONE (0x00000000)
492 #define MPI_EVENT_LOG_DATA (0x00000001)
493 #define MPI_EVENT_STATE_CHANGE (0x00000002)
494 #define MPI_EVENT_UNIT_ATTENTION (0x00000003)
495 #define MPI_EVENT_IOC_BUS_RESET (0x00000004)
496 #define MPI_EVENT_EXT_BUS_RESET (0x00000005)
497 #define MPI_EVENT_RESCAN (0x00000006)
498 #define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007)
499 #define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008)
500 #define MPI_EVENT_LOGOUT (0x00000009)
501 #define MPI_EVENT_EVENT_CHANGE (0x0000000A)
502 #define MPI_EVENT_INTEGRATED_RAID (0x0000000B)
503 #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C)
504 #define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D)
505 #define MPI_EVENT_QUEUE_FULL (0x0000000E)
506 #define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0000000F)
507 #define MPI_EVENT_SAS_SES (0x00000010)
508 #define MPI_EVENT_PERSISTENT_TABLE_FULL (0x00000011)
509 #define MPI_EVENT_SAS_PHY_LINK_STATUS (0x00000012)
510 #define MPI_EVENT_SAS_DISCOVERY_ERROR (0x00000013)
511 #define MPI_EVENT_IR_RESYNC_UPDATE (0x00000014)
512 #define MPI_EVENT_IR2 (0x00000015)
513 #define MPI_EVENT_SAS_DISCOVERY (0x00000016)
514 #define MPI_EVENT_SAS_BROADCAST_PRIMITIVE (0x00000017)
515 #define MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x00000018)
516 #define MPI_EVENT_SAS_INIT_TABLE_OVERFLOW (0x00000019)
517 #define MPI_EVENT_SAS_SMP_ERROR (0x0000001A)
518 #define MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE (0x0000001B)
519 #define MPI_EVENT_LOG_ENTRY_ADDED (0x00000021)
520
521 /* AckRequired field values */
522
523 #define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
524 #define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
525
526 /* EventChange Event data */
527
528 typedef struct _EVENT_DATA_EVENT_CHANGE
529 {
530 U8 EventState; /* 00h */
531 U8 Reserved; /* 01h */
532 U16 Reserved1; /* 02h */
533 } EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE,
534 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t;
535
536 /* LogEntryAdded Event data */
537
538 /* this structure matches MPI_LOG_0_ENTRY in mpi_cnfg.h */
539 #define MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH (0x1C)
540 typedef struct _EVENT_DATA_LOG_ENTRY
541 {
542 U32 TimeStamp; /* 00h */
543 U32 Reserved1; /* 04h */
544 U16 LogSequence; /* 08h */
545 U16 LogEntryQualifier; /* 0Ah */
546 U8 LogData[MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH]; /* 0Ch */
547 } EVENT_DATA_LOG_ENTRY, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY,
548 MpiEventDataLogEntry_t, MPI_POINTER pMpiEventDataLogEntry_t;
549
550 typedef struct _EVENT_DATA_LOG_ENTRY_ADDED
551 {
552 U16 LogSequence; /* 00h */
553 U16 Reserved1; /* 02h */
554 U32 Reserved2; /* 04h */
555 EVENT_DATA_LOG_ENTRY LogEntry; /* 08h */
556 } EVENT_DATA_LOG_ENTRY_ADDED, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY_ADDED,
557 MpiEventDataLogEntryAdded_t, MPI_POINTER pMpiEventDataLogEntryAdded_t;
558
559 /* SCSI Event data for Port, Bus and Device forms */
560
561 typedef struct _EVENT_DATA_SCSI
562 {
563 U8 TargetID; /* 00h */
564 U8 BusPort; /* 01h */
565 U16 Reserved; /* 02h */
566 } EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI,
567 EventDataScsi_t, MPI_POINTER pEventDataScsi_t;
568
569 /* SCSI Device Status Change Event data */
570
571 typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE
572 {
573 U8 TargetID; /* 00h */
574 U8 Bus; /* 01h */
575 U8 ReasonCode; /* 02h */
576 U8 LUN; /* 03h */
577 U8 ASC; /* 04h */
578 U8 ASCQ; /* 05h */
579 U16 Reserved; /* 06h */
580 } EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE,
581 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE,
582 MpiEventDataScsiDeviceStatusChange_t,
583 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t;
584
585 /* MPI SCSI Device Status Change Event data ReasonCode values */
586 #define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03)
587 #define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04)
588 #define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05)
589
590 /* SAS Device Status Change Event data */
591
592 typedef struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
593 {
594 U8 TargetID; /* 00h */
595 U8 Bus; /* 01h */
596 U8 ReasonCode; /* 02h */
597 U8 Reserved; /* 03h */
598 U8 ASC; /* 04h */
599 U8 ASCQ; /* 05h */
600 U16 DevHandle; /* 06h */
601 U32 DeviceInfo; /* 08h */
602 U16 ParentDevHandle; /* 0Ch */
603 U8 PhyNum; /* 0Eh */
604 U8 Reserved1; /* 0Fh */
605 U64 SASAddress; /* 10h */
606 U8 LUN[8]; /* 18h */
607 U16 TaskTag; /* 20h */
608 U16 Reserved2; /* 22h */
609 } EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
610 MPI_POINTER PTR_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
611 MpiEventDataSasDeviceStatusChange_t,
612 MPI_POINTER pMpiEventDataSasDeviceStatusChange_t;
613
614 /* MPI SAS Device Status Change Event data ReasonCode values */
615 #define MPI_EVENT_SAS_DEV_STAT_RC_ADDED (0x03)
616 #define MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING (0x04)
617 #define MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
618 #define MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED (0x06)
619 #define MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
620 #define MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
621 #define MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
622 #define MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
623 #define MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
624 #define MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
625 #define MPI_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
626 #define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_INTERNAL_DEV_RESET (0x0E)
627 #define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_TASK_ABORT_INTERNAL (0x0F)
628
629
630 /* SCSI Event data for Queue Full event */
631
632 typedef struct _EVENT_DATA_QUEUE_FULL
633 {
634 U8 TargetID; /* 00h */
635 U8 Bus; /* 01h */
636 U16 CurrentDepth; /* 02h */
637 } EVENT_DATA_QUEUE_FULL, MPI_POINTER PTR_EVENT_DATA_QUEUE_FULL,
638 EventDataQueueFull_t, MPI_POINTER pEventDataQueueFull_t;
639
640 /* MPI Integrated RAID Event data */
641
642 typedef struct _EVENT_DATA_RAID
643 {
644 U8 VolumeID; /* 00h */
645 U8 VolumeBus; /* 01h */
646 U8 ReasonCode; /* 02h */
647 U8 PhysDiskNum; /* 03h */
648 U8 ASC; /* 04h */
649 U8 ASCQ; /* 05h */
650 U16 Reserved; /* 06h */
651 U32 SettingsStatus; /* 08h */
652 } EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID,
653 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t;
654
655 /* MPI Integrated RAID Event data ReasonCode values */
656 #define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00)
657 #define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01)
658 #define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02)
659 #define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03)
660 #define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04)
661 #define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05)
662 #define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06)
663 #define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07)
664 #define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08)
665 #define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09)
666 #define MPI_EVENT_RAID_RC_SMART_DATA (0x0A)
667 #define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B)
668
669
670 /* MPI Integrated RAID Resync Update Event data */
671
672 typedef struct _MPI_EVENT_DATA_IR_RESYNC_UPDATE
673 {
674 U8 VolumeID; /* 00h */
675 U8 VolumeBus; /* 01h */
676 U8 ResyncComplete; /* 02h */
677 U8 Reserved1; /* 03h */
678 U32 Reserved2; /* 04h */
679 } MPI_EVENT_DATA_IR_RESYNC_UPDATE,
680 MPI_POINTER PTR_MPI_EVENT_DATA_IR_RESYNC_UPDATE,
681 MpiEventDataIrResyncUpdate_t, MPI_POINTER pMpiEventDataIrResyncUpdate_t;
682
683 /* MPI IR2 Event data */
684
685 /* MPI_LD_STATE or MPI_PD_STATE */
686 typedef struct _IR2_STATE_CHANGED
687 {
688 U16 PreviousState; /* 00h */
689 U16 NewState; /* 02h */
690 } IR2_STATE_CHANGED, MPI_POINTER PTR_IR2_STATE_CHANGED;
691
692 typedef struct _IR2_PD_INFO
693 {
694 U16 DeviceHandle; /* 00h */
695 U8 TruncEnclosureHandle; /* 02h */
696 U8 TruncatedSlot; /* 03h */
697 } IR2_PD_INFO, MPI_POINTER PTR_IR2_PD_INFO;
698
699 typedef union _MPI_IR2_RC_EVENT_DATA
700 {
701 IR2_STATE_CHANGED StateChanged;
702 U32 Lba;
703 IR2_PD_INFO PdInfo;
704 } MPI_IR2_RC_EVENT_DATA, MPI_POINTER PTR_MPI_IR2_RC_EVENT_DATA;
705
706 typedef struct _MPI_EVENT_DATA_IR2
707 {
708 U8 TargetID; /* 00h */
709 U8 Bus; /* 01h */
710 U8 ReasonCode; /* 02h */
711 U8 PhysDiskNum; /* 03h */
712 MPI_IR2_RC_EVENT_DATA IR2EventData; /* 04h */
713 } MPI_EVENT_DATA_IR2, MPI_POINTER PTR_MPI_EVENT_DATA_IR2,
714 MpiEventDataIR2_t, MPI_POINTER pMpiEventDataIR2_t;
715
716 /* MPI IR2 Event data ReasonCode values */
717 #define MPI_EVENT_IR2_RC_LD_STATE_CHANGED (0x01)
718 #define MPI_EVENT_IR2_RC_PD_STATE_CHANGED (0x02)
719 #define MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL (0x03)
720 #define MPI_EVENT_IR2_RC_PD_INSERTED (0x04)
721 #define MPI_EVENT_IR2_RC_PD_REMOVED (0x05)
722 #define MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED (0x06)
723 #define MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR (0x07)
724 #define MPI_EVENT_IR2_RC_DUAL_PORT_ADDED (0x08)
725 #define MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED (0x09)
726
727 /* defines for logical disk states */
728 #define MPI_LD_STATE_OPTIMAL (0x00)
729 #define MPI_LD_STATE_DEGRADED (0x01)
730 #define MPI_LD_STATE_FAILED (0x02)
731 #define MPI_LD_STATE_MISSING (0x03)
732 #define MPI_LD_STATE_OFFLINE (0x04)
733
734 /* defines for physical disk states */
735 #define MPI_PD_STATE_ONLINE (0x00)
736 #define MPI_PD_STATE_MISSING (0x01)
737 #define MPI_PD_STATE_NOT_COMPATIBLE (0x02)
738 #define MPI_PD_STATE_FAILED (0x03)
739 #define MPI_PD_STATE_INITIALIZING (0x04)
740 #define MPI_PD_STATE_OFFLINE_AT_HOST_REQUEST (0x05)
741 #define MPI_PD_STATE_FAILED_AT_HOST_REQUEST (0x06)
742 #define MPI_PD_STATE_OFFLINE_FOR_ANOTHER_REASON (0xFF)
743
744 /* MPI Link Status Change Event data */
745
746 typedef struct _EVENT_DATA_LINK_STATUS
747 {
748 U8 State; /* 00h */
749 U8 Reserved; /* 01h */
750 U16 Reserved1; /* 02h */
751 U8 Reserved2; /* 04h */
752 U8 Port; /* 05h */
753 U16 Reserved3; /* 06h */
754 } EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS,
755 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t;
756
757 #define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000)
758 #define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001)
759
760 /* MPI Loop State Change Event data */
761
762 typedef struct _EVENT_DATA_LOOP_STATE
763 {
764 U8 Character4; /* 00h */
765 U8 Character3; /* 01h */
766 U8 Type; /* 02h */
767 U8 Reserved; /* 03h */
768 U8 Reserved1; /* 04h */
769 U8 Port; /* 05h */
770 U16 Reserved2; /* 06h */
771 } EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE,
772 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t;
773
774 #define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001)
775 #define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002)
776 #define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003)
777
778 /* MPI LOGOUT Event data */
779
780 typedef struct _EVENT_DATA_LOGOUT
781 {
782 U32 NPortID; /* 00h */
783 U8 AliasIndex; /* 04h */
784 U8 Port; /* 05h */
785 U16 Reserved1; /* 06h */
786 } EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT,
787 EventDataLogout_t, MPI_POINTER pEventDataLogout_t;
788
789 #define MPI_EVENT_LOGOUT_ALL_ALIASES (0xFF)
790
791 /* SAS SES Event data */
792
793 typedef struct _EVENT_DATA_SAS_SES
794 {
795 U8 PhyNum; /* 00h */
796 U8 Port; /* 01h */
797 U8 PortWidth; /* 02h */
798 U8 Reserved1; /* 04h */
799 } EVENT_DATA_SAS_SES, MPI_POINTER PTR_EVENT_DATA_SAS_SES,
800 MpiEventDataSasSes_t, MPI_POINTER pMpiEventDataSasSes_t;
801
802 /* SAS Broadcast Primitive Event data */
803
804 typedef struct _EVENT_DATA_SAS_BROADCAST_PRIMITIVE
805 {
806 U8 PhyNum; /* 00h */
807 U8 Port; /* 01h */
808 U8 PortWidth; /* 02h */
809 U8 Primitive; /* 04h */
810 } EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
811 MPI_POINTER PTR_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
812 MpiEventDataSasBroadcastPrimitive_t,
813 MPI_POINTER pMpiEventDataSasBroadcastPrimitive_t;
814
815 #define MPI_EVENT_PRIMITIVE_CHANGE (0x01)
816 #define MPI_EVENT_PRIMITIVE_EXPANDER (0x03)
817 #define MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
818 #define MPI_EVENT_PRIMITIVE_RESERVED3 (0x05)
819 #define MPI_EVENT_PRIMITIVE_RESERVED4 (0x06)
820 #define MPI_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
821 #define MPI_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
822
823 /* SAS Phy Link Status Event data */
824
825 typedef struct _EVENT_DATA_SAS_PHY_LINK_STATUS
826 {
827 U8 PhyNum; /* 00h */
828 U8 LinkRates; /* 01h */
829 U16 DevHandle; /* 02h */
830 U64 SASAddress; /* 04h */
831 } EVENT_DATA_SAS_PHY_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_SAS_PHY_LINK_STATUS,
832 MpiEventDataSasPhyLinkStatus_t, MPI_POINTER pMpiEventDataSasPhyLinkStatus_t;
833
834 /* defines for the LinkRates field of the SAS PHY Link Status event */
835 #define MPI_EVENT_SAS_PLS_LR_CURRENT_MASK (0xF0)
836 #define MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT (4)
837 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK (0x0F)
838 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT (0)
839 #define MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN (0x00)
840 #define MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED (0x01)
841 #define MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION (0x02)
842 #define MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE (0x03)
843 #define MPI_EVENT_SAS_PLS_LR_RATE_1_5 (0x08)
844 #define MPI_EVENT_SAS_PLS_LR_RATE_3_0 (0x09)
845 #define MPI_EVENT_SAS_PLS_LR_RATE_6_0 (0x0A)
846
847 /* SAS Discovery Event data */
848
849 typedef struct _EVENT_DATA_SAS_DISCOVERY
850 {
851 U32 DiscoveryStatus; /* 00h */
852 U32 Reserved1; /* 04h */
853 } EVENT_DATA_SAS_DISCOVERY, MPI_POINTER PTR_EVENT_DATA_SAS_DISCOVERY,
854 EventDataSasDiscovery_t, MPI_POINTER pEventDataSasDiscovery_t;
855
856 #define MPI_EVENT_SAS_DSCVRY_COMPLETE (0x00000000)
857 #define MPI_EVENT_SAS_DSCVRY_IN_PROGRESS (0x00000001)
858 #define MPI_EVENT_SAS_DSCVRY_PHY_BITS_MASK (0xFFFF0000)
859 #define MPI_EVENT_SAS_DSCVRY_PHY_BITS_SHIFT (16)
860
861 /* SAS Discovery Error Event data */
862
863 typedef struct _EVENT_DATA_DISCOVERY_ERROR
864 {
865 U32 DiscoveryStatus; /* 00h */
866 U8 Port; /* 04h */
867 U8 Reserved1; /* 05h */
868 U16 Reserved2; /* 06h */
869 } EVENT_DATA_DISCOVERY_ERROR, MPI_POINTER PTR_EVENT_DATA_DISCOVERY_ERROR,
870 EventDataDiscoveryError_t, MPI_POINTER pEventDataDiscoveryError_t;
871
872 #define MPI_EVENT_DSCVRY_ERR_DS_LOOP_DETECTED (0x00000001)
873 #define MPI_EVENT_DSCVRY_ERR_DS_UNADDRESSABLE_DEVICE (0x00000002)
874 #define MPI_EVENT_DSCVRY_ERR_DS_MULTIPLE_PORTS (0x00000004)
875 #define MPI_EVENT_DSCVRY_ERR_DS_EXPANDER_ERR (0x00000008)
876 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_TIMEOUT (0x00000010)
877 #define MPI_EVENT_DSCVRY_ERR_DS_OUT_ROUTE_ENTRIES (0x00000020)
878 #define MPI_EVENT_DSCVRY_ERR_DS_INDEX_NOT_EXIST (0x00000040)
879 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_FUNCTION_FAILED (0x00000080)
880 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_CRC_ERROR (0x00000100)
881 #define MPI_EVENT_DSCVRY_ERR_DS_MULTPL_SUBTRACTIVE (0x00000200)
882 #define MPI_EVENT_DSCVRY_ERR_DS_TABLE_TO_TABLE (0x00000400)
883 #define MPI_EVENT_DSCVRY_ERR_DS_UNSUPPORTED_DEVICE (0x00000800)
884 #define MPI_EVENT_DSCVRY_ERR_DS_MAX_SATA_TARGETS (0x00001000)
885 #define MPI_EVENT_DSCVRY_ERR_DS_MULTI_PORT_DOMAIN (0x00002000)
886 #define MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE (0x00004000)
887
888 /* SAS SMP Error Event data */
889
890 typedef struct _EVENT_DATA_SAS_SMP_ERROR
891 {
892 U8 Status; /* 00h */
893 U8 Port; /* 01h */
894 U8 SMPFunctionResult; /* 02h */
895 U8 Reserved1; /* 03h */
896 U64 SASAddress; /* 04h */
897 } EVENT_DATA_SAS_SMP_ERROR, MPI_POINTER PTR_EVENT_DATA_SAS_SMP_ERROR,
898 MpiEventDataSasSmpError_t, MPI_POINTER pMpiEventDataSasSmpError_t;
899
900 /* defines for the Status field of the SAS SMP Error event */
901 #define MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID (0x00)
902 #define MPI_EVENT_SAS_SMP_CRC_ERROR (0x01)
903 #define MPI_EVENT_SAS_SMP_TIMEOUT (0x02)
904 #define MPI_EVENT_SAS_SMP_NO_DESTINATION (0x03)
905 #define MPI_EVENT_SAS_SMP_BAD_DESTINATION (0x04)
906
907 /* SAS Initiator Device Status Change Event data */
908
909 typedef struct _EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
910 {
911 U8 ReasonCode; /* 00h */
912 U8 Port; /* 01h */
913 U16 DevHandle; /* 02h */
914 U64 SASAddress; /* 04h */
915 } EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
916 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
917 MpiEventDataSasInitDevStatusChange_t,
918 MPI_POINTER pMpiEventDataSasInitDevStatusChange_t;
919
920 /* defines for the ReasonCode field of the SAS Initiator Device Status Change event */
921 #define MPI_EVENT_SAS_INIT_RC_ADDED (0x01)
922 #define MPI_EVENT_SAS_INIT_RC_REMOVED (0x02)
923 #define MPI_EVENT_SAS_INIT_RC_INACCESSIBLE (0x03)
924
925 /* SAS Initiator Device Table Overflow Event data */
926
927 typedef struct _EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
928 {
929 U8 MaxInit; /* 00h */
930 U8 CurrentInit; /* 01h */
931 U16 Reserved1; /* 02h */
932 U64 SASAddress; /* 04h */
933 } EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
934 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
935 MpiEventDataSasInitTableOverflow_t,
936 MPI_POINTER pMpiEventDataSasInitTableOverflow_t;
937
938 /* SAS Expander Status Change Event data */
939
940 typedef struct _EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE
941 {
942 U8 ReasonCode; /* 00h */
943 U8 Reserved1; /* 01h */
944 U16 Reserved2; /* 02h */
945 U8 PhysicalPort; /* 04h */
946 U8 Reserved3; /* 05h */
947 U16 EnclosureHandle; /* 06h */
948 U64 SASAddress; /* 08h */
949 U32 DiscoveryStatus; /* 10h */
950 U16 DevHandle; /* 14h */
951 U16 ParentDevHandle; /* 16h */
952 U16 ExpanderChangeCount; /* 18h */
953 U16 ExpanderRouteIndexes; /* 1Ah */
954 U8 NumPhys; /* 1Ch */
955 U8 SASLevel; /* 1Dh */
956 U8 Flags; /* 1Eh */
957 U8 Reserved4; /* 1Fh */
958 } EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE,
959 MPI_POINTER PTR_EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE,
960 MpiEventDataSasExpanderStatusChange_t,
961 MPI_POINTER pMpiEventDataSasExpanderStatusChange_t;
962
963 /* values for ReasonCode field of SAS Expander Status Change Event data */
964 #define MPI_EVENT_SAS_EXP_RC_ADDED (0x00)
965 #define MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING (0x01)
966
967 /* values for DiscoveryStatus field of SAS Expander Status Change Event data */
968 #define MPI_EVENT_SAS_EXP_DS_LOOP_DETECTED (0x00000001)
969 #define MPI_EVENT_SAS_EXP_DS_UNADDRESSABLE_DEVICE (0x00000002)
970 #define MPI_EVENT_SAS_EXP_DS_MULTIPLE_PORTS (0x00000004)
971 #define MPI_EVENT_SAS_EXP_DS_EXPANDER_ERR (0x00000008)
972 #define MPI_EVENT_SAS_EXP_DS_SMP_TIMEOUT (0x00000010)
973 #define MPI_EVENT_SAS_EXP_DS_OUT_ROUTE_ENTRIES (0x00000020)
974 #define MPI_EVENT_SAS_EXP_DS_INDEX_NOT_EXIST (0x00000040)
975 #define MPI_EVENT_SAS_EXP_DS_SMP_FUNCTION_FAILED (0x00000080)
976 #define MPI_EVENT_SAS_EXP_DS_SMP_CRC_ERROR (0x00000100)
977 #define MPI_EVENT_SAS_EXP_DS_SUBTRACTIVE_LINK (0x00000200)
978 #define MPI_EVENT_SAS_EXP_DS_TABLE_LINK (0x00000400)
979 #define MPI_EVENT_SAS_EXP_DS_UNSUPPORTED_DEVICE (0x00000800)
980
981 /* values for Flags field of SAS Expander Status Change Event data */
982 #define MPI_EVENT_SAS_EXP_FLAGS_ROUTE_TABLE_CONFIG (0x02)
983 #define MPI_EVENT_SAS_EXP_FLAGS_CONFIG_IN_PROGRESS (0x01)
984
985
986
987 /*****************************************************************************
988 *
989 * F i r m w a r e L o a d M e s s a g e s
990 *
991 *****************************************************************************/
992
993 /****************************************************************************/
994 /* Firmware Download message and associated structures */
995 /****************************************************************************/
996
997 typedef struct _MSG_FW_DOWNLOAD
998 {
999 U8 ImageType; /* 00h */
1000 U8 Reserved; /* 01h */
1001 U8 ChainOffset; /* 02h */
1002 U8 Function; /* 03h */
1003 U8 Reserved1[3]; /* 04h */
1004 U8 MsgFlags; /* 07h */
1005 U32 MsgContext; /* 08h */
1006 SGE_MPI_UNION SGL; /* 0Ch */
1007 } MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD,
1008 FWDownload_t, MPI_POINTER pFWDownload_t;
1009
1010 #define MPI_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1011
1012 #define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00)
1013 #define MPI_FW_DOWNLOAD_ITYPE_FW (0x01)
1014 #define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1015 #define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03)
1016 #define MPI_FW_DOWNLOAD_ITYPE_BOOTLOADER (0x04)
1017 #define MPI_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1018 #define MPI_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1019 #define MPI_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1020 #define MPI_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1021 #define MPI_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1022
1023
1024 typedef struct _FWDownloadTCSGE
1025 {
1026 U8 Reserved; /* 00h */
1027 U8 ContextSize; /* 01h */
1028 U8 DetailsLength; /* 02h */
1029 U8 Flags; /* 03h */
1030 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */
1031 U32 ImageOffset; /* 08h */
1032 U32 ImageSize; /* 0Ch */
1033 } FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE,
1034 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t;
1035
1036 /* Firmware Download reply */
1037 typedef struct _MSG_FW_DOWNLOAD_REPLY
1038 {
1039 U8 ImageType; /* 00h */
1040 U8 Reserved; /* 01h */
1041 U8 MsgLength; /* 02h */
1042 U8 Function; /* 03h */
1043 U8 Reserved1[3]; /* 04h */
1044 U8 MsgFlags; /* 07h */
1045 U32 MsgContext; /* 08h */
1046 U16 Reserved2; /* 0Ch */
1047 U16 IOCStatus; /* 0Eh */
1048 U32 IOCLogInfo; /* 10h */
1049 } MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY,
1050 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t;
1051
1052
1053 /****************************************************************************/
1054 /* Firmware Upload message and associated structures */
1055 /****************************************************************************/
1056
1057 typedef struct _MSG_FW_UPLOAD
1058 {
1059 U8 ImageType; /* 00h */
1060 U8 Reserved; /* 01h */
1061 U8 ChainOffset; /* 02h */
1062 U8 Function; /* 03h */
1063 U8 Reserved1[3]; /* 04h */
1064 U8 MsgFlags; /* 07h */
1065 U32 MsgContext; /* 08h */
1066 SGE_MPI_UNION SGL; /* 0Ch */
1067 } MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD,
1068 FWUpload_t, MPI_POINTER pFWUpload_t;
1069
1070 #define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00)
1071 #define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1072 #define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1073 #define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03)
1074 #define MPI_FW_UPLOAD_ITYPE_BOOTLOADER (0x04)
1075 #define MPI_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1076 #define MPI_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1077 #define MPI_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1078 #define MPI_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1079 #define MPI_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1080 #define MPI_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1081 #define MPI_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1082
1083 typedef struct _FWUploadTCSGE
1084 {
1085 U8 Reserved; /* 00h */
1086 U8 ContextSize; /* 01h */
1087 U8 DetailsLength; /* 02h */
1088 U8 Flags; /* 03h */
1089 U32 Reserved1; /* 04h */
1090 U32 ImageOffset; /* 08h */
1091 U32 ImageSize; /* 0Ch */
1092 } FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE,
1093 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t;
1094
1095 /* Firmware Upload reply */
1096 typedef struct _MSG_FW_UPLOAD_REPLY
1097 {
1098 U8 ImageType; /* 00h */
1099 U8 Reserved; /* 01h */
1100 U8 MsgLength; /* 02h */
1101 U8 Function; /* 03h */
1102 U8 Reserved1[3]; /* 04h */
1103 U8 MsgFlags; /* 07h */
1104 U32 MsgContext; /* 08h */
1105 U16 Reserved2; /* 0Ch */
1106 U16 IOCStatus; /* 0Eh */
1107 U32 IOCLogInfo; /* 10h */
1108 U32 ActualImageSize; /* 14h */
1109 } MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY,
1110 FWUploadReply_t, MPI_POINTER pFWUploadReply_t;
1111
1112
1113 typedef struct _MPI_FW_HEADER
1114 {
1115 U32 ArmBranchInstruction0; /* 00h */
1116 U32 Signature0; /* 04h */
1117 U32 Signature1; /* 08h */
1118 U32 Signature2; /* 0Ch */
1119 U32 ArmBranchInstruction1; /* 10h */
1120 U32 ArmBranchInstruction2; /* 14h */
1121 U32 Reserved; /* 18h */
1122 U32 Checksum; /* 1Ch */
1123 U16 VendorId; /* 20h */
1124 U16 ProductId; /* 22h */
1125 MPI_FW_VERSION FWVersion; /* 24h */
1126 U32 SeqCodeVersion; /* 28h */
1127 U32 ImageSize; /* 2Ch */
1128 U32 NextImageHeaderOffset; /* 30h */
1129 U32 LoadStartAddress; /* 34h */
1130 U32 IopResetVectorValue; /* 38h */
1131 U32 IopResetRegAddr; /* 3Ch */
1132 U32 VersionNameWhat; /* 40h */
1133 U8 VersionName[32]; /* 44h */
1134 U32 VendorNameWhat; /* 64h */
1135 U8 VendorName[32]; /* 68h */
1136 } MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER,
1137 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t;
1138
1139 #define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1140
1141 /* defines for using the ProductId field */
1142 #define MPI_FW_HEADER_PID_TYPE_MASK (0xF000)
1143 #define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000)
1144 #define MPI_FW_HEADER_PID_TYPE_FC (0x1000)
1145 #define MPI_FW_HEADER_PID_TYPE_SAS (0x2000)
1146
1147 #define MPI_FW_HEADER_SIGNATURE_0 (0x5AEAA55A)
1148 #define MPI_FW_HEADER_SIGNATURE_1 (0xA55AEAA5)
1149 #define MPI_FW_HEADER_SIGNATURE_2 (0x5AA55AEA)
1150
1151 #define MPI_FW_HEADER_PID_PROD_MASK (0x0F00)
1152 #define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100)
1153 #define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1154 #define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300)
1155 #define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400)
1156 #define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500)
1157 #define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600)
1158 #define MPI_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1159
1160 #define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1161 /* SCSI */
1162 #define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001)
1163 #define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002)
1164 #define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003)
1165 #define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004)
1166 #define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005)
1167 #define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006)
1168 #define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007)
1169 #define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008)
1170 #define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009)
1171 #define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A)
1172 #define MPI_FW_HEADER_PID_FAMILY_1030TA0_SCSI (0x000B)
1173 #define MPI_FW_HEADER_PID_FAMILY_1020TA0_SCSI (0x000C)
1174 /* Fibre Channel */
1175 #define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000)
1176 #define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) /* 919 and 929 */
1177 #define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) /* 919X and 929X */
1178 #define MPI_FW_HEADER_PID_FAMILY_919XL_FC (0x0003) /* 919XL and 929XL */
1179 #define MPI_FW_HEADER_PID_FAMILY_939X_FC (0x0004) /* 939X and 949X */
1180 #define MPI_FW_HEADER_PID_FAMILY_959_FC (0x0005)
1181 #define MPI_FW_HEADER_PID_FAMILY_949E_FC (0x0006)
1182 /* SAS */
1183 #define MPI_FW_HEADER_PID_FAMILY_1064_SAS (0x0001)
1184 #define MPI_FW_HEADER_PID_FAMILY_1068_SAS (0x0002)
1185 #define MPI_FW_HEADER_PID_FAMILY_1078_SAS (0x0003)
1186 #define MPI_FW_HEADER_PID_FAMILY_106xE_SAS (0x0004) /* 1068E, 1066E, and 1064E */
1187
1188 typedef struct _MPI_EXT_IMAGE_HEADER
1189 {
1190 U8 ImageType; /* 00h */
1191 U8 Reserved; /* 01h */
1192 U16 Reserved1; /* 02h */
1193 U32 Checksum; /* 04h */
1194 U32 ImageSize; /* 08h */
1195 U32 NextImageHeaderOffset; /* 0Ch */
1196 U32 LoadStartAddress; /* 10h */
1197 U32 Reserved2; /* 14h */
1198 } MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER,
1199 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t;
1200
1201 /* defines for the ImageType field */
1202 #define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1203 #define MPI_EXT_IMAGE_TYPE_FW (0x01)
1204 #define MPI_EXT_IMAGE_TYPE_NVDATA (0x03)
1205 #define MPI_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1206 #define MPI_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1207
1208 #endif