This source file includes following definitions.
- r8a774c0_cpg_mssr_init
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13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/soc/renesas/rcar-rst.h>
17
18 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
19
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
22
23 enum clk_ids {
24
25 LAST_DT_CORE_CLK = R8A774C0_CLK_CANFD,
26
27
28 CLK_EXTAL,
29
30
31 CLK_MAIN,
32 CLK_PLL0,
33 CLK_PLL1,
34 CLK_PLL3,
35 CLK_PLL0D4,
36 CLK_PLL0D6,
37 CLK_PLL0D8,
38 CLK_PLL0D20,
39 CLK_PLL0D24,
40 CLK_PLL1D2,
41 CLK_PE,
42 CLK_S0,
43 CLK_S1,
44 CLK_S2,
45 CLK_S3,
46 CLK_SDSRC,
47 CLK_RINT,
48 CLK_OCO,
49
50
51 MOD_CLK_BASE
52 };
53
54 static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
55
56 DEF_INPUT("extal", CLK_EXTAL),
57
58
59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
60 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
62
63 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
64 DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
65 DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
66 DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
67 DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
68 DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
69 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
70 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
71 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
72 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
73 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
74 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
75 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
76
77 DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
78
79 DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
80
81
82 DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),
83 DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),
84 DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
85 DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
86 DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),
87 DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
88 DEF_FIXED("s0d1", R8A774C0_CLK_S0D1, CLK_S0, 1, 1),
89 DEF_FIXED("s0d3", R8A774C0_CLK_S0D3, CLK_S0, 3, 1),
90 DEF_FIXED("s0d6", R8A774C0_CLK_S0D6, CLK_S0, 6, 1),
91 DEF_FIXED("s0d12", R8A774C0_CLK_S0D12, CLK_S0, 12, 1),
92 DEF_FIXED("s0d24", R8A774C0_CLK_S0D24, CLK_S0, 24, 1),
93 DEF_FIXED("s1d1", R8A774C0_CLK_S1D1, CLK_S1, 1, 1),
94 DEF_FIXED("s1d2", R8A774C0_CLK_S1D2, CLK_S1, 2, 1),
95 DEF_FIXED("s1d4", R8A774C0_CLK_S1D4, CLK_S1, 4, 1),
96 DEF_FIXED("s2d1", R8A774C0_CLK_S2D1, CLK_S2, 1, 1),
97 DEF_FIXED("s2d2", R8A774C0_CLK_S2D2, CLK_S2, 2, 1),
98 DEF_FIXED("s2d4", R8A774C0_CLK_S2D4, CLK_S2, 4, 1),
99 DEF_FIXED("s3d1", R8A774C0_CLK_S3D1, CLK_S3, 1, 1),
100 DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
101 DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
102
103 DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074),
104 DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078),
105 DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c),
106
107 DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1),
108 DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1),
109 DEF_FIXED("cpex", R8A774C0_CLK_CPEX, CLK_EXTAL, 4, 1),
110
111 DEF_DIV6_RO("osc", R8A774C0_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
112
113 DEF_GEN3_PE("s0d6c", R8A774C0_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
114 DEF_GEN3_PE("s3d1c", R8A774C0_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
115 DEF_GEN3_PE("s3d2c", R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
116 DEF_GEN3_PE("s3d4c", R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
117
118 DEF_DIV6P1("canfd", R8A774C0_CLK_CANFD, CLK_PLL0D6, 0x244),
119 DEF_DIV6P1("csi0", R8A774C0_CLK_CSI0, CLK_PLL1D2, 0x00c),
120 DEF_DIV6P1("mso", R8A774C0_CLK_MSO, CLK_PLL1D2, 0x014),
121
122 DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
123 };
124
125 static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
126 DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C),
127 DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C),
128 DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C),
129 DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C),
130 DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
131 DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
132 DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
133 DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
134 DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C),
135 DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C),
136 DEF_MOD("msiof3", 208, R8A774C0_CLK_MSO),
137 DEF_MOD("msiof2", 209, R8A774C0_CLK_MSO),
138 DEF_MOD("msiof1", 210, R8A774C0_CLK_MSO),
139 DEF_MOD("msiof0", 211, R8A774C0_CLK_MSO),
140 DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1),
141 DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1),
142 DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1),
143
144 DEF_MOD("cmt3", 300, R8A774C0_CLK_R),
145 DEF_MOD("cmt2", 301, R8A774C0_CLK_R),
146 DEF_MOD("cmt1", 302, R8A774C0_CLK_R),
147 DEF_MOD("cmt0", 303, R8A774C0_CLK_R),
148 DEF_MOD("scif2", 310, R8A774C0_CLK_S3D4C),
149 DEF_MOD("sdif3", 311, R8A774C0_CLK_SD3),
150 DEF_MOD("sdif1", 313, R8A774C0_CLK_SD1),
151 DEF_MOD("sdif0", 314, R8A774C0_CLK_SD0),
152 DEF_MOD("pcie0", 319, R8A774C0_CLK_S3D1),
153 DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1),
154 DEF_MOD("usb-dmac0", 330, R8A774C0_CLK_S3D1),
155 DEF_MOD("usb-dmac1", 331, R8A774C0_CLK_S3D1),
156
157 DEF_MOD("rwdt", 402, R8A774C0_CLK_R),
158 DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
159 DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
160
161 DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2),
162 DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
163 DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
164 DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
165 DEF_MOD("hscif1", 519, R8A774C0_CLK_S3D1C),
166 DEF_MOD("hscif0", 520, R8A774C0_CLK_S3D1C),
167 DEF_MOD("thermal", 522, R8A774C0_CLK_CP),
168 DEF_MOD("pwm", 523, R8A774C0_CLK_S3D4C),
169
170 DEF_MOD("fcpvd1", 602, R8A774C0_CLK_S1D2),
171 DEF_MOD("fcpvd0", 603, R8A774C0_CLK_S1D2),
172 DEF_MOD("fcpvb0", 607, R8A774C0_CLK_S0D1),
173 DEF_MOD("fcpvi0", 611, R8A774C0_CLK_S0D1),
174 DEF_MOD("fcpf0", 615, R8A774C0_CLK_S0D1),
175 DEF_MOD("fcpcs", 619, R8A774C0_CLK_S0D1),
176 DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2),
177 DEF_MOD("vspd0", 623, R8A774C0_CLK_S1D2),
178 DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
179 DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
180
181 DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
182 DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D2),
183 DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
184 DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
185 DEF_MOD("du0", 724, R8A774C0_CLK_S1D1),
186 DEF_MOD("lvds", 727, R8A774C0_CLK_S2D1),
187
188 DEF_MOD("vin5", 806, R8A774C0_CLK_S1D2),
189 DEF_MOD("vin4", 807, R8A774C0_CLK_S1D2),
190 DEF_MOD("etheravb", 812, R8A774C0_CLK_S3D2),
191
192 DEF_MOD("gpio6", 906, R8A774C0_CLK_S3D4),
193 DEF_MOD("gpio5", 907, R8A774C0_CLK_S3D4),
194 DEF_MOD("gpio4", 908, R8A774C0_CLK_S3D4),
195 DEF_MOD("gpio3", 909, R8A774C0_CLK_S3D4),
196 DEF_MOD("gpio2", 910, R8A774C0_CLK_S3D4),
197 DEF_MOD("gpio1", 911, R8A774C0_CLK_S3D4),
198 DEF_MOD("gpio0", 912, R8A774C0_CLK_S3D4),
199 DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2),
200 DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
201 DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
202 DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
203 DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
204 DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
205 DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
206 DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
207 DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2),
208 DEF_MOD("i2c1", 930, R8A774C0_CLK_S3D2),
209 DEF_MOD("i2c0", 931, R8A774C0_CLK_S3D2),
210
211 DEF_MOD("i2c7", 1003, R8A774C0_CLK_S3D2),
212 DEF_MOD("ssi-all", 1005, R8A774C0_CLK_S3D4),
213 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
214 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
215 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
216 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
217 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
218 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
219 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
220 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
221 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
222 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
223 DEF_MOD("scu-all", 1017, R8A774C0_CLK_S3D4),
224 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
225 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
226 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
228 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
229 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
230 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
231 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
232 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
233 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
234 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
235 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
236 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
237 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
238 };
239
240 static const unsigned int r8a774c0_crit_mod_clks[] __initconst = {
241 MOD_CLK_ID(408),
242 };
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253
254 #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
255
256 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
257
258 { 1, 100, 3, 100, 3, },
259 { 1, 100, 3, 58, 3, },
260 };
261
262 static int __init r8a774c0_cpg_mssr_init(struct device *dev)
263 {
264 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
265 u32 cpg_mode;
266 int error;
267
268 error = rcar_rst_read_mode_pins(&cpg_mode);
269 if (error)
270 return error;
271
272 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
273
274 return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
275 }
276
277 const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {
278
279 .core_clks = r8a774c0_core_clks,
280 .num_core_clks = ARRAY_SIZE(r8a774c0_core_clks),
281 .last_dt_core_clk = LAST_DT_CORE_CLK,
282 .num_total_core_clks = MOD_CLK_BASE,
283
284
285 .mod_clks = r8a774c0_mod_clks,
286 .num_mod_clks = ARRAY_SIZE(r8a774c0_mod_clks),
287 .num_hw_mod_clks = 12 * 32,
288
289
290 .crit_mod_clks = r8a774c0_crit_mod_clks,
291 .num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks),
292
293
294 .init = r8a774c0_cpg_mssr_init,
295 .cpg_clk_register = rcar_gen3_cpg_clk_register,
296 };