This source file includes following definitions.
- r8a77980_cpg_mssr_init
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13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/soc/renesas/rcar-rst.h>
17 #include <linux/sys_soc.h>
18
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
20
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
23
24 enum clk_ids {
25
26 LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
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28
29 CLK_EXTAL,
30 CLK_EXTALR,
31
32
33 CLK_MAIN,
34 CLK_PLL1,
35 CLK_PLL2,
36 CLK_PLL3,
37 CLK_PLL1_DIV2,
38 CLK_PLL1_DIV4,
39 CLK_S0,
40 CLK_S1,
41 CLK_S2,
42 CLK_S3,
43 CLK_SDSRC,
44 CLK_RPCSRC,
45 CLK_OCO,
46
47
48 MOD_CLK_BASE
49 };
50
51 static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
52
53 DEF_INPUT("extal", CLK_EXTAL),
54 DEF_INPUT("extalr", CLK_EXTALR),
55
56
57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61
62 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
63 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
64 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
65 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
66 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
67 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
68 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
69 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
70 DEF_RATE(".oco", CLK_OCO, 32768),
71
72 DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
73 CLK_RPCSRC),
74 DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
75 R8A77980_CLK_RPC),
76
77
78 DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
79 DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
80 DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
81 DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
82 DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
83 DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
84 DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
85 DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
86 DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
87 DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
88 DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
89 DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
90 DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
91 DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
92 DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
93 DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
94 DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
95 DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
96 DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
97 DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
98
99 DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
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101 DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
102 DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
103 DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
104
105 DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
106 DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
107 DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
108
109 DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
110 DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
111 };
112
113 static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
114 DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
115 DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
116 DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
117 DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
118 DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
119 DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
120 DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
121 DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
122 DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
123 DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
124 DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
125 DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
126 DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
127 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
128 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
129 DEF_MOD("cmt3", 300, R8A77980_CLK_R),
130 DEF_MOD("cmt2", 301, R8A77980_CLK_R),
131 DEF_MOD("cmt1", 302, R8A77980_CLK_R),
132 DEF_MOD("cmt0", 303, R8A77980_CLK_R),
133 DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
134 DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
135 DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
136 DEF_MOD("rwdt", 402, R8A77980_CLK_R),
137 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
138 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
139 DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
140 DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
141 DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
142 DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
143 DEF_MOD("imp4", 521, R8A77980_CLK_S1D1),
144 DEF_MOD("thermal", 522, R8A77980_CLK_CP),
145 DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
146 DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
147 DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
148 DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
149 DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
150 DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
151 DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
152 DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
153 DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
154 DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
155 DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
156 DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
157 DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
158 DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
159 DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
160 DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
161 DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
162 DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
163 DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
164 DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
165 DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
166 DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
167 DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
168 DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
169 DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
170 DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
171 DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
172 DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
173 DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
174 DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
175 DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
176 DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
177 DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
178 DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
179 DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
180 };
181
182 static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
183 MOD_CLK_ID(408),
184 };
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200 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
201 (((md) & BIT(13)) >> 13))
202
203 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
204
205 { 1, 192, 1, 192, 1, 16, },
206 { 1, 160, 1, 160, 1, 19, },
207 { 1, 118, 1, 118, 1, 26, },
208 { 2, 192, 1, 192, 1, 32, },
209 };
210
211 static int __init r8a77980_cpg_mssr_init(struct device *dev)
212 {
213 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
214 u32 cpg_mode;
215 int error;
216
217 error = rcar_rst_read_mode_pins(&cpg_mode);
218 if (error)
219 return error;
220
221 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
222
223 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
224 }
225
226 const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
227
228 .core_clks = r8a77980_core_clks,
229 .num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
230 .last_dt_core_clk = LAST_DT_CORE_CLK,
231 .num_total_core_clks = MOD_CLK_BASE,
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233
234 .mod_clks = r8a77980_mod_clks,
235 .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
236 .num_hw_mod_clks = 12 * 32,
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239 .crit_mod_clks = r8a77980_crit_mod_clks,
240 .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
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243 .init = r8a77980_cpg_mssr_init,
244 .cpg_clk_register = rcar_gen3_cpg_clk_register,
245 };