This source file includes following definitions.
- clkc_readl
- clkc_writel
- pll_clk_recalc_rate
- dto_clk_is_enabled
- dto_clk_enable
- dto_clk_disable
- dto_clk_recalc_rate
- dto_clk_round_rate
- dto_clk_set_rate
- dto_clk_get_parent
- dto_clk_set_parent
- ARRAY_SIZE
- unit_clk_enable
- unit_clk_disable
- atlas7_unit_clk_register
- atlas7_reset_module
- atlas7_clk_init
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8 #include <linux/bitops.h>
9 #include <linux/io.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/of_address.h>
13 #include <linux/reset-controller.h>
14 #include <linux/slab.h>
15
16 #define SIRFSOC_CLKC_MEMPLL_AB_FREQ 0x0000
17 #define SIRFSOC_CLKC_MEMPLL_AB_SSC 0x0004
18 #define SIRFSOC_CLKC_MEMPLL_AB_CTRL0 0x0008
19 #define SIRFSOC_CLKC_MEMPLL_AB_CTRL1 0x000c
20 #define SIRFSOC_CLKC_MEMPLL_AB_STATUS 0x0010
21 #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_ADDR 0x0014
22 #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_DATA 0x0018
23
24 #define SIRFSOC_CLKC_CPUPLL_AB_FREQ 0x001c
25 #define SIRFSOC_CLKC_CPUPLL_AB_SSC 0x0020
26 #define SIRFSOC_CLKC_CPUPLL_AB_CTRL0 0x0024
27 #define SIRFSOC_CLKC_CPUPLL_AB_CTRL1 0x0028
28 #define SIRFSOC_CLKC_CPUPLL_AB_STATUS 0x002c
29
30 #define SIRFSOC_CLKC_SYS0PLL_AB_FREQ 0x0030
31 #define SIRFSOC_CLKC_SYS0PLL_AB_SSC 0x0034
32 #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL0 0x0038
33 #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL1 0x003c
34 #define SIRFSOC_CLKC_SYS0PLL_AB_STATUS 0x0040
35
36 #define SIRFSOC_CLKC_SYS1PLL_AB_FREQ 0x0044
37 #define SIRFSOC_CLKC_SYS1PLL_AB_SSC 0x0048
38 #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL0 0x004c
39 #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL1 0x0050
40 #define SIRFSOC_CLKC_SYS1PLL_AB_STATUS 0x0054
41
42 #define SIRFSOC_CLKC_SYS2PLL_AB_FREQ 0x0058
43 #define SIRFSOC_CLKC_SYS2PLL_AB_SSC 0x005c
44 #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL0 0x0060
45 #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL1 0x0064
46 #define SIRFSOC_CLKC_SYS2PLL_AB_STATUS 0x0068
47
48 #define SIRFSOC_CLKC_SYS3PLL_AB_FREQ 0x006c
49 #define SIRFSOC_CLKC_SYS3PLL_AB_SSC 0x0070
50 #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL0 0x0074
51 #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL1 0x0078
52 #define SIRFSOC_CLKC_SYS3PLL_AB_STATUS 0x007c
53
54 #define SIRFSOC_ABPLL_CTRL0_SSEN 0x00001000
55 #define SIRFSOC_ABPLL_CTRL0_BYPASS 0x00000010
56 #define SIRFSOC_ABPLL_CTRL0_RESET 0x00000001
57
58 #define SIRFSOC_CLKC_AUDIO_DTO_INC 0x0088
59 #define SIRFSOC_CLKC_DISP0_DTO_INC 0x008c
60 #define SIRFSOC_CLKC_DISP1_DTO_INC 0x0090
61
62 #define SIRFSOC_CLKC_AUDIO_DTO_SRC 0x0094
63 #define SIRFSOC_CLKC_AUDIO_DTO_ENA 0x0098
64 #define SIRFSOC_CLKC_AUDIO_DTO_DROFF 0x009c
65
66 #define SIRFSOC_CLKC_DISP0_DTO_SRC 0x00a0
67 #define SIRFSOC_CLKC_DISP0_DTO_ENA 0x00a4
68 #define SIRFSOC_CLKC_DISP0_DTO_DROFF 0x00a8
69
70 #define SIRFSOC_CLKC_DISP1_DTO_SRC 0x00ac
71 #define SIRFSOC_CLKC_DISP1_DTO_ENA 0x00b0
72 #define SIRFSOC_CLKC_DISP1_DTO_DROFF 0x00b4
73
74 #define SIRFSOC_CLKC_I2S_CLK_SEL 0x00b8
75 #define SIRFSOC_CLKC_I2S_SEL_STAT 0x00bc
76
77 #define SIRFSOC_CLKC_USBPHY_CLKDIV_CFG 0x00c0
78 #define SIRFSOC_CLKC_USBPHY_CLKDIV_ENA 0x00c4
79 #define SIRFSOC_CLKC_USBPHY_CLK_SEL 0x00c8
80 #define SIRFSOC_CLKC_USBPHY_CLK_SEL_STAT 0x00cc
81
82 #define SIRFSOC_CLKC_BTSS_CLKDIV_CFG 0x00d0
83 #define SIRFSOC_CLKC_BTSS_CLKDIV_ENA 0x00d4
84 #define SIRFSOC_CLKC_BTSS_CLK_SEL 0x00d8
85 #define SIRFSOC_CLKC_BTSS_CLK_SEL_STAT 0x00dc
86
87 #define SIRFSOC_CLKC_RGMII_CLKDIV_CFG 0x00e0
88 #define SIRFSOC_CLKC_RGMII_CLKDIV_ENA 0x00e4
89 #define SIRFSOC_CLKC_RGMII_CLK_SEL 0x00e8
90 #define SIRFSOC_CLKC_RGMII_CLK_SEL_STAT 0x00ec
91
92 #define SIRFSOC_CLKC_CPU_CLKDIV_CFG 0x00f0
93 #define SIRFSOC_CLKC_CPU_CLKDIV_ENA 0x00f4
94 #define SIRFSOC_CLKC_CPU_CLK_SEL 0x00f8
95 #define SIRFSOC_CLKC_CPU_CLK_SEL_STAT 0x00fc
96
97 #define SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG 0x0100
98 #define SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA 0x0104
99 #define SIRFSOC_CLKC_SDPHY01_CLK_SEL 0x0108
100 #define SIRFSOC_CLKC_SDPHY01_CLK_SEL_STAT 0x010c
101
102 #define SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG 0x0110
103 #define SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA 0x0114
104 #define SIRFSOC_CLKC_SDPHY23_CLK_SEL 0x0118
105 #define SIRFSOC_CLKC_SDPHY23_CLK_SEL_STAT 0x011c
106
107 #define SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG 0x0120
108 #define SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA 0x0124
109 #define SIRFSOC_CLKC_SDPHY45_CLK_SEL 0x0128
110 #define SIRFSOC_CLKC_SDPHY45_CLK_SEL_STAT 0x012c
111
112 #define SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG 0x0130
113 #define SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA 0x0134
114 #define SIRFSOC_CLKC_SDPHY67_CLK_SEL 0x0138
115 #define SIRFSOC_CLKC_SDPHY67_CLK_SEL_STAT 0x013c
116
117 #define SIRFSOC_CLKC_CAN_CLKDIV_CFG 0x0140
118 #define SIRFSOC_CLKC_CAN_CLKDIV_ENA 0x0144
119 #define SIRFSOC_CLKC_CAN_CLK_SEL 0x0148
120 #define SIRFSOC_CLKC_CAN_CLK_SEL_STAT 0x014c
121
122 #define SIRFSOC_CLKC_DEINT_CLKDIV_CFG 0x0150
123 #define SIRFSOC_CLKC_DEINT_CLKDIV_ENA 0x0154
124 #define SIRFSOC_CLKC_DEINT_CLK_SEL 0x0158
125 #define SIRFSOC_CLKC_DEINT_CLK_SEL_STAT 0x015c
126
127 #define SIRFSOC_CLKC_NAND_CLKDIV_CFG 0x0160
128 #define SIRFSOC_CLKC_NAND_CLKDIV_ENA 0x0164
129 #define SIRFSOC_CLKC_NAND_CLK_SEL 0x0168
130 #define SIRFSOC_CLKC_NAND_CLK_SEL_STAT 0x016c
131
132 #define SIRFSOC_CLKC_DISP0_CLKDIV_CFG 0x0170
133 #define SIRFSOC_CLKC_DISP0_CLKDIV_ENA 0x0174
134 #define SIRFSOC_CLKC_DISP0_CLK_SEL 0x0178
135 #define SIRFSOC_CLKC_DISP0_CLK_SEL_STAT 0x017c
136
137 #define SIRFSOC_CLKC_DISP1_CLKDIV_CFG 0x0180
138 #define SIRFSOC_CLKC_DISP1_CLKDIV_ENA 0x0184
139 #define SIRFSOC_CLKC_DISP1_CLK_SEL 0x0188
140 #define SIRFSOC_CLKC_DISP1_CLK_SEL_STAT 0x018c
141
142 #define SIRFSOC_CLKC_GPU_CLKDIV_CFG 0x0190
143 #define SIRFSOC_CLKC_GPU_CLKDIV_ENA 0x0194
144 #define SIRFSOC_CLKC_GPU_CLK_SEL 0x0198
145 #define SIRFSOC_CLKC_GPU_CLK_SEL_STAT 0x019c
146
147 #define SIRFSOC_CLKC_GNSS_CLKDIV_CFG 0x01a0
148 #define SIRFSOC_CLKC_GNSS_CLKDIV_ENA 0x01a4
149 #define SIRFSOC_CLKC_GNSS_CLK_SEL 0x01a8
150 #define SIRFSOC_CLKC_GNSS_CLK_SEL_STAT 0x01ac
151
152 #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG0 0x01b0
153 #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG1 0x01b4
154 #define SIRFSOC_CLKC_SHARED_DIVIDER_ENA 0x01b8
155
156 #define SIRFSOC_CLKC_SYS_CLK_SEL 0x01bc
157 #define SIRFSOC_CLKC_SYS_CLK_SEL_STAT 0x01c0
158 #define SIRFSOC_CLKC_IO_CLK_SEL 0x01c4
159 #define SIRFSOC_CLKC_IO_CLK_SEL_STAT 0x01c8
160 #define SIRFSOC_CLKC_G2D_CLK_SEL 0x01cc
161 #define SIRFSOC_CLKC_G2D_CLK_SEL_STAT 0x01d0
162 #define SIRFSOC_CLKC_JPENC_CLK_SEL 0x01d4
163 #define SIRFSOC_CLKC_JPENC_CLK_SEL_STAT 0x01d8
164 #define SIRFSOC_CLKC_VDEC_CLK_SEL 0x01dc
165 #define SIRFSOC_CLKC_VDEC_CLK_SEL_STAT 0x01e0
166 #define SIRFSOC_CLKC_GMAC_CLK_SEL 0x01e4
167 #define SIRFSOC_CLKC_GMAC_CLK_SEL_STAT 0x01e8
168 #define SIRFSOC_CLKC_USB_CLK_SEL 0x01ec
169 #define SIRFSOC_CLKC_USB_CLK_SEL_STAT 0x01f0
170 #define SIRFSOC_CLKC_KAS_CLK_SEL 0x01f4
171 #define SIRFSOC_CLKC_KAS_CLK_SEL_STAT 0x01f8
172 #define SIRFSOC_CLKC_SEC_CLK_SEL 0x01fc
173 #define SIRFSOC_CLKC_SEC_CLK_SEL_STAT 0x0200
174 #define SIRFSOC_CLKC_SDR_CLK_SEL 0x0204
175 #define SIRFSOC_CLKC_SDR_CLK_SEL_STAT 0x0208
176 #define SIRFSOC_CLKC_VIP_CLK_SEL 0x020c
177 #define SIRFSOC_CLKC_VIP_CLK_SEL_STAT 0x0210
178 #define SIRFSOC_CLKC_NOCD_CLK_SEL 0x0214
179 #define SIRFSOC_CLKC_NOCD_CLK_SEL_STAT 0x0218
180 #define SIRFSOC_CLKC_NOCR_CLK_SEL 0x021c
181 #define SIRFSOC_CLKC_NOCR_CLK_SEL_STAT 0x0220
182 #define SIRFSOC_CLKC_TPIU_CLK_SEL 0x0224
183 #define SIRFSOC_CLKC_TPIU_CLK_SEL_STAT 0x0228
184
185 #define SIRFSOC_CLKC_ROOT_CLK_EN0_SET 0x022c
186 #define SIRFSOC_CLKC_ROOT_CLK_EN0_CLR 0x0230
187 #define SIRFSOC_CLKC_ROOT_CLK_EN0_STAT 0x0234
188 #define SIRFSOC_CLKC_ROOT_CLK_EN1_SET 0x0238
189 #define SIRFSOC_CLKC_ROOT_CLK_EN1_CLR 0x023c
190 #define SIRFSOC_CLKC_ROOT_CLK_EN1_STAT 0x0240
191
192 #define SIRFSOC_CLKC_LEAF_CLK_EN0_SET 0x0244
193 #define SIRFSOC_CLKC_LEAF_CLK_EN0_CLR 0x0248
194 #define SIRFSOC_CLKC_LEAF_CLK_EN0_STAT 0x024c
195
196 #define SIRFSOC_CLKC_RSTC_A7_SW_RST 0x0308
197
198 #define SIRFSOC_CLKC_LEAF_CLK_EN1_SET 0x04a0
199 #define SIRFSOC_CLKC_LEAF_CLK_EN2_SET 0x04b8
200 #define SIRFSOC_CLKC_LEAF_CLK_EN3_SET 0x04d0
201 #define SIRFSOC_CLKC_LEAF_CLK_EN4_SET 0x04e8
202 #define SIRFSOC_CLKC_LEAF_CLK_EN5_SET 0x0500
203 #define SIRFSOC_CLKC_LEAF_CLK_EN6_SET 0x0518
204 #define SIRFSOC_CLKC_LEAF_CLK_EN7_SET 0x0530
205 #define SIRFSOC_CLKC_LEAF_CLK_EN8_SET 0x0548
206
207 #define SIRFSOC_NOC_CLK_IDLEREQ_SET 0x02D0
208 #define SIRFSOC_NOC_CLK_IDLEREQ_CLR 0x02D4
209 #define SIRFSOC_NOC_CLK_SLVRDY_SET 0x02E8
210 #define SIRFSOC_NOC_CLK_SLVRDY_CLR 0x02EC
211 #define SIRFSOC_NOC_CLK_IDLE_STATUS 0x02F4
212
213 struct clk_pll {
214 struct clk_hw hw;
215 u16 regofs;
216 };
217 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
218
219 struct clk_dto {
220 struct clk_hw hw;
221 u16 inc_offset;
222 u16 src_offset;
223 };
224 #define to_dtoclk(_hw) container_of(_hw, struct clk_dto, hw)
225
226 enum clk_unit_type {
227 CLK_UNIT_NOC_OTHER,
228 CLK_UNIT_NOC_CLOCK,
229 CLK_UNIT_NOC_SOCKET,
230 };
231
232 struct clk_unit {
233 struct clk_hw hw;
234 u16 regofs;
235 u16 bit;
236 u32 type;
237 u8 idle_bit;
238 spinlock_t *lock;
239 };
240 #define to_unitclk(_hw) container_of(_hw, struct clk_unit, hw)
241
242 struct atlas7_div_init_data {
243 const char *div_name;
244 const char *parent_name;
245 const char *gate_name;
246 unsigned long flags;
247 u8 divider_flags;
248 u8 gate_flags;
249 u32 div_offset;
250 u8 shift;
251 u8 width;
252 u32 gate_offset;
253 u8 gate_bit;
254 spinlock_t *lock;
255 };
256
257 struct atlas7_mux_init_data {
258 const char *mux_name;
259 const char * const *parent_names;
260 u8 parent_num;
261 unsigned long flags;
262 u8 mux_flags;
263 u32 mux_offset;
264 u8 shift;
265 u8 width;
266 };
267
268 struct atlas7_unit_init_data {
269 u32 index;
270 const char *unit_name;
271 const char *parent_name;
272 unsigned long flags;
273 u32 regofs;
274 u8 bit;
275 u32 type;
276 u8 idle_bit;
277 spinlock_t *lock;
278 };
279
280 struct atlas7_reset_desc {
281 const char *name;
282 u32 clk_ofs;
283 u8 clk_bit;
284 u32 rst_ofs;
285 u8 rst_bit;
286 spinlock_t *lock;
287 };
288
289 static void __iomem *sirfsoc_clk_vbase;
290 static struct clk_onecell_data clk_data;
291
292 static const struct clk_div_table pll_div_table[] = {
293 { .val = 0, .div = 1 },
294 { .val = 1, .div = 2 },
295 { .val = 2, .div = 4 },
296 { .val = 3, .div = 8 },
297 { .val = 4, .div = 16 },
298 { .val = 5, .div = 32 },
299 };
300
301 static DEFINE_SPINLOCK(cpupll_ctrl1_lock);
302 static DEFINE_SPINLOCK(mempll_ctrl1_lock);
303 static DEFINE_SPINLOCK(sys0pll_ctrl1_lock);
304 static DEFINE_SPINLOCK(sys1pll_ctrl1_lock);
305 static DEFINE_SPINLOCK(sys2pll_ctrl1_lock);
306 static DEFINE_SPINLOCK(sys3pll_ctrl1_lock);
307 static DEFINE_SPINLOCK(usbphy_div_lock);
308 static DEFINE_SPINLOCK(btss_div_lock);
309 static DEFINE_SPINLOCK(rgmii_div_lock);
310 static DEFINE_SPINLOCK(cpu_div_lock);
311 static DEFINE_SPINLOCK(sdphy01_div_lock);
312 static DEFINE_SPINLOCK(sdphy23_div_lock);
313 static DEFINE_SPINLOCK(sdphy45_div_lock);
314 static DEFINE_SPINLOCK(sdphy67_div_lock);
315 static DEFINE_SPINLOCK(can_div_lock);
316 static DEFINE_SPINLOCK(deint_div_lock);
317 static DEFINE_SPINLOCK(nand_div_lock);
318 static DEFINE_SPINLOCK(disp0_div_lock);
319 static DEFINE_SPINLOCK(disp1_div_lock);
320 static DEFINE_SPINLOCK(gpu_div_lock);
321 static DEFINE_SPINLOCK(gnss_div_lock);
322
323 static DEFINE_SPINLOCK(share_div_lock);
324 static DEFINE_SPINLOCK(root0_gate_lock);
325 static DEFINE_SPINLOCK(root1_gate_lock);
326 static DEFINE_SPINLOCK(leaf0_gate_lock);
327 static DEFINE_SPINLOCK(leaf1_gate_lock);
328 static DEFINE_SPINLOCK(leaf2_gate_lock);
329 static DEFINE_SPINLOCK(leaf3_gate_lock);
330 static DEFINE_SPINLOCK(leaf4_gate_lock);
331 static DEFINE_SPINLOCK(leaf5_gate_lock);
332 static DEFINE_SPINLOCK(leaf6_gate_lock);
333 static DEFINE_SPINLOCK(leaf7_gate_lock);
334 static DEFINE_SPINLOCK(leaf8_gate_lock);
335
336 static inline unsigned long clkc_readl(unsigned reg)
337 {
338 return readl(sirfsoc_clk_vbase + reg);
339 }
340
341 static inline void clkc_writel(u32 val, unsigned reg)
342 {
343 writel(val, sirfsoc_clk_vbase + reg);
344 }
345
346
347
348
349
350
351
352 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
353 unsigned long parent_rate)
354 {
355 unsigned long fin = parent_rate;
356 struct clk_pll *clk = to_pllclk(hw);
357 u64 rate;
358 u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 -
359 SIRFSOC_CLKC_MEMPLL_AB_FREQ);
360 u32 regfreq = clkc_readl(clk->regofs);
361 u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC -
362 SIRFSOC_CLKC_MEMPLL_AB_FREQ);
363 u32 nr = (regfreq >> 16 & (BIT(3) - 1)) + 1;
364 u32 nf = (regfreq & (BIT(9) - 1)) + 1;
365 u32 ssdiv = regssc >> 8 & (BIT(12) - 1);
366 u32 ssdepth = regssc >> 20 & (BIT(2) - 1);
367 u32 ssmod = regssc & (BIT(8) - 1);
368
369 if (regctrl0 & SIRFSOC_ABPLL_CTRL0_BYPASS)
370 return fin;
371
372 if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) {
373 rate = fin;
374 rate *= 1 << 24;
375 do_div(rate, nr);
376 do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth)
377 + (ssmod << ssdepth)));
378 } else {
379 rate = 2 * fin;
380 rate *= nf;
381 do_div(rate, nr);
382 }
383 return rate;
384 }
385
386 static const struct clk_ops ab_pll_ops = {
387 .recalc_rate = pll_clk_recalc_rate,
388 };
389
390 static const char * const pll_clk_parents[] = {
391 "xin",
392 };
393
394 static const struct clk_init_data clk_cpupll_init = {
395 .name = "cpupll_vco",
396 .ops = &ab_pll_ops,
397 .parent_names = pll_clk_parents,
398 .num_parents = ARRAY_SIZE(pll_clk_parents),
399 };
400
401 static struct clk_pll clk_cpupll = {
402 .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ,
403 .hw = {
404 .init = &clk_cpupll_init,
405 },
406 };
407
408 static const struct clk_init_data clk_mempll_init = {
409 .name = "mempll_vco",
410 .ops = &ab_pll_ops,
411 .parent_names = pll_clk_parents,
412 .num_parents = ARRAY_SIZE(pll_clk_parents),
413 };
414
415 static struct clk_pll clk_mempll = {
416 .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ,
417 .hw = {
418 .init = &clk_mempll_init,
419 },
420 };
421
422 static const struct clk_init_data clk_sys0pll_init = {
423 .name = "sys0pll_vco",
424 .ops = &ab_pll_ops,
425 .parent_names = pll_clk_parents,
426 .num_parents = ARRAY_SIZE(pll_clk_parents),
427 };
428
429 static struct clk_pll clk_sys0pll = {
430 .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ,
431 .hw = {
432 .init = &clk_sys0pll_init,
433 },
434 };
435
436 static const struct clk_init_data clk_sys1pll_init = {
437 .name = "sys1pll_vco",
438 .ops = &ab_pll_ops,
439 .parent_names = pll_clk_parents,
440 .num_parents = ARRAY_SIZE(pll_clk_parents),
441 };
442
443 static struct clk_pll clk_sys1pll = {
444 .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ,
445 .hw = {
446 .init = &clk_sys1pll_init,
447 },
448 };
449
450 static const struct clk_init_data clk_sys2pll_init = {
451 .name = "sys2pll_vco",
452 .ops = &ab_pll_ops,
453 .parent_names = pll_clk_parents,
454 .num_parents = ARRAY_SIZE(pll_clk_parents),
455 };
456
457 static struct clk_pll clk_sys2pll = {
458 .regofs = SIRFSOC_CLKC_SYS2PLL_AB_FREQ,
459 .hw = {
460 .init = &clk_sys2pll_init,
461 },
462 };
463
464 static const struct clk_init_data clk_sys3pll_init = {
465 .name = "sys3pll_vco",
466 .ops = &ab_pll_ops,
467 .parent_names = pll_clk_parents,
468 .num_parents = ARRAY_SIZE(pll_clk_parents),
469 };
470
471 static struct clk_pll clk_sys3pll = {
472 .regofs = SIRFSOC_CLKC_SYS3PLL_AB_FREQ,
473 .hw = {
474 .init = &clk_sys3pll_init,
475 },
476 };
477
478
479
480
481
482
483 #define DTO_RESL_DOUBLE (1ULL << 29)
484 #define DTO_RESL_NORMAL (1ULL << 28)
485
486 static int dto_clk_is_enabled(struct clk_hw *hw)
487 {
488 struct clk_dto *clk = to_dtoclk(hw);
489 int reg;
490
491 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
492
493 return !!(clkc_readl(reg) & BIT(0));
494 }
495
496 static int dto_clk_enable(struct clk_hw *hw)
497 {
498 u32 val, reg;
499 struct clk_dto *clk = to_dtoclk(hw);
500
501 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
502
503 val = clkc_readl(reg) | BIT(0);
504 clkc_writel(val, reg);
505 return 0;
506 }
507
508 static void dto_clk_disable(struct clk_hw *hw)
509 {
510 u32 val, reg;
511 struct clk_dto *clk = to_dtoclk(hw);
512
513 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
514
515 val = clkc_readl(reg) & ~BIT(0);
516 clkc_writel(val, reg);
517 }
518
519 static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
520 unsigned long parent_rate)
521 {
522 u64 rate = parent_rate;
523 struct clk_dto *clk = to_dtoclk(hw);
524 u32 finc = clkc_readl(clk->inc_offset);
525 u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
526
527 rate *= finc;
528 if (droff & BIT(0))
529
530 do_div(rate, DTO_RESL_NORMAL);
531 else
532 do_div(rate, DTO_RESL_DOUBLE);
533
534 return rate;
535 }
536
537 static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
538 unsigned long *parent_rate)
539 {
540 u64 dividend = rate * DTO_RESL_DOUBLE;
541
542 do_div(dividend, *parent_rate);
543 dividend *= *parent_rate;
544 do_div(dividend, DTO_RESL_DOUBLE);
545
546 return dividend;
547 }
548
549 static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate,
550 unsigned long parent_rate)
551 {
552 u64 dividend = rate * DTO_RESL_DOUBLE;
553 struct clk_dto *clk = to_dtoclk(hw);
554
555 do_div(dividend, parent_rate);
556 clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
557 clkc_writel(dividend, clk->inc_offset);
558
559 return 0;
560 }
561
562 static u8 dto_clk_get_parent(struct clk_hw *hw)
563 {
564 struct clk_dto *clk = to_dtoclk(hw);
565
566 return clkc_readl(clk->src_offset);
567 }
568
569
570
571
572 static int dto_clk_set_parent(struct clk_hw *hw, u8 index)
573 {
574 struct clk_dto *clk = to_dtoclk(hw);
575
576 clkc_writel(index, clk->src_offset);
577 return 0;
578 }
579
580 static const struct clk_ops dto_ops = {
581 .is_enabled = dto_clk_is_enabled,
582 .enable = dto_clk_enable,
583 .disable = dto_clk_disable,
584 .recalc_rate = dto_clk_recalc_rate,
585 .round_rate = dto_clk_round_rate,
586 .set_rate = dto_clk_set_rate,
587 .get_parent = dto_clk_get_parent,
588 .set_parent = dto_clk_set_parent,
589 };
590
591
592 static const char * const audiodto_clk_parents[] = {
593 "sys0pll_clk1",
594 "sys1pll_clk1",
595 "sys3pll_clk1",
596 };
597
598 static const struct clk_init_data clk_audiodto_init = {
599 .name = "audio_dto",
600 .ops = &dto_ops,
601 .parent_names = audiodto_clk_parents,
602 .num_parents = ARRAY_SIZE(audiodto_clk_parents),
603 };
604
605 static struct clk_dto clk_audio_dto = {
606 .inc_offset = SIRFSOC_CLKC_AUDIO_DTO_INC,
607 .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC,
608 .hw = {
609 .init = &clk_audiodto_init,
610 },
611 };
612
613 static const char * const disp0dto_clk_parents[] = {
614 "sys0pll_clk1",
615 "sys1pll_clk1",
616 "sys3pll_clk1",
617 };
618
619 static const struct clk_init_data clk_disp0dto_init = {
620 .name = "disp0_dto",
621 .ops = &dto_ops,
622 .parent_names = disp0dto_clk_parents,
623 .num_parents = ARRAY_SIZE(disp0dto_clk_parents),
624 };
625
626 static struct clk_dto clk_disp0_dto = {
627 .inc_offset = SIRFSOC_CLKC_DISP0_DTO_INC,
628 .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC,
629 .hw = {
630 .init = &clk_disp0dto_init,
631 },
632 };
633
634 static const char * const disp1dto_clk_parents[] = {
635 "sys0pll_clk1",
636 "sys1pll_clk1",
637 "sys3pll_clk1",
638 };
639
640 static const struct clk_init_data clk_disp1dto_init = {
641 .name = "disp1_dto",
642 .ops = &dto_ops,
643 .parent_names = disp1dto_clk_parents,
644 .num_parents = ARRAY_SIZE(disp1dto_clk_parents),
645 };
646
647 static struct clk_dto clk_disp1_dto = {
648 .inc_offset = SIRFSOC_CLKC_DISP1_DTO_INC,
649 .src_offset = SIRFSOC_CLKC_DISP1_DTO_SRC,
650 .hw = {
651 .init = &clk_disp1dto_init,
652 },
653 };
654
655 static struct atlas7_div_init_data divider_list[] __initdata = {
656
657 { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock },
658 { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock },
659 { "sys2pll_qa1", "sys2pll_fixdiv", "sys2pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 8, &usbphy_div_lock },
660 { "sys3pll_qa1", "sys3pll_fixdiv", "sys3pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 12, &usbphy_div_lock },
661 { "sys0pll_qa2", "sys0pll_fixdiv", "sys0pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 0, &btss_div_lock },
662 { "sys1pll_qa2", "sys1pll_fixdiv", "sys1pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 4, &btss_div_lock },
663 { "sys2pll_qa2", "sys2pll_fixdiv", "sys2pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 8, &btss_div_lock },
664 { "sys3pll_qa2", "sys3pll_fixdiv", "sys3pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 12, &btss_div_lock },
665 { "sys0pll_qa3", "sys0pll_fixdiv", "sys0pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 0, &rgmii_div_lock },
666 { "sys1pll_qa3", "sys1pll_fixdiv", "sys1pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 4, &rgmii_div_lock },
667 { "sys2pll_qa3", "sys2pll_fixdiv", "sys2pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 8, &rgmii_div_lock },
668 { "sys3pll_qa3", "sys3pll_fixdiv", "sys3pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 12, &rgmii_div_lock },
669 { "sys0pll_qa4", "sys0pll_fixdiv", "sys0pll_a4", 0, 0, 0, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 0, &cpu_div_lock },
670 { "sys1pll_qa4", "sys1pll_fixdiv", "sys1pll_a4", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 4, &cpu_div_lock },
671 { "sys0pll_qa5", "sys0pll_fixdiv", "sys0pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 0, &sdphy01_div_lock },
672 { "sys1pll_qa5", "sys1pll_fixdiv", "sys1pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 4, &sdphy01_div_lock },
673 { "sys2pll_qa5", "sys2pll_fixdiv", "sys2pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 8, &sdphy01_div_lock },
674 { "sys3pll_qa5", "sys3pll_fixdiv", "sys3pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 12, &sdphy01_div_lock },
675 { "sys0pll_qa6", "sys0pll_fixdiv", "sys0pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 0, &sdphy23_div_lock },
676 { "sys1pll_qa6", "sys1pll_fixdiv", "sys1pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 4, &sdphy23_div_lock },
677 { "sys2pll_qa6", "sys2pll_fixdiv", "sys2pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 8, &sdphy23_div_lock },
678 { "sys3pll_qa6", "sys3pll_fixdiv", "sys3pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 12, &sdphy23_div_lock },
679 { "sys0pll_qa7", "sys0pll_fixdiv", "sys0pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 0, &sdphy45_div_lock },
680 { "sys1pll_qa7", "sys1pll_fixdiv", "sys1pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 4, &sdphy45_div_lock },
681 { "sys2pll_qa7", "sys2pll_fixdiv", "sys2pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 8, &sdphy45_div_lock },
682 { "sys3pll_qa7", "sys3pll_fixdiv", "sys3pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 12, &sdphy45_div_lock },
683 { "sys0pll_qa8", "sys0pll_fixdiv", "sys0pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 0, &sdphy67_div_lock },
684 { "sys1pll_qa8", "sys1pll_fixdiv", "sys1pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 4, &sdphy67_div_lock },
685 { "sys2pll_qa8", "sys2pll_fixdiv", "sys2pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 8, &sdphy67_div_lock },
686 { "sys3pll_qa8", "sys3pll_fixdiv", "sys3pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 12, &sdphy67_div_lock },
687 { "sys0pll_qa9", "sys0pll_fixdiv", "sys0pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 0, &can_div_lock },
688 { "sys1pll_qa9", "sys1pll_fixdiv", "sys1pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 4, &can_div_lock },
689 { "sys2pll_qa9", "sys2pll_fixdiv", "sys2pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 8, &can_div_lock },
690 { "sys3pll_qa9", "sys3pll_fixdiv", "sys3pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 12, &can_div_lock },
691 { "sys0pll_qa10", "sys0pll_fixdiv", "sys0pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 0, &deint_div_lock },
692 { "sys1pll_qa10", "sys1pll_fixdiv", "sys1pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 4, &deint_div_lock },
693 { "sys2pll_qa10", "sys2pll_fixdiv", "sys2pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 8, &deint_div_lock },
694 { "sys3pll_qa10", "sys3pll_fixdiv", "sys3pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 12, &deint_div_lock },
695 { "sys0pll_qa11", "sys0pll_fixdiv", "sys0pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 0, &nand_div_lock },
696 { "sys1pll_qa11", "sys1pll_fixdiv", "sys1pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 4, &nand_div_lock },
697 { "sys2pll_qa11", "sys2pll_fixdiv", "sys2pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 8, &nand_div_lock },
698 { "sys3pll_qa11", "sys3pll_fixdiv", "sys3pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 12, &nand_div_lock },
699 { "sys0pll_qa12", "sys0pll_fixdiv", "sys0pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 0, &disp0_div_lock },
700 { "sys1pll_qa12", "sys1pll_fixdiv", "sys1pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 4, &disp0_div_lock },
701 { "sys2pll_qa12", "sys2pll_fixdiv", "sys2pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 8, &disp0_div_lock },
702 { "sys3pll_qa12", "sys3pll_fixdiv", "sys3pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 12, &disp0_div_lock },
703 { "sys0pll_qa13", "sys0pll_fixdiv", "sys0pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 0, &disp1_div_lock },
704 { "sys1pll_qa13", "sys1pll_fixdiv", "sys1pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 4, &disp1_div_lock },
705 { "sys2pll_qa13", "sys2pll_fixdiv", "sys2pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 8, &disp1_div_lock },
706 { "sys3pll_qa13", "sys3pll_fixdiv", "sys3pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 12, &disp1_div_lock },
707 { "sys0pll_qa14", "sys0pll_fixdiv", "sys0pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 0, &gpu_div_lock },
708 { "sys1pll_qa14", "sys1pll_fixdiv", "sys1pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 4, &gpu_div_lock },
709 { "sys2pll_qa14", "sys2pll_fixdiv", "sys2pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 8, &gpu_div_lock },
710 { "sys3pll_qa14", "sys3pll_fixdiv", "sys3pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 12, &gpu_div_lock },
711 { "sys0pll_qa15", "sys0pll_fixdiv", "sys0pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 0, &gnss_div_lock },
712 { "sys1pll_qa15", "sys1pll_fixdiv", "sys1pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 4, &gnss_div_lock },
713 { "sys2pll_qa15", "sys2pll_fixdiv", "sys2pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 8, &gnss_div_lock },
714 { "sys3pll_qa15", "sys3pll_fixdiv", "sys3pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 12, &gnss_div_lock },
715 { "sys1pll_qa18", "sys1pll_fixdiv", "sys1pll_a18", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 24, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 12, &share_div_lock },
716 { "sys1pll_qa19", "sys1pll_fixdiv", "sys1pll_a19", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 16, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 8, &share_div_lock },
717 { "sys1pll_qa20", "sys1pll_fixdiv", "sys1pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 4, &share_div_lock },
718 { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock },
719 { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock },
720 { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock },
721 };
722
723 static const char * const i2s_clk_parents[] = {
724 "xin",
725 "xinw",
726 "audio_dto",
727
728 };
729
730 static const char * const usbphy_clk_parents[] = {
731 "xin",
732 "xinw",
733 "sys0pll_a1",
734 "sys1pll_a1",
735 "sys2pll_a1",
736 "sys3pll_a1",
737 };
738
739 static const char * const btss_clk_parents[] = {
740 "xin",
741 "xinw",
742 "sys0pll_a2",
743 "sys1pll_a2",
744 "sys2pll_a2",
745 "sys3pll_a2",
746 };
747
748 static const char * const rgmii_clk_parents[] = {
749 "xin",
750 "xinw",
751 "sys0pll_a3",
752 "sys1pll_a3",
753 "sys2pll_a3",
754 "sys3pll_a3",
755 };
756
757 static const char * const cpu_clk_parents[] = {
758 "xin",
759 "xinw",
760 "sys0pll_a4",
761 "sys1pll_a4",
762 "cpupll_clk1",
763 };
764
765 static const char * const sdphy01_clk_parents[] = {
766 "xin",
767 "xinw",
768 "sys0pll_a5",
769 "sys1pll_a5",
770 "sys2pll_a5",
771 "sys3pll_a5",
772 };
773
774 static const char * const sdphy23_clk_parents[] = {
775 "xin",
776 "xinw",
777 "sys0pll_a6",
778 "sys1pll_a6",
779 "sys2pll_a6",
780 "sys3pll_a6",
781 };
782
783 static const char * const sdphy45_clk_parents[] = {
784 "xin",
785 "xinw",
786 "sys0pll_a7",
787 "sys1pll_a7",
788 "sys2pll_a7",
789 "sys3pll_a7",
790 };
791
792 static const char * const sdphy67_clk_parents[] = {
793 "xin",
794 "xinw",
795 "sys0pll_a8",
796 "sys1pll_a8",
797 "sys2pll_a8",
798 "sys3pll_a8",
799 };
800
801 static const char * const can_clk_parents[] = {
802 "xin",
803 "xinw",
804 "sys0pll_a9",
805 "sys1pll_a9",
806 "sys2pll_a9",
807 "sys3pll_a9",
808 };
809
810 static const char * const deint_clk_parents[] = {
811 "xin",
812 "xinw",
813 "sys0pll_a10",
814 "sys1pll_a10",
815 "sys2pll_a10",
816 "sys3pll_a10",
817 };
818
819 static const char * const nand_clk_parents[] = {
820 "xin",
821 "xinw",
822 "sys0pll_a11",
823 "sys1pll_a11",
824 "sys2pll_a11",
825 "sys3pll_a11",
826 };
827
828 static const char * const disp0_clk_parents[] = {
829 "xin",
830 "xinw",
831 "sys0pll_a12",
832 "sys1pll_a12",
833 "sys2pll_a12",
834 "sys3pll_a12",
835 "disp0_dto",
836 };
837
838 static const char * const disp1_clk_parents[] = {
839 "xin",
840 "xinw",
841 "sys0pll_a13",
842 "sys1pll_a13",
843 "sys2pll_a13",
844 "sys3pll_a13",
845 "disp1_dto",
846 };
847
848 static const char * const gpu_clk_parents[] = {
849 "xin",
850 "xinw",
851 "sys0pll_a14",
852 "sys1pll_a14",
853 "sys2pll_a14",
854 "sys3pll_a14",
855 };
856
857 static const char * const gnss_clk_parents[] = {
858 "xin",
859 "xinw",
860 "sys0pll_a15",
861 "sys1pll_a15",
862 "sys2pll_a15",
863 "sys3pll_a15",
864 };
865
866 static const char * const sys_clk_parents[] = {
867 "xin",
868 "xinw",
869 "sys2pll_a20",
870 "sys1pll_a20",
871 "sys1pll_a19",
872 "sys1pll_a18",
873 "sys0pll_a20",
874 "sys1pll_a17",
875 };
876
877 static const char * const io_clk_parents[] = {
878 "xin",
879 "xinw",
880 "sys2pll_a20",
881 "sys1pll_a20",
882 "sys1pll_a19",
883 "sys1pll_a18",
884 "sys0pll_a20",
885 "sys1pll_a17",
886 };
887
888 static const char * const g2d_clk_parents[] = {
889 "xin",
890 "xinw",
891 "sys2pll_a20",
892 "sys1pll_a20",
893 "sys1pll_a19",
894 "sys1pll_a18",
895 "sys0pll_a20",
896 "sys1pll_a17",
897 };
898
899 static const char * const jpenc_clk_parents[] = {
900 "xin",
901 "xinw",
902 "sys2pll_a20",
903 "sys1pll_a20",
904 "sys1pll_a19",
905 "sys1pll_a18",
906 "sys0pll_a20",
907 "sys1pll_a17",
908 };
909
910 static const char * const vdec_clk_parents[] = {
911 "xin",
912 "xinw",
913 "sys2pll_a20",
914 "sys1pll_a20",
915 "sys1pll_a19",
916 "sys1pll_a18",
917 "sys0pll_a20",
918 "sys1pll_a17",
919 };
920
921 static const char * const gmac_clk_parents[] = {
922 "xin",
923 "xinw",
924 "sys2pll_a20",
925 "sys1pll_a20",
926 "sys1pll_a19",
927 "sys1pll_a18",
928 "sys0pll_a20",
929 "sys1pll_a17",
930 };
931
932 static const char * const usb_clk_parents[] = {
933 "xin",
934 "xinw",
935 "sys2pll_a20",
936 "sys1pll_a20",
937 "sys1pll_a19",
938 "sys1pll_a18",
939 "sys0pll_a20",
940 "sys1pll_a17",
941 };
942
943 static const char * const kas_clk_parents[] = {
944 "xin",
945 "xinw",
946 "sys2pll_a20",
947 "sys1pll_a20",
948 "sys1pll_a19",
949 "sys1pll_a18",
950 "sys0pll_a20",
951 "sys1pll_a17",
952 };
953
954 static const char * const sec_clk_parents[] = {
955 "xin",
956 "xinw",
957 "sys2pll_a20",
958 "sys1pll_a20",
959 "sys1pll_a19",
960 "sys1pll_a18",
961 "sys0pll_a20",
962 "sys1pll_a17",
963 };
964
965 static const char * const sdr_clk_parents[] = {
966 "xin",
967 "xinw",
968 "sys2pll_a20",
969 "sys1pll_a20",
970 "sys1pll_a19",
971 "sys1pll_a18",
972 "sys0pll_a20",
973 "sys1pll_a17",
974 };
975
976 static const char * const vip_clk_parents[] = {
977 "xin",
978 "xinw",
979 "sys2pll_a20",
980 "sys1pll_a20",
981 "sys1pll_a19",
982 "sys1pll_a18",
983 "sys0pll_a20",
984 "sys1pll_a17",
985 };
986
987 static const char * const nocd_clk_parents[] = {
988 "xin",
989 "xinw",
990 "sys2pll_a20",
991 "sys1pll_a20",
992 "sys1pll_a19",
993 "sys1pll_a18",
994 "sys0pll_a20",
995 "sys1pll_a17",
996 };
997
998 static const char * const nocr_clk_parents[] = {
999 "xin",
1000 "xinw",
1001 "sys2pll_a20",
1002 "sys1pll_a20",
1003 "sys1pll_a19",
1004 "sys1pll_a18",
1005 "sys0pll_a20",
1006 "sys1pll_a17",
1007 };
1008
1009 static const char * const tpiu_clk_parents[] = {
1010 "xin",
1011 "xinw",
1012 "sys2pll_a20",
1013 "sys1pll_a20",
1014 "sys1pll_a19",
1015 "sys1pll_a18",
1016 "sys0pll_a20",
1017 "sys1pll_a17",
1018 };
1019
1020 static struct atlas7_mux_init_data mux_list[] __initdata = {
1021
1022 { "i2s_mux", i2s_clk_parents, ARRAY_SIZE(i2s_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 2 },
1023 { "usbphy_mux", usbphy_clk_parents, ARRAY_SIZE(usbphy_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 3 },
1024 { "btss_mux", btss_clk_parents, ARRAY_SIZE(btss_clk_parents), 0, 0, SIRFSOC_CLKC_BTSS_CLK_SEL, 0, 3 },
1025 { "rgmii_mux", rgmii_clk_parents, ARRAY_SIZE(rgmii_clk_parents), 0, 0, SIRFSOC_CLKC_RGMII_CLK_SEL, 0, 3 },
1026 { "cpu_mux", cpu_clk_parents, ARRAY_SIZE(cpu_clk_parents), 0, 0, SIRFSOC_CLKC_CPU_CLK_SEL, 0, 3 },
1027 { "sdphy01_mux", sdphy01_clk_parents, ARRAY_SIZE(sdphy01_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY01_CLK_SEL, 0, 3 },
1028 { "sdphy23_mux", sdphy23_clk_parents, ARRAY_SIZE(sdphy23_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY23_CLK_SEL, 0, 3 },
1029 { "sdphy45_mux", sdphy45_clk_parents, ARRAY_SIZE(sdphy45_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY45_CLK_SEL, 0, 3 },
1030 { "sdphy67_mux", sdphy67_clk_parents, ARRAY_SIZE(sdphy67_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY67_CLK_SEL, 0, 3 },
1031 { "can_mux", can_clk_parents, ARRAY_SIZE(can_clk_parents), 0, 0, SIRFSOC_CLKC_CAN_CLK_SEL, 0, 3 },
1032 { "deint_mux", deint_clk_parents, ARRAY_SIZE(deint_clk_parents), 0, 0, SIRFSOC_CLKC_DEINT_CLK_SEL, 0, 3 },
1033 { "nand_mux", nand_clk_parents, ARRAY_SIZE(nand_clk_parents), 0, 0, SIRFSOC_CLKC_NAND_CLK_SEL, 0, 3 },
1034 { "disp0_mux", disp0_clk_parents, ARRAY_SIZE(disp0_clk_parents), 0, 0, SIRFSOC_CLKC_DISP0_CLK_SEL, 0, 3 },
1035 { "disp1_mux", disp1_clk_parents, ARRAY_SIZE(disp1_clk_parents), 0, 0, SIRFSOC_CLKC_DISP1_CLK_SEL, 0, 3 },
1036 { "gpu_mux", gpu_clk_parents, ARRAY_SIZE(gpu_clk_parents), 0, 0, SIRFSOC_CLKC_GPU_CLK_SEL, 0, 3 },
1037 { "gnss_mux", gnss_clk_parents, ARRAY_SIZE(gnss_clk_parents), 0, 0, SIRFSOC_CLKC_GNSS_CLK_SEL, 0, 3 },
1038 { "sys_mux", sys_clk_parents, ARRAY_SIZE(sys_clk_parents), 0, 0, SIRFSOC_CLKC_SYS_CLK_SEL, 0, 3 },
1039 { "io_mux", io_clk_parents, ARRAY_SIZE(io_clk_parents), 0, 0, SIRFSOC_CLKC_IO_CLK_SEL, 0, 3 },
1040 { "g2d_mux", g2d_clk_parents, ARRAY_SIZE(g2d_clk_parents), 0, 0, SIRFSOC_CLKC_G2D_CLK_SEL, 0, 3 },
1041 { "jpenc_mux", jpenc_clk_parents, ARRAY_SIZE(jpenc_clk_parents), 0, 0, SIRFSOC_CLKC_JPENC_CLK_SEL, 0, 3 },
1042 { "vdec_mux", vdec_clk_parents, ARRAY_SIZE(vdec_clk_parents), 0, 0, SIRFSOC_CLKC_VDEC_CLK_SEL, 0, 3 },
1043 { "gmac_mux", gmac_clk_parents, ARRAY_SIZE(gmac_clk_parents), 0, 0, SIRFSOC_CLKC_GMAC_CLK_SEL, 0, 3 },
1044 { "usb_mux", usb_clk_parents, ARRAY_SIZE(usb_clk_parents), 0, 0, SIRFSOC_CLKC_USB_CLK_SEL, 0, 3 },
1045 { "kas_mux", kas_clk_parents, ARRAY_SIZE(kas_clk_parents), 0, 0, SIRFSOC_CLKC_KAS_CLK_SEL, 0, 3 },
1046 { "sec_mux", sec_clk_parents, ARRAY_SIZE(sec_clk_parents), 0, 0, SIRFSOC_CLKC_SEC_CLK_SEL, 0, 3 },
1047 { "sdr_mux", sdr_clk_parents, ARRAY_SIZE(sdr_clk_parents), 0, 0, SIRFSOC_CLKC_SDR_CLK_SEL, 0, 3 },
1048 { "vip_mux", vip_clk_parents, ARRAY_SIZE(vip_clk_parents), 0, 0, SIRFSOC_CLKC_VIP_CLK_SEL, 0, 3 },
1049 { "nocd_mux", nocd_clk_parents, ARRAY_SIZE(nocd_clk_parents), 0, 0, SIRFSOC_CLKC_NOCD_CLK_SEL, 0, 3 },
1050 { "nocr_mux", nocr_clk_parents, ARRAY_SIZE(nocr_clk_parents), 0, 0, SIRFSOC_CLKC_NOCR_CLK_SEL, 0, 3 },
1051 { "tpiu_mux", tpiu_clk_parents, ARRAY_SIZE(tpiu_clk_parents), 0, 0, SIRFSOC_CLKC_TPIU_CLK_SEL, 0, 3 },
1052 };
1053
1054
1055 static struct atlas7_unit_init_data unit_list[] __initdata = {
1056
1057 { 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, 0, 0, &root0_gate_lock },
1058 { 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, 0, 0, &root0_gate_lock },
1059 { 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, 0, 0, &root0_gate_lock },
1060 { 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, 0, 0, &root0_gate_lock },
1061 { 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, 0, 0, &root0_gate_lock },
1062 { 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, 0, 0, &root0_gate_lock },
1063 { 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, 0, 0, &root0_gate_lock },
1064 { 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, 0, 0, &root0_gate_lock },
1065 { 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, 0, 0, &root0_gate_lock },
1066 { 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, 0, 0, &root0_gate_lock },
1067 { 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, 0, 0, &root0_gate_lock },
1068 { 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, 0, 0, &root0_gate_lock },
1069 { 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, 0, 0, &root0_gate_lock },
1070 { 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, 0, 0, &root0_gate_lock },
1071 { 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, 0, 0, &root0_gate_lock },
1072 { 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, 0, 0, &root0_gate_lock },
1073 { 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, 0, 0, &root0_gate_lock },
1074 { 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, 0, 0, &root0_gate_lock },
1075 { 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, 0, 0, &root0_gate_lock },
1076 { 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, 0, 0, &root0_gate_lock },
1077 { 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, 0, 0, &root0_gate_lock },
1078 { 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, 0, 0, &root0_gate_lock },
1079 { 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, 0, 0, &root0_gate_lock },
1080 { 23, "btm_btss", "btss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 0, 0, 0, &root1_gate_lock },
1081 { 24, "mediam_usbphy", "usbphy_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 1, 0, 0, &root1_gate_lock },
1082 { 25, "rtcm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 2, 0, 0, &root1_gate_lock },
1083 { 26, "audmscm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 3, 0, 0, &root1_gate_lock },
1084 { 27, "vdifm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 4, 0, 0, &root1_gate_lock },
1085 { 28, "gnssm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 5, 0, 0, &root1_gate_lock },
1086 { 29, "mediam_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 6, 0, 0, &root1_gate_lock },
1087 { 30, "cpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 8, 0, 0, &root1_gate_lock },
1088 { 31, "gpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 9, 0, 0, &root1_gate_lock },
1089 { 32, "audmscm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 11, 0, 0, &root1_gate_lock },
1090 { 33, "vdifm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 12, 0, 0, &root1_gate_lock },
1091 { 34, "gnssm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 13, 0, 0, &root1_gate_lock },
1092 { 35, "mediam_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 14, 0, 0, &root1_gate_lock },
1093 { 36, "ddrm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 15, 0, 0, &root1_gate_lock },
1094 { 37, "cpum_tpiu", "tpiu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 16, 0, 0, &root1_gate_lock },
1095 { 38, "gpum_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 17, 0, 0, &root1_gate_lock },
1096 { 39, "gnssm_rgmii", "rgmii_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 20, 0, 0, &root1_gate_lock },
1097 { 40, "mediam_vdec", "vdec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 21, 0, 0, &root1_gate_lock },
1098 { 41, "gpum_sdr", "sdr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 22, 0, 0, &root1_gate_lock },
1099 { 42, "vdifm_deint", "deint_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 23, 0, 0, &root1_gate_lock },
1100 { 43, "gnssm_can", "can_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 26, 0, 0, &root1_gate_lock },
1101 { 44, "mediam_usb", "usb_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 28, 0, 0, &root1_gate_lock },
1102 { 45, "gnssm_gmac", "gmac_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 29, 0, 0, &root1_gate_lock },
1103 { 46, "cvd_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 0, CLK_UNIT_NOC_CLOCK, 4, &leaf1_gate_lock },
1104 { 47, "timer_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 1, 0, 0, &leaf1_gate_lock },
1105 { 48, "pulse_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 2, 0, 0, &leaf1_gate_lock },
1106 { 49, "tsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 3, 0, 0, &leaf1_gate_lock },
1107 { 50, "tsc_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 21, 0, 0, &leaf1_gate_lock },
1108 { 51, "ioctop_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 4, 0, 0, &leaf1_gate_lock },
1109 { 52, "rsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 5, 0, 0, &leaf1_gate_lock },
1110 { 53, "dvm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 6, CLK_UNIT_NOC_SOCKET, 7, &leaf1_gate_lock },
1111 { 54, "lvds_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 7, CLK_UNIT_NOC_SOCKET, 8, &leaf1_gate_lock },
1112 { 55, "kas_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 8, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock },
1113 { 56, "ac97_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 9, 0, 0, &leaf1_gate_lock },
1114 { 57, "usp0_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 10, CLK_UNIT_NOC_SOCKET, 4, &leaf1_gate_lock },
1115 { 58, "usp1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 11, CLK_UNIT_NOC_SOCKET, 5, &leaf1_gate_lock },
1116 { 59, "usp2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 12, CLK_UNIT_NOC_SOCKET, 6, &leaf1_gate_lock },
1117 { 60, "dmac2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 13, CLK_UNIT_NOC_SOCKET, 1, &leaf1_gate_lock },
1118 { 61, "dmac3_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 14, CLK_UNIT_NOC_SOCKET, 2, &leaf1_gate_lock },
1119 { 62, "audioif_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 15, CLK_UNIT_NOC_SOCKET, 0, &leaf1_gate_lock },
1120 { 63, "i2s1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 17, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock },
1121 { 64, "thaudmscm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 22, 0, 0, &leaf1_gate_lock },
1122 { 65, "analogtest_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 23, 0, 0, &leaf1_gate_lock },
1123 { 66, "sys2pci_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 0, CLK_UNIT_NOC_CLOCK, 20, &leaf2_gate_lock },
1124 { 67, "pciarb_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 1, 0, 0, &leaf2_gate_lock },
1125 { 68, "pcicopy_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 2, 0, 0, &leaf2_gate_lock },
1126 { 69, "rom_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 3, 0, 0, &leaf2_gate_lock },
1127 { 70, "sdio23_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 4, 0, 0, &leaf2_gate_lock },
1128 { 71, "sdio45_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 5, 0, 0, &leaf2_gate_lock },
1129 { 72, "sdio67_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 6, 0, 0, &leaf2_gate_lock },
1130 { 73, "vip1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 7, 0, 0, &leaf2_gate_lock },
1131 { 74, "vip1_vip", "vdifm_vip", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 16, CLK_UNIT_NOC_CLOCK, 21, &leaf2_gate_lock },
1132 { 75, "sdio23_sdphy23", "vdifm_sdphy23", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 8, 0, 0, &leaf2_gate_lock },
1133 { 76, "sdio45_sdphy45", "vdifm_sdphy45", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 9, 0, 0, &leaf2_gate_lock },
1134 { 77, "sdio67_sdphy67", "vdifm_sdphy67", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 10, 0, 0, &leaf2_gate_lock },
1135 { 78, "vpp0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 11, CLK_UNIT_NOC_CLOCK, 22, &leaf2_gate_lock },
1136 { 79, "lcd0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 12, CLK_UNIT_NOC_CLOCK, 18, &leaf2_gate_lock },
1137 { 80, "vpp1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 13, CLK_UNIT_NOC_CLOCK, 23, &leaf2_gate_lock },
1138 { 81, "lcd1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 14, CLK_UNIT_NOC_CLOCK, 19, &leaf2_gate_lock },
1139 { 82, "dcu_deint", "vdifm_deint", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 15, CLK_UNIT_NOC_CLOCK, 17, &leaf2_gate_lock },
1140 { 83, "vdifm_dapa_r_nocr", "vdifm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 17, 0, 0, &leaf2_gate_lock },
1141 { 84, "gpio1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 18, 0, 0, &leaf2_gate_lock },
1142 { 85, "thvdifm_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 19, 0, 0, &leaf2_gate_lock },
1143 { 86, "gmac_rgmii", "gnssm_rgmii", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 0, 0, 0, &leaf3_gate_lock },
1144 { 87, "gmac_gmac", "gnssm_gmac", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 1, CLK_UNIT_NOC_CLOCK, 10, &leaf3_gate_lock },
1145 { 88, "uart1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 2, CLK_UNIT_NOC_SOCKET, 14, &leaf3_gate_lock },
1146 { 89, "dmac0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 3, CLK_UNIT_NOC_SOCKET, 11, &leaf3_gate_lock },
1147 { 90, "uart0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 4, CLK_UNIT_NOC_SOCKET, 13, &leaf3_gate_lock },
1148 { 91, "uart2_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 5, CLK_UNIT_NOC_SOCKET, 15, &leaf3_gate_lock },
1149 { 92, "uart3_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 6, CLK_UNIT_NOC_SOCKET, 16, &leaf3_gate_lock },
1150 { 93, "uart4_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 7, CLK_UNIT_NOC_SOCKET, 17, &leaf3_gate_lock },
1151 { 94, "uart5_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 8, CLK_UNIT_NOC_SOCKET, 18, &leaf3_gate_lock },
1152 { 95, "spi1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 9, CLK_UNIT_NOC_SOCKET, 12, &leaf3_gate_lock },
1153 { 96, "gnss_gnss", "gnssm_gnss", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 10, 0, 0, &leaf3_gate_lock },
1154 { 97, "canbus1_can", "gnssm_can", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 12, CLK_UNIT_NOC_CLOCK, 7, &leaf3_gate_lock },
1155 { 98, "ccsec_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 15, CLK_UNIT_NOC_CLOCK, 9, &leaf3_gate_lock },
1156 { 99, "ccpub_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 16, CLK_UNIT_NOC_CLOCK, 8, &leaf3_gate_lock },
1157 { 100, "gnssm_dapa_r_nocr", "gnssm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 13, 0, 0, &leaf3_gate_lock },
1158 { 101, "thgnssm_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 14, 0, 0, &leaf3_gate_lock },
1159 { 102, "media_vdec", "mediam_vdec", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 0, CLK_UNIT_NOC_CLOCK, 3, &leaf4_gate_lock },
1160 { 103, "media_jpenc", "mediam_jpenc", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 1, CLK_UNIT_NOC_CLOCK, 1, &leaf4_gate_lock },
1161 { 104, "g2d_g2d", "mediam_g2d", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 2, CLK_UNIT_NOC_CLOCK, 12, &leaf4_gate_lock },
1162 { 105, "i2c0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 3, CLK_UNIT_NOC_SOCKET, 21, &leaf4_gate_lock },
1163 { 106, "i2c1_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 4, CLK_UNIT_NOC_SOCKET, 20, &leaf4_gate_lock },
1164 { 107, "gpio0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 5, CLK_UNIT_NOC_SOCKET, 19, &leaf4_gate_lock },
1165 { 108, "nand_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 6, 0, 0, &leaf4_gate_lock },
1166 { 109, "sdio01_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 7, 0, 0, &leaf4_gate_lock },
1167 { 110, "sys2pci2_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 8, CLK_UNIT_NOC_CLOCK, 13, &leaf4_gate_lock },
1168 { 111, "sdio01_sdphy01", "mediam_sdphy01", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 9, 0, 0, &leaf4_gate_lock },
1169 { 112, "nand_nand", "mediam_nand", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 10, CLK_UNIT_NOC_CLOCK, 14, &leaf4_gate_lock },
1170 { 113, "usb0_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 11, CLK_UNIT_NOC_CLOCK, 15, &leaf4_gate_lock },
1171 { 114, "usb1_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 12, CLK_UNIT_NOC_CLOCK, 16, &leaf4_gate_lock },
1172 { 115, "usbphy0_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 13, 0, 0, &leaf4_gate_lock },
1173 { 116, "usbphy1_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 14, 0, 0, &leaf4_gate_lock },
1174 { 117, "thmediam_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 15, 0, 0, &leaf4_gate_lock },
1175 { 118, "memc_mem", "mempll_clk1", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 0, 0, 0, &leaf5_gate_lock },
1176 { 119, "dapa_mem", "mempll_clk1", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 1, 0, 0, &leaf5_gate_lock },
1177 { 120, "nocddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 2, 0, 0, &leaf5_gate_lock },
1178 { 121, "thddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 3, 0, 0, &leaf5_gate_lock },
1179 { 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, CLK_UNIT_NOC_SOCKET, 9, &leaf6_gate_lock },
1180 { 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, CLK_UNIT_NOC_SOCKET, 10, &leaf6_gate_lock },
1181 { 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, 0, 0, &leaf6_gate_lock },
1182 { 125, "coresight_tpiu", "cpum_tpiu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, 0, 0, &leaf6_gate_lock },
1183 { 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, CLK_UNIT_NOC_CLOCK, 0, &leaf7_gate_lock },
1184 { 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, CLK_UNIT_NOC_CLOCK, 11, &leaf7_gate_lock },
1185 { 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, 0, 0, &leaf7_gate_lock },
1186 { 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, 0, 0, &leaf8_gate_lock },
1187 { 130, "dmac4_io", "a7ca_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, 0, 0, &leaf8_gate_lock },
1188 { 131, "uart6_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, 0, 0, &leaf8_gate_lock },
1189 { 132, "usp3_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, 0, 0, &leaf8_gate_lock },
1190 { 133, "a7ca_io", "noc_btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, 0, 0, &leaf8_gate_lock },
1191 { 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, 0, 0, &leaf8_gate_lock },
1192 { 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, 0, 0, &leaf8_gate_lock },
1193 { 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, 0, 0, &root1_gate_lock },
1194 { 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, 0, 0, &leaf8_gate_lock },
1195 { 138, "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, 0, 0, &leaf0_gate_lock },
1196 { 139, "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, 0, 0, &leaf0_gate_lock },
1197 { 140, "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, 0, 0, &leaf0_gate_lock },
1198 { 141, "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, 0, 0, &leaf0_gate_lock },
1199 };
1200
1201 static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)];
1202
1203 static int unit_clk_is_enabled(struct clk_hw *hw)
1204 {
1205 struct clk_unit *clk = to_unitclk(hw);
1206 u32 reg;
1207
1208 reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
1209
1210 return !!(clkc_readl(reg) & BIT(clk->bit));
1211 }
1212
1213 static int unit_clk_enable(struct clk_hw *hw)
1214 {
1215 u32 reg;
1216 struct clk_unit *clk = to_unitclk(hw);
1217 unsigned long flags;
1218
1219 reg = clk->regofs;
1220
1221 spin_lock_irqsave(clk->lock, flags);
1222 clkc_writel(BIT(clk->bit), reg);
1223 if (clk->type == CLK_UNIT_NOC_CLOCK)
1224 clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR);
1225 else if (clk->type == CLK_UNIT_NOC_SOCKET)
1226 clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_SET);
1227
1228 spin_unlock_irqrestore(clk->lock, flags);
1229 return 0;
1230 }
1231
1232 static void unit_clk_disable(struct clk_hw *hw)
1233 {
1234 u32 reg;
1235 u32 i = 0;
1236 struct clk_unit *clk = to_unitclk(hw);
1237 unsigned long flags;
1238
1239 reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
1240 spin_lock_irqsave(clk->lock, flags);
1241 if (clk->type == CLK_UNIT_NOC_CLOCK) {
1242 clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_SET);
1243 while (!(clkc_readl(SIRFSOC_NOC_CLK_IDLE_STATUS) &
1244 BIT(clk->idle_bit)) && (i++ < 100)) {
1245 cpu_relax();
1246 udelay(10);
1247 }
1248
1249 if (i == 100) {
1250 pr_err("unit NoC Clock disconnect Error:timeout\n");
1251
1252 clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR);
1253 goto err;
1254 }
1255
1256 } else if (clk->type == CLK_UNIT_NOC_SOCKET)
1257 clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_CLR);
1258
1259 clkc_writel(BIT(clk->bit), reg);
1260 err:
1261 spin_unlock_irqrestore(clk->lock, flags);
1262 }
1263
1264 static const struct clk_ops unit_clk_ops = {
1265 .is_enabled = unit_clk_is_enabled,
1266 .enable = unit_clk_enable,
1267 .disable = unit_clk_disable,
1268 };
1269
1270 static struct clk * __init
1271 atlas7_unit_clk_register(struct device *dev, const char *name,
1272 const char * const parent_name, unsigned long flags,
1273 u32 regofs, u8 bit, u32 type, u8 idle_bit, spinlock_t *lock)
1274 {
1275 struct clk *clk;
1276 struct clk_unit *unit;
1277 struct clk_init_data init;
1278
1279 unit = kzalloc(sizeof(*unit), GFP_KERNEL);
1280 if (!unit)
1281 return ERR_PTR(-ENOMEM);
1282
1283 init.name = name;
1284 init.parent_names = &parent_name;
1285 init.num_parents = 1;
1286 init.ops = &unit_clk_ops;
1287 init.flags = flags;
1288
1289 unit->hw.init = &init;
1290 unit->regofs = regofs;
1291 unit->bit = bit;
1292
1293 unit->type = type;
1294 unit->idle_bit = idle_bit;
1295 unit->lock = lock;
1296
1297 clk = clk_register(dev, &unit->hw);
1298 if (IS_ERR(clk))
1299 kfree(unit);
1300
1301 return clk;
1302 }
1303
1304 static struct atlas7_reset_desc atlas7_reset_unit[] = {
1305 { "PWM", 0x0244, 0, 0x0320, 0, &leaf0_gate_lock },
1306 { "THCGUM", 0x0244, 3, 0x0320, 1, &leaf0_gate_lock },
1307 { "CVD", 0x04A0, 0, 0x032C, 0, &leaf1_gate_lock },
1308 { "TIMER", 0x04A0, 1, 0x032C, 1, &leaf1_gate_lock },
1309 { "PULSEC", 0x04A0, 2, 0x032C, 2, &leaf1_gate_lock },
1310 { "TSC", 0x04A0, 3, 0x032C, 3, &leaf1_gate_lock },
1311 { "IOCTOP", 0x04A0, 4, 0x032C, 4, &leaf1_gate_lock },
1312 { "RSC", 0x04A0, 5, 0x032C, 5, &leaf1_gate_lock },
1313 { "DVM", 0x04A0, 6, 0x032C, 6, &leaf1_gate_lock },
1314 { "LVDS", 0x04A0, 7, 0x032C, 7, &leaf1_gate_lock },
1315 { "KAS", 0x04A0, 8, 0x032C, 8, &leaf1_gate_lock },
1316 { "AC97", 0x04A0, 9, 0x032C, 9, &leaf1_gate_lock },
1317 { "USP0", 0x04A0, 10, 0x032C, 10, &leaf1_gate_lock },
1318 { "USP1", 0x04A0, 11, 0x032C, 11, &leaf1_gate_lock },
1319 { "USP2", 0x04A0, 12, 0x032C, 12, &leaf1_gate_lock },
1320 { "DMAC2", 0x04A0, 13, 0x032C, 13, &leaf1_gate_lock },
1321 { "DMAC3", 0x04A0, 14, 0x032C, 14, &leaf1_gate_lock },
1322 { "AUDIO", 0x04A0, 15, 0x032C, 15, &leaf1_gate_lock },
1323 { "I2S1", 0x04A0, 17, 0x032C, 16, &leaf1_gate_lock },
1324 { "PMU_AUDIO", 0x04A0, 22, 0x032C, 17, &leaf1_gate_lock },
1325 { "THAUDMSCM", 0x04A0, 23, 0x032C, 18, &leaf1_gate_lock },
1326 { "SYS2PCI", 0x04B8, 0, 0x0338, 0, &leaf2_gate_lock },
1327 { "PCIARB", 0x04B8, 1, 0x0338, 1, &leaf2_gate_lock },
1328 { "PCICOPY", 0x04B8, 2, 0x0338, 2, &leaf2_gate_lock },
1329 { "ROM", 0x04B8, 3, 0x0338, 3, &leaf2_gate_lock },
1330 { "SDIO23", 0x04B8, 4, 0x0338, 4, &leaf2_gate_lock },
1331 { "SDIO45", 0x04B8, 5, 0x0338, 5, &leaf2_gate_lock },
1332 { "SDIO67", 0x04B8, 6, 0x0338, 6, &leaf2_gate_lock },
1333 { "VIP1", 0x04B8, 7, 0x0338, 7, &leaf2_gate_lock },
1334 { "VPP0", 0x04B8, 11, 0x0338, 8, &leaf2_gate_lock },
1335 { "LCD0", 0x04B8, 12, 0x0338, 9, &leaf2_gate_lock },
1336 { "VPP1", 0x04B8, 13, 0x0338, 10, &leaf2_gate_lock },
1337 { "LCD1", 0x04B8, 14, 0x0338, 11, &leaf2_gate_lock },
1338 { "DCU", 0x04B8, 15, 0x0338, 12, &leaf2_gate_lock },
1339 { "GPIO", 0x04B8, 18, 0x0338, 13, &leaf2_gate_lock },
1340 { "DAPA_VDIFM", 0x04B8, 17, 0x0338, 15, &leaf2_gate_lock },
1341 { "THVDIFM", 0x04B8, 19, 0x0338, 16, &leaf2_gate_lock },
1342 { "RGMII", 0x04D0, 0, 0x0344, 0, &leaf3_gate_lock },
1343 { "GMAC", 0x04D0, 1, 0x0344, 1, &leaf3_gate_lock },
1344 { "UART1", 0x04D0, 2, 0x0344, 2, &leaf3_gate_lock },
1345 { "DMAC0", 0x04D0, 3, 0x0344, 3, &leaf3_gate_lock },
1346 { "UART0", 0x04D0, 4, 0x0344, 4, &leaf3_gate_lock },
1347 { "UART2", 0x04D0, 5, 0x0344, 5, &leaf3_gate_lock },
1348 { "UART3", 0x04D0, 6, 0x0344, 6, &leaf3_gate_lock },
1349 { "UART4", 0x04D0, 7, 0x0344, 7, &leaf3_gate_lock },
1350 { "UART5", 0x04D0, 8, 0x0344, 8, &leaf3_gate_lock },
1351 { "SPI1", 0x04D0, 9, 0x0344, 9, &leaf3_gate_lock },
1352 { "GNSS_SYS_M0", 0x04D0, 10, 0x0344, 10, &leaf3_gate_lock },
1353 { "CANBUS1", 0x04D0, 12, 0x0344, 11, &leaf3_gate_lock },
1354 { "CCSEC", 0x04D0, 15, 0x0344, 12, &leaf3_gate_lock },
1355 { "CCPUB", 0x04D0, 16, 0x0344, 13, &leaf3_gate_lock },
1356 { "DAPA_GNSSM", 0x04D0, 13, 0x0344, 14, &leaf3_gate_lock },
1357 { "THGNSSM", 0x04D0, 14, 0x0344, 15, &leaf3_gate_lock },
1358 { "VDEC", 0x04E8, 0, 0x0350, 0, &leaf4_gate_lock },
1359 { "JPENC", 0x04E8, 1, 0x0350, 1, &leaf4_gate_lock },
1360 { "G2D", 0x04E8, 2, 0x0350, 2, &leaf4_gate_lock },
1361 { "I2C0", 0x04E8, 3, 0x0350, 3, &leaf4_gate_lock },
1362 { "I2C1", 0x04E8, 4, 0x0350, 4, &leaf4_gate_lock },
1363 { "GPIO0", 0x04E8, 5, 0x0350, 5, &leaf4_gate_lock },
1364 { "NAND", 0x04E8, 6, 0x0350, 6, &leaf4_gate_lock },
1365 { "SDIO01", 0x04E8, 7, 0x0350, 7, &leaf4_gate_lock },
1366 { "SYS2PCI2", 0x04E8, 8, 0x0350, 8, &leaf4_gate_lock },
1367 { "USB0", 0x04E8, 11, 0x0350, 9, &leaf4_gate_lock },
1368 { "USB1", 0x04E8, 12, 0x0350, 10, &leaf4_gate_lock },
1369 { "THMEDIAM", 0x04E8, 15, 0x0350, 11, &leaf4_gate_lock },
1370 { "MEMC_DDRPHY", 0x0500, 0, 0x035C, 0, &leaf5_gate_lock },
1371 { "MEMC_UPCTL", 0x0500, 0, 0x035C, 1, &leaf5_gate_lock },
1372 { "DAPA_MEM", 0x0500, 1, 0x035C, 2, &leaf5_gate_lock },
1373 { "MEMC_MEMDIV", 0x0500, 0, 0x035C, 3, &leaf5_gate_lock },
1374 { "THDDRM", 0x0500, 3, 0x035C, 4, &leaf5_gate_lock },
1375 { "CORESIGHT", 0x0518, 3, 0x0368, 13, &leaf6_gate_lock },
1376 { "THCPUM", 0x0518, 4, 0x0368, 17, &leaf6_gate_lock },
1377 { "GRAPHIC", 0x0530, 0, 0x0374, 0, &leaf7_gate_lock },
1378 { "VSS_SDR", 0x0530, 1, 0x0374, 1, &leaf7_gate_lock },
1379 { "THGPUM", 0x0530, 2, 0x0374, 2, &leaf7_gate_lock },
1380 { "DMAC4", 0x0548, 2, 0x0380, 1, &leaf8_gate_lock },
1381 { "UART6", 0x0548, 3, 0x0380, 2, &leaf8_gate_lock },
1382 { "USP3", 0x0548, 4, 0x0380, 3, &leaf8_gate_lock },
1383 { "THBTM", 0x0548, 5, 0x0380, 5, &leaf8_gate_lock },
1384 { "A7CA", 0x0548, 1, 0x0380, 0, &leaf8_gate_lock },
1385 { "A7CA_APB", 0x0548, 5, 0x0380, 4, &leaf8_gate_lock },
1386 };
1387
1388 static int atlas7_reset_module(struct reset_controller_dev *rcdev,
1389 unsigned long reset_idx)
1390 {
1391 struct atlas7_reset_desc *reset = &atlas7_reset_unit[reset_idx];
1392 unsigned long flags;
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404 spin_lock_irqsave(reset->lock, flags);
1405
1406 if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) {
1407 clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
1408 udelay(2);
1409 clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
1410 clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
1411
1412 clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
1413 } else {
1414 clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
1415 clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
1416 udelay(2);
1417 clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
1418 clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
1419 }
1420 spin_unlock_irqrestore(reset->lock, flags);
1421
1422 return 0;
1423 }
1424
1425 static const struct reset_control_ops atlas7_rst_ops = {
1426 .reset = atlas7_reset_module,
1427 };
1428
1429 static struct reset_controller_dev atlas7_rst_ctlr = {
1430 .ops = &atlas7_rst_ops,
1431 .owner = THIS_MODULE,
1432 .of_reset_n_cells = 1,
1433 };
1434
1435 static void __init atlas7_clk_init(struct device_node *np)
1436 {
1437 struct clk *clk;
1438 struct atlas7_div_init_data *div;
1439 struct atlas7_mux_init_data *mux;
1440 struct atlas7_unit_init_data *unit;
1441 int i;
1442 int ret;
1443
1444 sirfsoc_clk_vbase = of_iomap(np, 0);
1445 if (!sirfsoc_clk_vbase)
1446 panic("unable to map clkc registers\n");
1447
1448 of_node_put(np);
1449
1450 clk = clk_register(NULL, &clk_cpupll.hw);
1451 BUG_ON(!clk);
1452 clk = clk_register(NULL, &clk_mempll.hw);
1453 BUG_ON(!clk);
1454 clk = clk_register(NULL, &clk_sys0pll.hw);
1455 BUG_ON(!clk);
1456 clk = clk_register(NULL, &clk_sys1pll.hw);
1457 BUG_ON(!clk);
1458 clk = clk_register(NULL, &clk_sys2pll.hw);
1459 BUG_ON(!clk);
1460 clk = clk_register(NULL, &clk_sys3pll.hw);
1461 BUG_ON(!clk);
1462
1463 clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0,
1464 sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0,
1465 pll_div_table, &cpupll_ctrl1_lock);
1466 BUG_ON(!clk);
1467 clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0,
1468 sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0,
1469 pll_div_table, &cpupll_ctrl1_lock);
1470 BUG_ON(!clk);
1471 clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0,
1472 sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0,
1473 pll_div_table, &cpupll_ctrl1_lock);
1474 BUG_ON(!clk);
1475
1476 clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0,
1477 sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0,
1478 pll_div_table, &mempll_ctrl1_lock);
1479 BUG_ON(!clk);
1480 clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0,
1481 sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0,
1482 pll_div_table, &mempll_ctrl1_lock);
1483 BUG_ON(!clk);
1484 clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0,
1485 sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0,
1486 pll_div_table, &mempll_ctrl1_lock);
1487 BUG_ON(!clk);
1488
1489 clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0,
1490 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0,
1491 pll_div_table, &sys0pll_ctrl1_lock);
1492 BUG_ON(!clk);
1493 clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0,
1494 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0,
1495 pll_div_table, &sys0pll_ctrl1_lock);
1496 BUG_ON(!clk);
1497 clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0,
1498 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0,
1499 pll_div_table, &sys0pll_ctrl1_lock);
1500 BUG_ON(!clk);
1501 clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco",
1502 CLK_SET_RATE_PARENT, 1, 2);
1503
1504 clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0,
1505 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0,
1506 pll_div_table, &sys1pll_ctrl1_lock);
1507 BUG_ON(!clk);
1508 clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0,
1509 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0,
1510 pll_div_table, &sys1pll_ctrl1_lock);
1511 BUG_ON(!clk);
1512 clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0,
1513 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0,
1514 pll_div_table, &sys1pll_ctrl1_lock);
1515 BUG_ON(!clk);
1516 clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco",
1517 CLK_SET_RATE_PARENT, 1, 2);
1518
1519 clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0,
1520 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0,
1521 pll_div_table, &sys2pll_ctrl1_lock);
1522 BUG_ON(!clk);
1523 clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0,
1524 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0,
1525 pll_div_table, &sys2pll_ctrl1_lock);
1526 BUG_ON(!clk);
1527 clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0,
1528 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0,
1529 pll_div_table, &sys2pll_ctrl1_lock);
1530 BUG_ON(!clk);
1531 clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco",
1532 CLK_SET_RATE_PARENT, 1, 2);
1533
1534 clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0,
1535 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0,
1536 pll_div_table, &sys3pll_ctrl1_lock);
1537 BUG_ON(!clk);
1538 clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0,
1539 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0,
1540 pll_div_table, &sys3pll_ctrl1_lock);
1541 BUG_ON(!clk);
1542 clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0,
1543 sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0,
1544 pll_div_table, &sys3pll_ctrl1_lock);
1545 BUG_ON(!clk);
1546 clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco",
1547 CLK_SET_RATE_PARENT, 1, 2);
1548
1549 BUG_ON(!clk);
1550 clk = clk_register_fixed_factor(NULL, "xinw_fixdiv_btslow", "xinw",
1551 CLK_SET_RATE_PARENT, 1, 4);
1552
1553 BUG_ON(!clk);
1554 clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1",
1555 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1556 12, 0, &cpupll_ctrl1_lock);
1557 BUG_ON(!clk);
1558 clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2",
1559 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1560 13, 0, &cpupll_ctrl1_lock);
1561 BUG_ON(!clk);
1562 clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3",
1563 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1564 14, 0, &cpupll_ctrl1_lock);
1565 BUG_ON(!clk);
1566
1567 clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1",
1568 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1569 sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1570 12, 0, &mempll_ctrl1_lock);
1571 BUG_ON(!clk);
1572 clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2",
1573 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1574 13, 0, &mempll_ctrl1_lock);
1575 BUG_ON(!clk);
1576 clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3",
1577 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1578 14, 0, &mempll_ctrl1_lock);
1579 BUG_ON(!clk);
1580
1581 clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1",
1582 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1583 12, 0, &sys0pll_ctrl1_lock);
1584 BUG_ON(!clk);
1585 clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2",
1586 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1587 13, 0, &sys0pll_ctrl1_lock);
1588 BUG_ON(!clk);
1589 clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3",
1590 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1591 14, 0, &sys0pll_ctrl1_lock);
1592 BUG_ON(!clk);
1593
1594 clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1",
1595 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1596 12, 0, &sys1pll_ctrl1_lock);
1597 BUG_ON(!clk);
1598 clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2",
1599 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1600 13, 0, &sys1pll_ctrl1_lock);
1601 BUG_ON(!clk);
1602 clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3",
1603 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1604 14, 0, &sys1pll_ctrl1_lock);
1605 BUG_ON(!clk);
1606
1607 clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1",
1608 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1609 12, 0, &sys2pll_ctrl1_lock);
1610 BUG_ON(!clk);
1611 clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2",
1612 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1613 13, 0, &sys2pll_ctrl1_lock);
1614 BUG_ON(!clk);
1615 clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3",
1616 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1617 14, 0, &sys2pll_ctrl1_lock);
1618 BUG_ON(!clk);
1619
1620 clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1",
1621 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1622 12, 0, &sys3pll_ctrl1_lock);
1623 BUG_ON(!clk);
1624 clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2",
1625 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1626 13, 0, &sys3pll_ctrl1_lock);
1627 BUG_ON(!clk);
1628 clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3",
1629 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1630 14, 0, &sys3pll_ctrl1_lock);
1631 BUG_ON(!clk);
1632
1633 clk = clk_register(NULL, &clk_audio_dto.hw);
1634 BUG_ON(!clk);
1635
1636 clk = clk_register(NULL, &clk_disp0_dto.hw);
1637 BUG_ON(!clk);
1638
1639 clk = clk_register(NULL, &clk_disp1_dto.hw);
1640 BUG_ON(!clk);
1641
1642 for (i = 0; i < ARRAY_SIZE(divider_list); i++) {
1643 div = ÷r_list[i];
1644 clk = clk_register_divider(NULL, div->div_name,
1645 div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset,
1646 div->shift, div->width, 0, div->lock);
1647 BUG_ON(!clk);
1648 clk = clk_register_gate(NULL, div->gate_name, div->div_name,
1649 div->gate_flags, sirfsoc_clk_vbase + div->gate_offset,
1650 div->gate_bit, 0, div->lock);
1651 BUG_ON(!clk);
1652 }
1653
1654 for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
1655 mux = &mux_list[i];
1656 clk = clk_register_mux(NULL, mux->mux_name, mux->parent_names,
1657 mux->parent_num, mux->flags,
1658 sirfsoc_clk_vbase + mux->mux_offset,
1659 mux->shift, mux->width,
1660 mux->mux_flags, NULL);
1661 atlas7_clks[ARRAY_SIZE(unit_list) + i] = clk;
1662 BUG_ON(!clk);
1663 }
1664
1665 for (i = 0; i < ARRAY_SIZE(unit_list); i++) {
1666 unit = &unit_list[i];
1667 atlas7_clks[i] = atlas7_unit_clk_register(NULL, unit->unit_name, unit->parent_name,
1668 unit->flags, unit->regofs, unit->bit, unit->type, unit->idle_bit, unit->lock);
1669 BUG_ON(!atlas7_clks[i]);
1670 }
1671
1672 clk_data.clks = atlas7_clks;
1673 clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list);
1674
1675 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1676 BUG_ON(ret);
1677
1678 atlas7_rst_ctlr.of_node = np;
1679 atlas7_rst_ctlr.nr_resets = ARRAY_SIZE(atlas7_reset_unit);
1680 reset_controller_register(&atlas7_rst_ctlr);
1681 }
1682 CLK_OF_DECLARE(atlas7_clk, "sirf,atlas7-car", atlas7_clk_init);