This source file includes following definitions.
- _omap3_dpll_write_clken
- _omap3_wait_dpll_status
- _omap3_dpll_compute_freqsel
- _omap3_noncore_dpll_lock
- _omap3_noncore_dpll_bypass
- _omap3_noncore_dpll_stop
- _lookup_dco
- _lookup_sddiv
- omap3_noncore_dpll_program
- omap3_dpll_recalc
- omap3_noncore_dpll_enable
- omap3_noncore_dpll_disable
- omap3_noncore_dpll_determine_rate
- omap3_noncore_dpll_set_parent
- omap3_noncore_dpll_set_rate
- omap3_noncore_dpll_set_rate_and_parent
- omap3_dpll_autoidle_read
- omap3_dpll_allow_idle
- omap3_dpll_deny_idle
- omap3_find_clkoutx2_dpll
- omap3_clkoutx2_recalc
- omap3_core_dpll_save_context
- omap3_core_dpll_restore_context
- omap3_noncore_dpll_save_context
- omap3_noncore_dpll_restore_context
- omap3_dpll4_set_rate
- omap3_dpll4_set_rate_and_parent
- omap3_dpll5_apply_errata
- omap3_dpll5_set_rate
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/bitops.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk/ti.h>
28
29 #include "clock.h"
30
31
32 #define DPLL_AUTOIDLE_DISABLE 0x0
33 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
34
35 #define MAX_DPLL_WAIT_TRIES 1000000
36
37 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
38
39
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
43
44
45
46
47 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
48 {
49 const struct dpll_data *dd;
50 u32 v;
51
52 dd = clk->dpll_data;
53
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
55 v &= ~dd->enable_mask;
56 v |= clken_bits << __ffs(dd->enable_mask);
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
58 }
59
60
61 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
62 {
63 const struct dpll_data *dd;
64 int i = 0;
65 int ret = -EINVAL;
66 const char *clk_name;
67
68 dd = clk->dpll_data;
69 clk_name = clk_hw_get_name(&clk->hw);
70
71 state <<= __ffs(dd->idlest_mask);
72
73 while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
74 != state) && i < MAX_DPLL_WAIT_TRIES) {
75 i++;
76 udelay(1);
77 }
78
79 if (i == MAX_DPLL_WAIT_TRIES) {
80 pr_err("clock: %s failed transition to '%s'\n",
81 clk_name, (state) ? "locked" : "bypassed");
82 } else {
83 pr_debug("clock: %s transition to '%s' in %d loops\n",
84 clk_name, (state) ? "locked" : "bypassed", i);
85
86 ret = 0;
87 }
88
89 return ret;
90 }
91
92
93 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
94 {
95 unsigned long fint;
96 u16 f = 0;
97
98 fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n;
99
100 pr_debug("clock: fint is %lu\n", fint);
101
102 if (fint >= 750000 && fint <= 1000000)
103 f = 0x3;
104 else if (fint > 1000000 && fint <= 1250000)
105 f = 0x4;
106 else if (fint > 1250000 && fint <= 1500000)
107 f = 0x5;
108 else if (fint > 1500000 && fint <= 1750000)
109 f = 0x6;
110 else if (fint > 1750000 && fint <= 2100000)
111 f = 0x7;
112 else if (fint > 7500000 && fint <= 10000000)
113 f = 0xB;
114 else if (fint > 10000000 && fint <= 12500000)
115 f = 0xC;
116 else if (fint > 12500000 && fint <= 15000000)
117 f = 0xD;
118 else if (fint > 15000000 && fint <= 17500000)
119 f = 0xE;
120 else if (fint > 17500000 && fint <= 21000000)
121 f = 0xF;
122 else
123 pr_debug("clock: unknown freqsel setting for %d\n", n);
124
125 return f;
126 }
127
128
129
130
131
132
133
134
135
136
137
138 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
139 {
140 const struct dpll_data *dd;
141 u8 ai;
142 u8 state = 1;
143 int r = 0;
144
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));
146
147 dd = clk->dpll_data;
148 state <<= __ffs(dd->idlest_mask);
149
150
151 if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
152 state)
153 goto done;
154
155 ai = omap3_dpll_autoidle_read(clk);
156
157 if (ai)
158 omap3_dpll_deny_idle(clk);
159
160 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
161
162 r = _omap3_wait_dpll_status(clk, 1);
163
164 if (ai)
165 omap3_dpll_allow_idle(clk);
166
167 done:
168 return r;
169 }
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
185 {
186 int r;
187 u8 ai;
188
189 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
190 return -EINVAL;
191
192 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
193 clk_hw_get_name(&clk->hw));
194
195 ai = omap3_dpll_autoidle_read(clk);
196
197 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
198
199 r = _omap3_wait_dpll_status(clk, 0);
200
201 if (ai)
202 omap3_dpll_allow_idle(clk);
203
204 return r;
205 }
206
207
208
209
210
211
212
213
214
215
216 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
217 {
218 u8 ai;
219
220 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
221 return -EINVAL;
222
223 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));
224
225 ai = omap3_dpll_autoidle_read(clk);
226
227 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
228
229 if (ai)
230 omap3_dpll_allow_idle(clk);
231
232 return 0;
233 }
234
235
236
237
238
239
240
241
242
243
244
245
246
247 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
248 {
249 unsigned long fint, clkinp;
250
251 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
252 fint = (clkinp / n) * m;
253
254 if (fint < 1000000000)
255 *dco = 2;
256 else
257 *dco = 4;
258 }
259
260
261
262
263
264
265
266
267
268
269
270
271
272 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
273 {
274 unsigned long clkinp, sd;
275 int mod1, mod2;
276
277 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
278
279
280
281
282
283 clkinp /= 100000;
284 mod1 = (clkinp * m) % (250 * n);
285 sd = (clkinp * m) / (250 * n);
286 mod2 = sd % 10;
287 sd /= 10;
288
289 if (mod1 || mod2)
290 sd++;
291 *sd_div = sd;
292 }
293
294
295
296
297
298
299
300
301
302 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
303 {
304 struct dpll_data *dd = clk->dpll_data;
305 u8 dco, sd_div, ai = 0;
306 u32 v;
307 bool errata_i810;
308
309
310 _omap3_noncore_dpll_bypass(clk);
311
312
313
314
315
316 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
317 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
318 v &= ~dd->freqsel_mask;
319 v |= freqsel << __ffs(dd->freqsel_mask);
320 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
321 }
322
323
324 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
325
326
327 if (dd->dcc_mask) {
328 if (dd->last_rounded_rate >= dd->dcc_rate)
329 v |= dd->dcc_mask;
330 else
331 v &= ~dd->dcc_mask;
332 }
333
334 v &= ~(dd->mult_mask | dd->div1_mask);
335 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
336 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
337
338
339 if (dd->dco_mask) {
340 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
341 v &= ~(dd->dco_mask);
342 v |= dco << __ffs(dd->dco_mask);
343 }
344 if (dd->sddiv_mask) {
345 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
346 dd->last_rounded_n);
347 v &= ~(dd->sddiv_mask);
348 v |= sd_div << __ffs(dd->sddiv_mask);
349 }
350
351
352
353
354
355
356
357
358 errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810;
359
360 if (errata_i810) {
361 ai = omap3_dpll_autoidle_read(clk);
362 if (ai) {
363 omap3_dpll_deny_idle(clk);
364
365
366 omap3_dpll_autoidle_read(clk);
367 }
368 }
369
370 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
371
372
373 if (dd->m4xen_mask || dd->lpmode_mask) {
374 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
375
376 if (dd->m4xen_mask) {
377 if (dd->last_rounded_m4xen)
378 v |= dd->m4xen_mask;
379 else
380 v &= ~dd->m4xen_mask;
381 }
382
383 if (dd->lpmode_mask) {
384 if (dd->last_rounded_lpmode)
385 v |= dd->lpmode_mask;
386 else
387 v &= ~dd->lpmode_mask;
388 }
389
390 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
391 }
392
393
394
395
396
397 _omap3_noncore_dpll_lock(clk);
398
399 if (errata_i810 && ai)
400 omap3_dpll_allow_idle(clk);
401
402 return 0;
403 }
404
405
406
407
408
409
410
411
412
413 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
414 {
415 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
416
417 return omap2_get_dpll_rate(clk);
418 }
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436 int omap3_noncore_dpll_enable(struct clk_hw *hw)
437 {
438 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
439 int r;
440 struct dpll_data *dd;
441 struct clk_hw *parent;
442
443 dd = clk->dpll_data;
444 if (!dd)
445 return -EINVAL;
446
447 if (clk->clkdm) {
448 r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
449 if (r) {
450 WARN(1,
451 "%s: could not enable %s's clockdomain %s: %d\n",
452 __func__, clk_hw_get_name(hw),
453 clk->clkdm_name, r);
454 return r;
455 }
456 }
457
458 parent = clk_hw_get_parent(hw);
459
460 if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {
461 WARN_ON(parent != dd->clk_bypass);
462 r = _omap3_noncore_dpll_bypass(clk);
463 } else {
464 WARN_ON(parent != dd->clk_ref);
465 r = _omap3_noncore_dpll_lock(clk);
466 }
467
468 return r;
469 }
470
471
472
473
474
475
476
477
478 void omap3_noncore_dpll_disable(struct clk_hw *hw)
479 {
480 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
481
482 _omap3_noncore_dpll_stop(clk);
483 if (clk->clkdm)
484 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
485 }
486
487
488
489
490
491
492
493
494
495
496
497
498
499 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
500 struct clk_rate_request *req)
501 {
502 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
503 struct dpll_data *dd;
504
505 if (!req->rate)
506 return -EINVAL;
507
508 dd = clk->dpll_data;
509 if (!dd)
510 return -EINVAL;
511
512 if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
513 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
514 req->best_parent_hw = dd->clk_bypass;
515 } else {
516 req->rate = omap2_dpll_round_rate(hw, req->rate,
517 &req->best_parent_rate);
518 req->best_parent_hw = dd->clk_ref;
519 }
520
521 req->best_parent_rate = req->rate;
522
523 return 0;
524 }
525
526
527
528
529
530
531
532
533
534 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
535 {
536 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
537 int ret;
538
539 if (!hw)
540 return -EINVAL;
541
542 if (index)
543 ret = _omap3_noncore_dpll_bypass(clk);
544 else
545 ret = _omap3_noncore_dpll_lock(clk);
546
547 return ret;
548 }
549
550
551
552
553
554
555
556
557
558
559
560
561 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
562 unsigned long parent_rate)
563 {
564 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
565 struct dpll_data *dd;
566 u16 freqsel = 0;
567 int ret;
568
569 if (!hw || !rate)
570 return -EINVAL;
571
572 dd = clk->dpll_data;
573 if (!dd)
574 return -EINVAL;
575
576 if (clk_hw_get_parent(hw) != dd->clk_ref)
577 return -EINVAL;
578
579 if (dd->last_rounded_rate == 0)
580 return -EINVAL;
581
582
583 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
584 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
585 WARN_ON(!freqsel);
586 }
587
588 pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
589 clk_hw_get_name(hw), rate);
590
591 ret = omap3_noncore_dpll_program(clk, freqsel);
592
593 return ret;
594 }
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
610 unsigned long rate,
611 unsigned long parent_rate,
612 u8 index)
613 {
614 int ret;
615
616 if (!hw || !rate)
617 return -EINVAL;
618
619
620
621
622
623
624 if (index)
625 ret = omap3_noncore_dpll_set_parent(hw, index);
626 else
627 ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
628
629 return ret;
630 }
631
632
633
634
635
636
637
638
639
640
641
642 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
643 {
644 const struct dpll_data *dd;
645 u32 v;
646
647 if (!clk || !clk->dpll_data)
648 return -EINVAL;
649
650 dd = clk->dpll_data;
651
652 if (!dd->autoidle_mask)
653 return -EINVAL;
654
655 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
656 v &= dd->autoidle_mask;
657 v >>= __ffs(dd->autoidle_mask);
658
659 return v;
660 }
661
662
663
664
665
666
667
668
669
670
671 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
672 {
673 const struct dpll_data *dd;
674 u32 v;
675
676 if (!clk || !clk->dpll_data)
677 return;
678
679 dd = clk->dpll_data;
680
681 if (!dd->autoidle_mask)
682 return;
683
684
685
686
687
688
689 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
690 v &= ~dd->autoidle_mask;
691 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
692 ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
693 }
694
695
696
697
698
699
700
701 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
702 {
703 const struct dpll_data *dd;
704 u32 v;
705
706 if (!clk || !clk->dpll_data)
707 return;
708
709 dd = clk->dpll_data;
710
711 if (!dd->autoidle_mask)
712 return;
713
714 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
715 v &= ~dd->autoidle_mask;
716 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
717 ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
718 }
719
720
721
722
723 static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
724 {
725 struct clk_hw_omap *pclk = NULL;
726
727
728 do {
729 do {
730 hw = clk_hw_get_parent(hw);
731 } while (hw && (!omap2_clk_is_hw_omap(hw)));
732 if (!hw)
733 break;
734 pclk = to_clk_hw_omap(hw);
735 } while (pclk && !pclk->dpll_data);
736
737
738 if (!pclk) {
739 WARN_ON(1);
740 return NULL;
741 }
742
743 return pclk;
744 }
745
746
747
748
749
750
751
752
753 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
754 unsigned long parent_rate)
755 {
756 const struct dpll_data *dd;
757 unsigned long rate;
758 u32 v;
759 struct clk_hw_omap *pclk = NULL;
760
761 if (!parent_rate)
762 return 0;
763
764 pclk = omap3_find_clkoutx2_dpll(hw);
765
766 if (!pclk)
767 return 0;
768
769 dd = pclk->dpll_data;
770
771 WARN_ON(!dd->enable_mask);
772
773 v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
774 v >>= __ffs(dd->enable_mask);
775 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
776 rate = parent_rate;
777 else
778 rate = parent_rate * 2;
779 return rate;
780 }
781
782
783
784
785
786
787
788
789 int omap3_core_dpll_save_context(struct clk_hw *hw)
790 {
791 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
792 struct dpll_data *dd;
793 u32 v;
794
795 dd = clk->dpll_data;
796
797 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
798 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
799
800 if (clk->context == DPLL_LOCKED) {
801 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
802 dd->last_rounded_m = (v & dd->mult_mask) >>
803 __ffs(dd->mult_mask);
804 dd->last_rounded_n = ((v & dd->div1_mask) >>
805 __ffs(dd->div1_mask)) + 1;
806 }
807
808 return 0;
809 }
810
811
812
813
814
815
816
817
818 void omap3_core_dpll_restore_context(struct clk_hw *hw)
819 {
820 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
821 const struct dpll_data *dd;
822 u32 v;
823
824 dd = clk->dpll_data;
825
826 if (clk->context == DPLL_LOCKED) {
827 _omap3_dpll_write_clken(clk, 0x4);
828 _omap3_wait_dpll_status(clk, 0);
829
830 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
831 v &= ~(dd->mult_mask | dd->div1_mask);
832 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
833 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
834 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
835
836 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
837 _omap3_wait_dpll_status(clk, 1);
838 } else {
839 _omap3_dpll_write_clken(clk, clk->context);
840 }
841 }
842
843
844
845
846
847
848
849
850 int omap3_noncore_dpll_save_context(struct clk_hw *hw)
851 {
852 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
853 struct dpll_data *dd;
854 u32 v;
855
856 dd = clk->dpll_data;
857
858 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
859 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
860
861 if (clk->context == DPLL_LOCKED) {
862 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
863 dd->last_rounded_m = (v & dd->mult_mask) >>
864 __ffs(dd->mult_mask);
865 dd->last_rounded_n = ((v & dd->div1_mask) >>
866 __ffs(dd->div1_mask)) + 1;
867 }
868
869 return 0;
870 }
871
872
873
874
875
876
877
878
879 void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
880 {
881 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
882 const struct dpll_data *dd;
883 u32 ctrl, mult_div1;
884
885 dd = clk->dpll_data;
886
887 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
888 mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
889
890 if (clk->context == ((ctrl & dd->enable_mask) >>
891 __ffs(dd->enable_mask)) &&
892 dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
893 __ffs(dd->mult_mask)) &&
894 dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
895 __ffs(dd->div1_mask)) + 1) {
896
897 return;
898 }
899
900 if (clk->context == DPLL_LOCKED)
901 omap3_noncore_dpll_program(clk, 0);
902 else
903 _omap3_dpll_write_clken(clk, clk->context);
904 }
905
906
907 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
908 .allow_idle = omap3_dpll_allow_idle,
909 .deny_idle = omap3_dpll_deny_idle,
910 };
911
912
913
914
915
916
917
918
919
920
921
922
923 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
924 unsigned long parent_rate)
925 {
926
927
928
929
930
931 if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
932 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
933 return -EINVAL;
934 }
935
936 return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
937 }
938
939
940
941
942
943
944
945
946
947
948
949
950
951 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
952 unsigned long parent_rate, u8 index)
953 {
954 if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
955 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
956 return -EINVAL;
957 }
958
959 return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
960 index);
961 }
962
963
964 static bool omap3_dpll5_apply_errata(struct clk_hw *hw,
965 unsigned long parent_rate)
966 {
967 struct omap3_dpll5_settings {
968 unsigned int rate, m, n;
969 };
970
971 static const struct omap3_dpll5_settings precomputed[] = {
972
973
974
975
976
977
978 { 12000000, 80, 0 + 1 },
979 { 13000000, 443, 5 + 1 },
980 { 19200000, 50, 0 + 1 },
981 { 26000000, 443, 11 + 1 },
982 { 38400000, 25, 0 + 1 }
983 };
984
985 const struct omap3_dpll5_settings *d;
986 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
987 struct dpll_data *dd;
988 unsigned int i;
989
990 for (i = 0; i < ARRAY_SIZE(precomputed); ++i) {
991 if (parent_rate == precomputed[i].rate)
992 break;
993 }
994
995 if (i == ARRAY_SIZE(precomputed))
996 return false;
997
998 d = &precomputed[i];
999
1000
1001 dd = clk->dpll_data;
1002 dd->last_rounded_m = d->m;
1003 dd->last_rounded_n = d->n;
1004 dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);
1005 omap3_noncore_dpll_program(clk, 0);
1006
1007 return true;
1008 }
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
1020 unsigned long parent_rate)
1021 {
1022 if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8) {
1023 if (omap3_dpll5_apply_errata(hw, parent_rate))
1024 return 0;
1025 }
1026
1027 return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
1028 }