1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * OMAP2/3/4 DPLL clock functions
4 *
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
7 *
8 * Contacts:
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Paul Walmsley
11 */
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/io.h>
19 #include <linux/clk/ti.h>
20
21 #include <asm/div64.h>
22
23 #include "clock.h"
24
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
26 #define DPLL_MIN_MULTIPLIER 2
27 #define DPLL_MIN_DIVIDER 1
28
29 /* Possible error results from _dpll_test_mult */
30 #define DPLL_MULT_UNDERFLOW -1
31
32 /*
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
34 * The higher the scale factor, the greater the risk of arithmetic overflow,
35 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
36 * must be a power of DPLL_SCALE_BASE.
37 */
38 #define DPLL_SCALE_FACTOR 64
39 #define DPLL_SCALE_BASE 2
40 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
41 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
42
43 /*
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
46 */
47 #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
48 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
49
50 /* _dpll_test_fint() return codes */
51 #define DPLL_FINT_UNDERFLOW -1
52 #define DPLL_FINT_INVALID -2
53
54 /* Private functions */
55
56 /*
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
59 * @n: divider value (N) to test
60 *
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
63 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
64 * (assuming that it is counting N upwards), or -2 if the enclosing loop
65 * should skip to the next iteration (again assuming N is increasing).
66 */
67 static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
68 {
69 struct dpll_data *dd;
70 long fint, fint_min, fint_max;
71 int ret = 0;
72
73 dd = clk->dpll_data;
74
75 /* DPLL divider must result in a valid jitter correction val */
76 fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
77
78 if (dd->flags & DPLL_J_TYPE) {
79 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
80 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
81 } else {
82 fint_min = ti_clk_get_features()->fint_min;
83 fint_max = ti_clk_get_features()->fint_max;
84 }
85
86 if (!fint_min || !fint_max) {
87 WARN(1, "No fint limits available!\n");
88 return DPLL_FINT_INVALID;
89 }
90
91 if (fint < ti_clk_get_features()->fint_min) {
92 pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
93 n);
94 dd->max_divider = n;
95 ret = DPLL_FINT_UNDERFLOW;
96 } else if (fint > ti_clk_get_features()->fint_max) {
97 pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
98 n);
99 dd->min_divider = n;
100 ret = DPLL_FINT_INVALID;
101 } else if (fint > ti_clk_get_features()->fint_band1_max &&
102 fint < ti_clk_get_features()->fint_band2_min) {
103 pr_debug("rejecting n=%d due to Fint failure\n", n);
104 ret = DPLL_FINT_INVALID;
105 }
106
107 return ret;
108 }
109
110 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
111 unsigned int m, unsigned int n)
112 {
113 unsigned long long num;
114
115 num = (unsigned long long)parent_rate * m;
116 do_div(num, n);
117 return num;
118 }
119
120 /*
121 * _dpll_test_mult - test a DPLL multiplier value
122 * @m: pointer to the DPLL m (multiplier) value under test
123 * @n: current DPLL n (divider) value under test
124 * @new_rate: pointer to storage for the resulting rounded rate
125 * @target_rate: the desired DPLL rate
126 * @parent_rate: the DPLL's parent clock rate
127 *
128 * This code tests a DPLL multiplier value, ensuring that the
129 * resulting rate will not be higher than the target_rate, and that
130 * the multiplier value itself is valid for the DPLL. Initially, the
131 * integer pointed to by the m argument should be prescaled by
132 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
133 * a non-scaled m upon return. This non-scaled m will result in a
134 * new_rate as close as possible to target_rate (but not greater than
135 * target_rate) given the current (parent_rate, n, prescaled m)
136 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
137 * non-scaled m attempted to underflow, which can allow the calling
138 * function to bail out early; or 0 upon success.
139 */
140 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
141 unsigned long target_rate,
142 unsigned long parent_rate)
143 {
144 int r = 0, carry = 0;
145
146 /* Unscale m and round if necessary */
147 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
148 carry = 1;
149 *m = (*m / DPLL_SCALE_FACTOR) + carry;
150
151 /*
152 * The new rate must be <= the target rate to avoid programming
153 * a rate that is impossible for the hardware to handle
154 */
155 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
156 if (*new_rate > target_rate) {
157 (*m)--;
158 *new_rate = 0;
159 }
160
161 /* Guard against m underflow */
162 if (*m < DPLL_MIN_MULTIPLIER) {
163 *m = DPLL_MIN_MULTIPLIER;
164 *new_rate = 0;
165 r = DPLL_MULT_UNDERFLOW;
166 }
167
168 if (*new_rate == 0)
169 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
170
171 return r;
172 }
173
174 /**
175 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
176 * @v: bitfield value of the DPLL enable
177 *
178 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
179 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
180 */
181 static int _omap2_dpll_is_in_bypass(u32 v)
182 {
183 u8 mask, val;
184
185 mask = ti_clk_get_features()->dpll_bypass_vals;
186
187 /*
188 * Each set bit in the mask corresponds to a bypass value equal
189 * to the bitshift. Go through each set-bit in the mask and
190 * compare against the given register value.
191 */
192 while (mask) {
193 val = __ffs(mask);
194 mask ^= (1 << val);
195 if (v == val)
196 return 1;
197 }
198
199 return 0;
200 }
201
202 /* Public functions */
203 u8 omap2_init_dpll_parent(struct clk_hw *hw)
204 {
205 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
206 u32 v;
207 struct dpll_data *dd;
208
209 dd = clk->dpll_data;
210 if (!dd)
211 return -EINVAL;
212
213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
214 v &= dd->enable_mask;
215 v >>= __ffs(dd->enable_mask);
216
217 /* Reparent the struct clk in case the dpll is in bypass */
218 if (_omap2_dpll_is_in_bypass(v))
219 return 1;
220
221 return 0;
222 }
223
224 /**
225 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
226 * @clk: struct clk * of a DPLL
227 *
228 * DPLLs can be locked or bypassed - basically, enabled or disabled.
229 * When locked, the DPLL output depends on the M and N values. When
230 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
232 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
233 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
234 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
235 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
236 * if the clock @clk is not a DPLL.
237 */
238 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
239 {
240 u64 dpll_clk;
241 u32 dpll_mult, dpll_div, v;
242 struct dpll_data *dd;
243
244 dd = clk->dpll_data;
245 if (!dd)
246 return 0;
247
248 /* Return bypass rate if DPLL is bypassed */
249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
250 v &= dd->enable_mask;
251 v >>= __ffs(dd->enable_mask);
252
253 if (_omap2_dpll_is_in_bypass(v))
254 return clk_hw_get_rate(dd->clk_bypass);
255
256 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
257 dpll_mult = v & dd->mult_mask;
258 dpll_mult >>= __ffs(dd->mult_mask);
259 dpll_div = v & dd->div1_mask;
260 dpll_div >>= __ffs(dd->div1_mask);
261
262 dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
263 do_div(dpll_clk, dpll_div + 1);
264
265 return dpll_clk;
266 }
267
268 /* DPLL rate rounding code */
269
270 /**
271 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
272 * @clk: struct clk * for a DPLL
273 * @target_rate: desired DPLL clock rate
274 *
275 * Given a DPLL and a desired target rate, round the target rate to a
276 * possible, programmable rate for this DPLL. Attempts to select the
277 * minimum possible n. Stores the computed (m, n) in the DPLL's
278 * dpll_data structure so set_rate() will not need to call this
279 * (expensive) function again. Returns ~0 if the target rate cannot
280 * be rounded, or the rounded rate upon success.
281 */
282 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
283 unsigned long *parent_rate)
284 {
285 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
286 int m, n, r, scaled_max_m;
287 int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
288 unsigned long scaled_rt_rp;
289 unsigned long new_rate = 0;
290 struct dpll_data *dd;
291 unsigned long ref_rate;
292 long delta;
293 long prev_min_delta = LONG_MAX;
294 const char *clk_name;
295
296 if (!clk || !clk->dpll_data)
297 return ~0;
298
299 dd = clk->dpll_data;
300
301 if (dd->max_rate && target_rate > dd->max_rate)
302 target_rate = dd->max_rate;
303
304 ref_rate = clk_hw_get_rate(dd->clk_ref);
305 clk_name = clk_hw_get_name(hw);
306 pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
307 clk_name, target_rate);
308
309 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
310 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
311
312 dd->last_rounded_rate = 0;
313
314 for (n = dd->min_divider; n <= dd->max_divider; n++) {
315 /* Is the (input clk, divider) pair valid for the DPLL? */
316 r = _dpll_test_fint(clk, n);
317 if (r == DPLL_FINT_UNDERFLOW)
318 break;
319 else if (r == DPLL_FINT_INVALID)
320 continue;
321
322 /* Compute the scaled DPLL multiplier, based on the divider */
323 m = scaled_rt_rp * n;
324
325 /*
326 * Since we're counting n up, a m overflow means we
327 * can bail out completely (since as n increases in
328 * the next iteration, there's no way that m can
329 * increase beyond the current m)
330 */
331 if (m > scaled_max_m)
332 break;
333
334 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
335 ref_rate);
336
337 /* m can't be set low enough for this n - try with a larger n */
338 if (r == DPLL_MULT_UNDERFLOW)
339 continue;
340
341 /* skip rates above our target rate */
342 delta = target_rate - new_rate;
343 if (delta < 0)
344 continue;
345
346 if (delta < prev_min_delta) {
347 prev_min_delta = delta;
348 min_delta_m = m;
349 min_delta_n = n;
350 }
351
352 pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
353 clk_name, m, n, new_rate);
354
355 if (delta == 0)
356 break;
357 }
358
359 if (prev_min_delta == LONG_MAX) {
360 pr_debug("clock: %s: cannot round to rate %lu\n",
361 clk_name, target_rate);
362 return ~0;
363 }
364
365 dd->last_rounded_m = min_delta_m;
366 dd->last_rounded_n = min_delta_n;
367 dd->last_rounded_rate = target_rate - prev_min_delta;
368
369 return dd->last_rounded_rate;
370 }