This source file includes following definitions.
- clk_pllv3_wait_lock
- clk_pllv3_prepare
- clk_pllv3_unprepare
- clk_pllv3_is_prepared
- clk_pllv3_recalc_rate
- clk_pllv3_round_rate
- clk_pllv3_set_rate
- clk_pllv3_sys_recalc_rate
- clk_pllv3_sys_round_rate
- clk_pllv3_sys_set_rate
- clk_pllv3_av_recalc_rate
- clk_pllv3_av_round_rate
- clk_pllv3_av_set_rate
- clk_pllv3_vf610_mf_to_rate
- clk_pllv3_vf610_rate_to_mf
- clk_pllv3_vf610_recalc_rate
- clk_pllv3_vf610_round_rate
- clk_pllv3_vf610_set_rate
- clk_pllv3_enet_recalc_rate
- imx_clk_hw_pllv3
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7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/io.h>
10 #include <linux/slab.h>
11 #include <linux/jiffies.h>
12 #include <linux/err.h>
13 #include "clk.h"
14
15 #define PLL_NUM_OFFSET 0x10
16 #define PLL_DENOM_OFFSET 0x20
17 #define PLL_IMX7_NUM_OFFSET 0x20
18 #define PLL_IMX7_DENOM_OFFSET 0x30
19
20 #define PLL_VF610_NUM_OFFSET 0x20
21 #define PLL_VF610_DENOM_OFFSET 0x30
22
23 #define BM_PLL_POWER (0x1 << 12)
24 #define BM_PLL_LOCK (0x1 << 31)
25 #define IMX7_ENET_PLL_POWER (0x1 << 5)
26 #define IMX7_DDR_PLL_POWER (0x1 << 20)
27
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38
39
40 struct clk_pllv3 {
41 struct clk_hw hw;
42 void __iomem *base;
43 u32 power_bit;
44 bool powerup_set;
45 u32 div_mask;
46 u32 div_shift;
47 unsigned long ref_clock;
48 u32 num_offset;
49 u32 denom_offset;
50 };
51
52 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
53
54 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
55 {
56 unsigned long timeout = jiffies + msecs_to_jiffies(10);
57 u32 val = readl_relaxed(pll->base) & pll->power_bit;
58
59
60 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
61 return 0;
62
63
64 do {
65 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
66 break;
67 if (time_after(jiffies, timeout))
68 break;
69 usleep_range(50, 500);
70 } while (1);
71
72 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
73 }
74
75 static int clk_pllv3_prepare(struct clk_hw *hw)
76 {
77 struct clk_pllv3 *pll = to_clk_pllv3(hw);
78 u32 val;
79
80 val = readl_relaxed(pll->base);
81 if (pll->powerup_set)
82 val |= pll->power_bit;
83 else
84 val &= ~pll->power_bit;
85 writel_relaxed(val, pll->base);
86
87 return clk_pllv3_wait_lock(pll);
88 }
89
90 static void clk_pllv3_unprepare(struct clk_hw *hw)
91 {
92 struct clk_pllv3 *pll = to_clk_pllv3(hw);
93 u32 val;
94
95 val = readl_relaxed(pll->base);
96 if (pll->powerup_set)
97 val &= ~pll->power_bit;
98 else
99 val |= pll->power_bit;
100 writel_relaxed(val, pll->base);
101 }
102
103 static int clk_pllv3_is_prepared(struct clk_hw *hw)
104 {
105 struct clk_pllv3 *pll = to_clk_pllv3(hw);
106
107 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
108 return 1;
109
110 return 0;
111 }
112
113 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
114 unsigned long parent_rate)
115 {
116 struct clk_pllv3 *pll = to_clk_pllv3(hw);
117 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
118
119 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
120 }
121
122 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
123 unsigned long *prate)
124 {
125 unsigned long parent_rate = *prate;
126
127 return (rate >= parent_rate * 22) ? parent_rate * 22 :
128 parent_rate * 20;
129 }
130
131 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long parent_rate)
133 {
134 struct clk_pllv3 *pll = to_clk_pllv3(hw);
135 u32 val, div;
136
137 if (rate == parent_rate * 22)
138 div = 1;
139 else if (rate == parent_rate * 20)
140 div = 0;
141 else
142 return -EINVAL;
143
144 val = readl_relaxed(pll->base);
145 val &= ~(pll->div_mask << pll->div_shift);
146 val |= (div << pll->div_shift);
147 writel_relaxed(val, pll->base);
148
149 return clk_pllv3_wait_lock(pll);
150 }
151
152 static const struct clk_ops clk_pllv3_ops = {
153 .prepare = clk_pllv3_prepare,
154 .unprepare = clk_pllv3_unprepare,
155 .is_prepared = clk_pllv3_is_prepared,
156 .recalc_rate = clk_pllv3_recalc_rate,
157 .round_rate = clk_pllv3_round_rate,
158 .set_rate = clk_pllv3_set_rate,
159 };
160
161 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
162 unsigned long parent_rate)
163 {
164 struct clk_pllv3 *pll = to_clk_pllv3(hw);
165 u32 div = readl_relaxed(pll->base) & pll->div_mask;
166
167 return parent_rate * div / 2;
168 }
169
170 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
171 unsigned long *prate)
172 {
173 unsigned long parent_rate = *prate;
174 unsigned long min_rate = parent_rate * 54 / 2;
175 unsigned long max_rate = parent_rate * 108 / 2;
176 u32 div;
177
178 if (rate > max_rate)
179 rate = max_rate;
180 else if (rate < min_rate)
181 rate = min_rate;
182 div = rate * 2 / parent_rate;
183
184 return parent_rate * div / 2;
185 }
186
187 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
188 unsigned long parent_rate)
189 {
190 struct clk_pllv3 *pll = to_clk_pllv3(hw);
191 unsigned long min_rate = parent_rate * 54 / 2;
192 unsigned long max_rate = parent_rate * 108 / 2;
193 u32 val, div;
194
195 if (rate < min_rate || rate > max_rate)
196 return -EINVAL;
197
198 div = rate * 2 / parent_rate;
199 val = readl_relaxed(pll->base);
200 val &= ~pll->div_mask;
201 val |= div;
202 writel_relaxed(val, pll->base);
203
204 return clk_pllv3_wait_lock(pll);
205 }
206
207 static const struct clk_ops clk_pllv3_sys_ops = {
208 .prepare = clk_pllv3_prepare,
209 .unprepare = clk_pllv3_unprepare,
210 .is_prepared = clk_pllv3_is_prepared,
211 .recalc_rate = clk_pllv3_sys_recalc_rate,
212 .round_rate = clk_pllv3_sys_round_rate,
213 .set_rate = clk_pllv3_sys_set_rate,
214 };
215
216 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
217 unsigned long parent_rate)
218 {
219 struct clk_pllv3 *pll = to_clk_pllv3(hw);
220 u32 mfn = readl_relaxed(pll->base + pll->num_offset);
221 u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
222 u32 div = readl_relaxed(pll->base) & pll->div_mask;
223 u64 temp64 = (u64)parent_rate;
224
225 temp64 *= mfn;
226 do_div(temp64, mfd);
227
228 return parent_rate * div + (unsigned long)temp64;
229 }
230
231 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
232 unsigned long *prate)
233 {
234 unsigned long parent_rate = *prate;
235 unsigned long min_rate = parent_rate * 27;
236 unsigned long max_rate = parent_rate * 54;
237 u32 div;
238 u32 mfn, mfd = 1000000;
239 u32 max_mfd = 0x3FFFFFFF;
240 u64 temp64;
241
242 if (rate > max_rate)
243 rate = max_rate;
244 else if (rate < min_rate)
245 rate = min_rate;
246
247 if (parent_rate <= max_mfd)
248 mfd = parent_rate;
249
250 div = rate / parent_rate;
251 temp64 = (u64) (rate - div * parent_rate);
252 temp64 *= mfd;
253 do_div(temp64, parent_rate);
254 mfn = temp64;
255
256 temp64 = (u64)parent_rate;
257 temp64 *= mfn;
258 do_div(temp64, mfd);
259
260 return parent_rate * div + (unsigned long)temp64;
261 }
262
263 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
264 unsigned long parent_rate)
265 {
266 struct clk_pllv3 *pll = to_clk_pllv3(hw);
267 unsigned long min_rate = parent_rate * 27;
268 unsigned long max_rate = parent_rate * 54;
269 u32 val, div;
270 u32 mfn, mfd = 1000000;
271 u32 max_mfd = 0x3FFFFFFF;
272 u64 temp64;
273
274 if (rate < min_rate || rate > max_rate)
275 return -EINVAL;
276
277 if (parent_rate <= max_mfd)
278 mfd = parent_rate;
279
280 div = rate / parent_rate;
281 temp64 = (u64) (rate - div * parent_rate);
282 temp64 *= mfd;
283 do_div(temp64, parent_rate);
284 mfn = temp64;
285
286 val = readl_relaxed(pll->base);
287 val &= ~pll->div_mask;
288 val |= div;
289 writel_relaxed(val, pll->base);
290 writel_relaxed(mfn, pll->base + pll->num_offset);
291 writel_relaxed(mfd, pll->base + pll->denom_offset);
292
293 return clk_pllv3_wait_lock(pll);
294 }
295
296 static const struct clk_ops clk_pllv3_av_ops = {
297 .prepare = clk_pllv3_prepare,
298 .unprepare = clk_pllv3_unprepare,
299 .is_prepared = clk_pllv3_is_prepared,
300 .recalc_rate = clk_pllv3_av_recalc_rate,
301 .round_rate = clk_pllv3_av_round_rate,
302 .set_rate = clk_pllv3_av_set_rate,
303 };
304
305 struct clk_pllv3_vf610_mf {
306 u32 mfi;
307 u32 mfn;
308 u32 mfd;
309 };
310
311 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
312 struct clk_pllv3_vf610_mf mf)
313 {
314 u64 temp64;
315
316 temp64 = parent_rate;
317 temp64 *= mf.mfn;
318 do_div(temp64, mf.mfd);
319
320 return (parent_rate * mf.mfi) + temp64;
321 }
322
323 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
324 unsigned long parent_rate, unsigned long rate)
325 {
326 struct clk_pllv3_vf610_mf mf;
327 u64 temp64;
328
329 mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
330 mf.mfd = 0x3fffffff;
331
332 if (rate <= parent_rate * mf.mfi)
333 mf.mfn = 0;
334 else if (rate >= parent_rate * (mf.mfi + 1))
335 mf.mfn = mf.mfd - 1;
336 else {
337
338 temp64 = rate - parent_rate * mf.mfi;
339 temp64 *= mf.mfd;
340 do_div(temp64, parent_rate);
341 mf.mfn = temp64;
342 }
343
344 return mf;
345 }
346
347 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
348 unsigned long parent_rate)
349 {
350 struct clk_pllv3 *pll = to_clk_pllv3(hw);
351 struct clk_pllv3_vf610_mf mf;
352
353 mf.mfn = readl_relaxed(pll->base + pll->num_offset);
354 mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
355 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
356
357 return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
358 }
359
360 static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
361 unsigned long *prate)
362 {
363 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
364
365 return clk_pllv3_vf610_mf_to_rate(*prate, mf);
366 }
367
368 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
369 unsigned long parent_rate)
370 {
371 struct clk_pllv3 *pll = to_clk_pllv3(hw);
372 struct clk_pllv3_vf610_mf mf =
373 clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
374 u32 val;
375
376 val = readl_relaxed(pll->base);
377 if (mf.mfi == 20)
378 val &= ~pll->div_mask;
379 else
380 val |= pll->div_mask;
381 writel_relaxed(val, pll->base);
382
383 writel_relaxed(mf.mfn, pll->base + pll->num_offset);
384 writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
385
386 return clk_pllv3_wait_lock(pll);
387 }
388
389 static const struct clk_ops clk_pllv3_vf610_ops = {
390 .prepare = clk_pllv3_prepare,
391 .unprepare = clk_pllv3_unprepare,
392 .is_prepared = clk_pllv3_is_prepared,
393 .recalc_rate = clk_pllv3_vf610_recalc_rate,
394 .round_rate = clk_pllv3_vf610_round_rate,
395 .set_rate = clk_pllv3_vf610_set_rate,
396 };
397
398 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
399 unsigned long parent_rate)
400 {
401 struct clk_pllv3 *pll = to_clk_pllv3(hw);
402
403 return pll->ref_clock;
404 }
405
406 static const struct clk_ops clk_pllv3_enet_ops = {
407 .prepare = clk_pllv3_prepare,
408 .unprepare = clk_pllv3_unprepare,
409 .is_prepared = clk_pllv3_is_prepared,
410 .recalc_rate = clk_pllv3_enet_recalc_rate,
411 };
412
413 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
414 const char *parent_name, void __iomem *base,
415 u32 div_mask)
416 {
417 struct clk_pllv3 *pll;
418 const struct clk_ops *ops;
419 struct clk_hw *hw;
420 struct clk_init_data init;
421 int ret;
422
423 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
424 if (!pll)
425 return ERR_PTR(-ENOMEM);
426
427 pll->power_bit = BM_PLL_POWER;
428 pll->num_offset = PLL_NUM_OFFSET;
429 pll->denom_offset = PLL_DENOM_OFFSET;
430
431 switch (type) {
432 case IMX_PLLV3_SYS:
433 ops = &clk_pllv3_sys_ops;
434 break;
435 case IMX_PLLV3_SYS_VF610:
436 ops = &clk_pllv3_vf610_ops;
437 pll->num_offset = PLL_VF610_NUM_OFFSET;
438 pll->denom_offset = PLL_VF610_DENOM_OFFSET;
439 break;
440 case IMX_PLLV3_USB_VF610:
441 pll->div_shift = 1;
442
443 case IMX_PLLV3_USB:
444 ops = &clk_pllv3_ops;
445 pll->powerup_set = true;
446 break;
447 case IMX_PLLV3_AV_IMX7:
448 pll->num_offset = PLL_IMX7_NUM_OFFSET;
449 pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
450
451 case IMX_PLLV3_AV:
452 ops = &clk_pllv3_av_ops;
453 break;
454 case IMX_PLLV3_ENET_IMX7:
455 pll->power_bit = IMX7_ENET_PLL_POWER;
456 pll->ref_clock = 1000000000;
457 ops = &clk_pllv3_enet_ops;
458 break;
459 case IMX_PLLV3_ENET:
460 pll->ref_clock = 500000000;
461 ops = &clk_pllv3_enet_ops;
462 break;
463 case IMX_PLLV3_DDR_IMX7:
464 pll->power_bit = IMX7_DDR_PLL_POWER;
465 pll->num_offset = PLL_IMX7_NUM_OFFSET;
466 pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
467 ops = &clk_pllv3_av_ops;
468 break;
469 default:
470 ops = &clk_pllv3_ops;
471 }
472 pll->base = base;
473 pll->div_mask = div_mask;
474
475 init.name = name;
476 init.ops = ops;
477 init.flags = 0;
478 init.parent_names = &parent_name;
479 init.num_parents = 1;
480
481 pll->hw.init = &init;
482 hw = &pll->hw;
483
484 ret = clk_hw_register(NULL, hw);
485 if (ret) {
486 kfree(pll);
487 return ERR_PTR(ret);
488 }
489
490 return hw;
491 }