This source file includes following definitions.
- sam9x60_pmc_setup
1
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
5
6 #include <dt-bindings/clock/at91.h>
7
8 #include "pmc.h"
9
10 static DEFINE_SPINLOCK(pmc_pll_lock);
11
12 static const struct clk_master_characteristics mck_characteristics = {
13 .output = { .min = 140000000, .max = 200000000 },
14 .divisors = { 1, 2, 4, 3 },
15 .have_div3_pres = 1,
16 };
17
18 static const struct clk_master_layout sam9x60_master_layout = {
19 .mask = 0x373,
20 .pres_shift = 4,
21 .offset = 0x28,
22 };
23
24 static const struct clk_range plla_outputs[] = {
25 { .min = 300000000, .max = 600000000 },
26 };
27
28 static const struct clk_pll_characteristics plla_characteristics = {
29 .input = { .min = 12000000, .max = 48000000 },
30 .num_output = ARRAY_SIZE(plla_outputs),
31 .output = plla_outputs,
32 };
33
34 static const struct clk_range upll_outputs[] = {
35 { .min = 300000000, .max = 500000000 },
36 };
37
38 static const struct clk_pll_characteristics upll_characteristics = {
39 .input = { .min = 12000000, .max = 48000000 },
40 .num_output = ARRAY_SIZE(upll_outputs),
41 .output = upll_outputs,
42 .upll = true,
43 };
44
45 static const struct clk_programmable_layout sam9x60_programmable_layout = {
46 .pres_mask = 0xff,
47 .pres_shift = 8,
48 .css_mask = 0x1f,
49 .have_slck_mck = 0,
50 .is_pres_direct = 1,
51 };
52
53 static const struct clk_pcr_layout sam9x60_pcr_layout = {
54 .offset = 0x88,
55 .cmd = BIT(31),
56 .gckcss_mask = GENMASK(12, 8),
57 .pid_mask = GENMASK(6, 0),
58 };
59
60 static const struct {
61 char *n;
62 char *p;
63 u8 id;
64 } sam9x60_systemck[] = {
65 { .n = "ddrck", .p = "masterck", .id = 2 },
66 { .n = "uhpck", .p = "usbck", .id = 6 },
67 { .n = "pck0", .p = "prog0", .id = 8 },
68 { .n = "pck1", .p = "prog1", .id = 9 },
69 { .n = "qspick", .p = "masterck", .id = 19 },
70 };
71
72 static const struct {
73 char *n;
74 u8 id;
75 } sam9x60_periphck[] = {
76 { .n = "pioA_clk", .id = 2, },
77 { .n = "pioB_clk", .id = 3, },
78 { .n = "pioC_clk", .id = 4, },
79 { .n = "flex0_clk", .id = 5, },
80 { .n = "flex1_clk", .id = 6, },
81 { .n = "flex2_clk", .id = 7, },
82 { .n = "flex3_clk", .id = 8, },
83 { .n = "flex6_clk", .id = 9, },
84 { .n = "flex7_clk", .id = 10, },
85 { .n = "flex8_clk", .id = 11, },
86 { .n = "sdmmc0_clk", .id = 12, },
87 { .n = "flex4_clk", .id = 13, },
88 { .n = "flex5_clk", .id = 14, },
89 { .n = "flex9_clk", .id = 15, },
90 { .n = "flex10_clk", .id = 16, },
91 { .n = "tcb0_clk", .id = 17, },
92 { .n = "pwm_clk", .id = 18, },
93 { .n = "adc_clk", .id = 19, },
94 { .n = "dma0_clk", .id = 20, },
95 { .n = "matrix_clk", .id = 21, },
96 { .n = "uhphs_clk", .id = 22, },
97 { .n = "udphs_clk", .id = 23, },
98 { .n = "macb0_clk", .id = 24, },
99 { .n = "lcd_clk", .id = 25, },
100 { .n = "sdmmc1_clk", .id = 26, },
101 { .n = "macb1_clk", .id = 27, },
102 { .n = "ssc_clk", .id = 28, },
103 { .n = "can0_clk", .id = 29, },
104 { .n = "can1_clk", .id = 30, },
105 { .n = "flex11_clk", .id = 32, },
106 { .n = "flex12_clk", .id = 33, },
107 { .n = "i2s_clk", .id = 34, },
108 { .n = "qspi_clk", .id = 35, },
109 { .n = "gfx2d_clk", .id = 36, },
110 { .n = "pit64b_clk", .id = 37, },
111 { .n = "trng_clk", .id = 38, },
112 { .n = "aes_clk", .id = 39, },
113 { .n = "tdes_clk", .id = 40, },
114 { .n = "sha_clk", .id = 41, },
115 { .n = "classd_clk", .id = 42, },
116 { .n = "isi_clk", .id = 43, },
117 { .n = "pioD_clk", .id = 44, },
118 { .n = "tcb1_clk", .id = 45, },
119 { .n = "dbgu_clk", .id = 47, },
120 { .n = "mpddr_clk", .id = 49, },
121 };
122
123 static const struct {
124 char *n;
125 u8 id;
126 struct clk_range r;
127 bool pll;
128 } sam9x60_gck[] = {
129 { .n = "flex0_gclk", .id = 5, },
130 { .n = "flex1_gclk", .id = 6, },
131 { .n = "flex2_gclk", .id = 7, },
132 { .n = "flex3_gclk", .id = 8, },
133 { .n = "flex6_gclk", .id = 9, },
134 { .n = "flex7_gclk", .id = 10, },
135 { .n = "flex8_gclk", .id = 11, },
136 { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },
137 { .n = "flex4_gclk", .id = 13, },
138 { .n = "flex5_gclk", .id = 14, },
139 { .n = "flex9_gclk", .id = 15, },
140 { .n = "flex10_gclk", .id = 16, },
141 { .n = "tcb0_gclk", .id = 17, },
142 { .n = "adc_gclk", .id = 19, },
143 { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, },
144 { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },
145 { .n = "flex11_gclk", .id = 32, },
146 { .n = "flex12_gclk", .id = 33, },
147 { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 },
148 .pll = true, },
149 { .n = "pit64b_gclk", .id = 37, },
150 { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 },
151 .pll = true, },
152 { .n = "tcb1_gclk", .id = 45, },
153 { .n = "dbgu_gclk", .id = 47, },
154 };
155
156 static void __init sam9x60_pmc_setup(struct device_node *np)
157 {
158 struct clk_range range = CLK_RANGE(0, 0);
159 const char *td_slck_name, *md_slck_name, *mainxtal_name;
160 struct pmc_data *sam9x60_pmc;
161 const char *parent_names[6];
162 struct regmap *regmap;
163 struct clk_hw *hw;
164 int i;
165 bool bypass;
166
167 i = of_property_match_string(np, "clock-names", "td_slck");
168 if (i < 0)
169 return;
170
171 td_slck_name = of_clk_get_parent_name(np, i);
172
173 i = of_property_match_string(np, "clock-names", "md_slck");
174 if (i < 0)
175 return;
176
177 md_slck_name = of_clk_get_parent_name(np, i);
178
179 i = of_property_match_string(np, "clock-names", "main_xtal");
180 if (i < 0)
181 return;
182 mainxtal_name = of_clk_get_parent_name(np, i);
183
184 regmap = syscon_node_to_regmap(np);
185 if (IS_ERR(regmap))
186 return;
187
188 sam9x60_pmc = pmc_data_allocate(PMC_MAIN + 1,
189 nck(sam9x60_systemck),
190 nck(sam9x60_periphck),
191 nck(sam9x60_gck));
192 if (!sam9x60_pmc)
193 return;
194
195 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 24000000,
196 50000000);
197 if (IS_ERR(hw))
198 goto err_free;
199
200 bypass = of_property_read_bool(np, "atmel,osc-bypass");
201
202 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
203 bypass);
204 if (IS_ERR(hw))
205 goto err_free;
206
207 parent_names[0] = "main_rc_osc";
208 parent_names[1] = "main_osc";
209 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
210 if (IS_ERR(hw))
211 goto err_free;
212
213 sam9x60_pmc->chws[PMC_MAIN] = hw;
214
215 hw = sam9x60_clk_register_pll(regmap, &pmc_pll_lock, "pllack",
216 "mainck", 0, &plla_characteristics);
217 if (IS_ERR(hw))
218 goto err_free;
219
220 hw = sam9x60_clk_register_pll(regmap, &pmc_pll_lock, "upllck",
221 "main_osc", 1, &upll_characteristics);
222 if (IS_ERR(hw))
223 goto err_free;
224
225 sam9x60_pmc->chws[PMC_UTMI] = hw;
226
227 parent_names[0] = md_slck_name;
228 parent_names[1] = "mainck";
229 parent_names[2] = "pllack";
230 hw = at91_clk_register_master(regmap, "masterck", 3, parent_names,
231 &sam9x60_master_layout,
232 &mck_characteristics);
233 if (IS_ERR(hw))
234 goto err_free;
235
236 sam9x60_pmc->chws[PMC_MCK] = hw;
237
238 parent_names[0] = "pllack";
239 parent_names[1] = "upllck";
240 parent_names[2] = "main_osc";
241 hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
242 if (IS_ERR(hw))
243 goto err_free;
244
245 parent_names[0] = md_slck_name;
246 parent_names[1] = td_slck_name;
247 parent_names[2] = "mainck";
248 parent_names[3] = "masterck";
249 parent_names[4] = "pllack";
250 parent_names[5] = "upllck";
251 for (i = 0; i < 8; i++) {
252 char name[6];
253
254 snprintf(name, sizeof(name), "prog%d", i);
255
256 hw = at91_clk_register_programmable(regmap, name,
257 parent_names, 6, i,
258 &sam9x60_programmable_layout);
259 if (IS_ERR(hw))
260 goto err_free;
261 }
262
263 for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
264 hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,
265 sam9x60_systemck[i].p,
266 sam9x60_systemck[i].id);
267 if (IS_ERR(hw))
268 goto err_free;
269
270 sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw;
271 }
272
273 for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
274 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
275 &sam9x60_pcr_layout,
276 sam9x60_periphck[i].n,
277 "masterck",
278 sam9x60_periphck[i].id,
279 &range);
280 if (IS_ERR(hw))
281 goto err_free;
282
283 sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw;
284 }
285
286 for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
287 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
288 &sam9x60_pcr_layout,
289 sam9x60_gck[i].n,
290 parent_names, 6,
291 sam9x60_gck[i].id,
292 sam9x60_gck[i].pll,
293 &sam9x60_gck[i].r);
294 if (IS_ERR(hw))
295 goto err_free;
296
297 sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw;
298 }
299
300 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc);
301
302 return;
303
304 err_free:
305 pmc_data_free(sam9x60_pmc);
306 }
307
308 CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);