1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Structures used by ASPEED clock drivers
4 *
5 * Copyright 2019 IBM Corp.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/kernel.h>
10 #include <linux/reset-controller.h>
11 #include <linux/spinlock.h>
12
13 struct clk_div_table;
14 struct regmap;
15
16 /**
17 * struct aspeed_gate_data - Aspeed gated clocks
18 * @clock_idx: bit used to gate this clock in the clock register
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
20 * reset is required when enabling the clock
21 * @name: the clock name
22 * @parent_name: the name of the parent clock
23 * @flags: standard clock framework flags
24 */
25 struct aspeed_gate_data {
26 u8 clock_idx;
27 s8 reset_idx;
28 const char *name;
29 const char *parent_name;
30 unsigned long flags;
31 };
32
33 /**
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
36 * @reg: register controlling gate
37 * @clock_idx: bit used to gate this clock in the clock register
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
39 * reset is required when enabling the clock
40 * @flags: hardware-specific flags
41 * @lock: register lock
42 *
43 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
44 * This modified version of clk_gate allows an optional reset bit to be
45 * specified.
46 */
47 struct aspeed_clk_gate {
48 struct clk_hw hw;
49 struct regmap *map;
50 u8 clock_idx;
51 s8 reset_idx;
52 u8 flags;
53 spinlock_t *lock;
54 };
55
56 #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
57
58 /**
59 * struct aspeed_reset - Aspeed reset controller
60 * @map: regmap to access the containing system controller
61 * @rcdev: reset controller device
62 */
63 struct aspeed_reset {
64 struct regmap *map;
65 struct reset_controller_dev rcdev;
66 };
67
68 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
69
70 /**
71 * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
72 * @div_table: Common divider lookup table
73 * @eclk_div_table: Divider lookup table for ECLK
74 * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
75 * @calc_pll: Callback to maculate common PLL settings
76 */
77 struct aspeed_clk_soc_data {
78 const struct clk_div_table *div_table;
79 const struct clk_div_table *eclk_div_table;
80 const struct clk_div_table *mac_div_table;
81 struct clk_hw *(*calc_pll)(const char *name, u32 val);
82 };