drivers/clk/qcom/gdsc.c

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This source file includes following definitions.
gdsc_check_status
gdsc_hwctrl
gdsc_poll_status
gdsc_toggle_logic
gdsc_deassert_reset
gdsc_assert_reset
gdsc_force_mem_on
gdsc_clear_mem_on
gdsc_deassert_clamp_io
gdsc_assert_clamp_io
gdsc_assert_reset_aon
gdsc_enable
gdsc_disable
gdsc_init
gdsc_register
gdsc_unregister
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
   4  */
   5 
   6 #include <linux/bitops.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/jiffies.h>
  10 #include <linux/kernel.h>
  11 #include <linux/ktime.h>
  12 #include <linux/pm_domain.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset-controller.h>
  15 #include <linux/slab.h>
  16 #include "gdsc.h"
  17 
  18 #define PWR_ON_MASK             BIT(31)
  19 #define EN_REST_WAIT_MASK       GENMASK_ULL(23, 20)
  20 #define EN_FEW_WAIT_MASK        GENMASK_ULL(19, 16)
  21 #define CLK_DIS_WAIT_MASK       GENMASK_ULL(15, 12)
  22 #define SW_OVERRIDE_MASK        BIT(2)
  23 #define HW_CONTROL_MASK         BIT(1)
  24 #define SW_COLLAPSE_MASK        BIT(0)
  25 #define GMEM_CLAMP_IO_MASK      BIT(0)
  26 #define GMEM_RESET_MASK         BIT(4)
  27 
  28 /* CFG_GDSCR */
  29 #define GDSC_POWER_UP_COMPLETE          BIT(16)
  30 #define GDSC_POWER_DOWN_COMPLETE        BIT(15)
  31 #define CFG_GDSCR_OFFSET                0x4
  32 
  33 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
  34 #define EN_REST_WAIT_VAL        (0x2 << 20)
  35 #define EN_FEW_WAIT_VAL         (0x8 << 16)
  36 #define CLK_DIS_WAIT_VAL        (0x2 << 12)
  37 
  38 #define RETAIN_MEM              BIT(14)
  39 #define RETAIN_PERIPH           BIT(13)
  40 
  41 #define TIMEOUT_US              500
  42 
  43 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  44 
  45 enum gdsc_status {
  46         GDSC_OFF,
  47         GDSC_ON
  48 };
  49 
  50 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
  51 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
  52 {
  53         unsigned int reg;
  54         u32 val;
  55         int ret;
  56 
  57         if (sc->flags & POLL_CFG_GDSCR)
  58                 reg = sc->gdscr + CFG_GDSCR_OFFSET;
  59         else if (sc->gds_hw_ctrl)
  60                 reg = sc->gds_hw_ctrl;
  61         else
  62                 reg = sc->gdscr;
  63 
  64         ret = regmap_read(sc->regmap, reg, &val);
  65         if (ret)
  66                 return ret;
  67 
  68         if (sc->flags & POLL_CFG_GDSCR) {
  69                 switch (status) {
  70                 case GDSC_ON:
  71                         return !!(val & GDSC_POWER_UP_COMPLETE);
  72                 case GDSC_OFF:
  73                         return !!(val & GDSC_POWER_DOWN_COMPLETE);
  74                 }
  75         }
  76 
  77         switch (status) {
  78         case GDSC_ON:
  79                 return !!(val & PWR_ON_MASK);
  80         case GDSC_OFF:
  81                 return !(val & PWR_ON_MASK);
  82         }
  83 
  84         return -EINVAL;
  85 }
  86 
  87 static int gdsc_hwctrl(struct gdsc *sc, bool en)
  88 {
  89         u32 val = en ? HW_CONTROL_MASK : 0;
  90 
  91         return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
  92 }
  93 
  94 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
  95 {
  96         ktime_t start;
  97 
  98         start = ktime_get();
  99         do {
 100                 if (gdsc_check_status(sc, status))
 101                         return 0;
 102         } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 103 
 104         if (gdsc_check_status(sc, status))
 105                 return 0;
 106 
 107         return -ETIMEDOUT;
 108 }
 109 
 110 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
 111 {
 112         int ret;
 113         u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
 114 
 115         ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
 116         if (ret)
 117                 return ret;
 118 
 119         /* If disabling votable gdscs, don't poll on status */
 120         if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
 121                 /*
 122                  * Add a short delay here to ensure that an enable
 123                  * right after it was disabled does not put it in an
 124                  * unknown state
 125                  */
 126                 udelay(TIMEOUT_US);
 127                 return 0;
 128         }
 129 
 130         if (sc->gds_hw_ctrl) {
 131                 /*
 132                  * The gds hw controller asserts/de-asserts the status bit soon
 133                  * after it receives a power on/off request from a master.
 134                  * The controller then takes around 8 xo cycles to start its
 135                  * internal state machine and update the status bit. During
 136                  * this time, the status bit does not reflect the true status
 137                  * of the core.
 138                  * Add a delay of 1 us between writing to the SW_COLLAPSE bit
 139                  * and polling the status bit.
 140                  */
 141                 udelay(1);
 142         }
 143 
 144         ret = gdsc_poll_status(sc, status);
 145         WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
 146         return ret;
 147 }
 148 
 149 static inline int gdsc_deassert_reset(struct gdsc *sc)
 150 {
 151         int i;
 152 
 153         for (i = 0; i < sc->reset_count; i++)
 154                 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
 155         return 0;
 156 }
 157 
 158 static inline int gdsc_assert_reset(struct gdsc *sc)
 159 {
 160         int i;
 161 
 162         for (i = 0; i < sc->reset_count; i++)
 163                 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
 164         return 0;
 165 }
 166 
 167 static inline void gdsc_force_mem_on(struct gdsc *sc)
 168 {
 169         int i;
 170         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 171 
 172         for (i = 0; i < sc->cxc_count; i++)
 173                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
 174 }
 175 
 176 static inline void gdsc_clear_mem_on(struct gdsc *sc)
 177 {
 178         int i;
 179         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 180 
 181         for (i = 0; i < sc->cxc_count; i++)
 182                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
 183 }
 184 
 185 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
 186 {
 187         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 188                            GMEM_CLAMP_IO_MASK, 0);
 189 }
 190 
 191 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
 192 {
 193         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 194                            GMEM_CLAMP_IO_MASK, 1);
 195 }
 196 
 197 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
 198 {
 199         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 200                            GMEM_RESET_MASK, 1);
 201         udelay(1);
 202         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 203                            GMEM_RESET_MASK, 0);
 204 }
 205 static int gdsc_enable(struct generic_pm_domain *domain)
 206 {
 207         struct gdsc *sc = domain_to_gdsc(domain);
 208         int ret;
 209 
 210         if (sc->pwrsts == PWRSTS_ON)
 211                 return gdsc_deassert_reset(sc);
 212 
 213         if (sc->flags & SW_RESET) {
 214                 gdsc_assert_reset(sc);
 215                 udelay(1);
 216                 gdsc_deassert_reset(sc);
 217         }
 218 
 219         if (sc->flags & CLAMP_IO) {
 220                 if (sc->flags & AON_RESET)
 221                         gdsc_assert_reset_aon(sc);
 222                 gdsc_deassert_clamp_io(sc);
 223         }
 224 
 225         ret = gdsc_toggle_logic(sc, GDSC_ON);
 226         if (ret)
 227                 return ret;
 228 
 229         if (sc->pwrsts & PWRSTS_OFF)
 230                 gdsc_force_mem_on(sc);
 231 
 232         /*
 233          * If clocks to this power domain were already on, they will take an
 234          * additional 4 clock cycles to re-enable after the power domain is
 235          * enabled. Delay to account for this. A delay is also needed to ensure
 236          * clocks are not enabled within 400ns of enabling power to the
 237          * memories.
 238          */
 239         udelay(1);
 240 
 241         /* Turn on HW trigger mode if supported */
 242         if (sc->flags & HW_CTRL) {
 243                 ret = gdsc_hwctrl(sc, true);
 244                 if (ret)
 245                         return ret;
 246                 /*
 247                  * Wait for the GDSC to go through a power down and
 248                  * up cycle.  In case a firmware ends up polling status
 249                  * bits for the gdsc, it might read an 'on' status before
 250                  * the GDSC can finish the power cycle.
 251                  * We wait 1us before returning to ensure the firmware
 252                  * can't immediately poll the status bits.
 253                  */
 254                 udelay(1);
 255         }
 256 
 257         return 0;
 258 }
 259 
 260 static int gdsc_disable(struct generic_pm_domain *domain)
 261 {
 262         struct gdsc *sc = domain_to_gdsc(domain);
 263         int ret;
 264 
 265         if (sc->pwrsts == PWRSTS_ON)
 266                 return gdsc_assert_reset(sc);
 267 
 268         /* Turn off HW trigger mode if supported */
 269         if (sc->flags & HW_CTRL) {
 270                 ret = gdsc_hwctrl(sc, false);
 271                 if (ret < 0)
 272                         return ret;
 273                 /*
 274                  * Wait for the GDSC to go through a power down and
 275                  * up cycle.  In case we end up polling status
 276                  * bits for the gdsc before the power cycle is completed
 277                  * it might read an 'on' status wrongly.
 278                  */
 279                 udelay(1);
 280 
 281                 ret = gdsc_poll_status(sc, GDSC_ON);
 282                 if (ret)
 283                         return ret;
 284         }
 285 
 286         if (sc->pwrsts & PWRSTS_OFF)
 287                 gdsc_clear_mem_on(sc);
 288 
 289         ret = gdsc_toggle_logic(sc, GDSC_OFF);
 290         if (ret)
 291                 return ret;
 292 
 293         if (sc->flags & CLAMP_IO)
 294                 gdsc_assert_clamp_io(sc);
 295 
 296         return 0;
 297 }
 298 
 299 static int gdsc_init(struct gdsc *sc)
 300 {
 301         u32 mask, val;
 302         int on, ret;
 303 
 304         /*
 305          * Disable HW trigger: collapse/restore occur based on registers writes.
 306          * Disable SW override: Use hardware state-machine for sequencing.
 307          * Configure wait time between states.
 308          */
 309         mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
 310                EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
 311         val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
 312         ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
 313         if (ret)
 314                 return ret;
 315 
 316         /* Force gdsc ON if only ON state is supported */
 317         if (sc->pwrsts == PWRSTS_ON) {
 318                 ret = gdsc_toggle_logic(sc, GDSC_ON);
 319                 if (ret)
 320                         return ret;
 321         }
 322 
 323         on = gdsc_check_status(sc, GDSC_ON);
 324         if (on < 0)
 325                 return on;
 326 
 327         /*
 328          * Votable GDSCs can be ON due to Vote from other masters.
 329          * If a Votable GDSC is ON, make sure we have a Vote.
 330          */
 331         if ((sc->flags & VOTABLE) && on)
 332                 gdsc_enable(&sc->pd);
 333 
 334         /* If ALWAYS_ON GDSCs are not ON, turn them ON */
 335         if (sc->flags & ALWAYS_ON) {
 336                 if (!on)
 337                         gdsc_enable(&sc->pd);
 338                 on = true;
 339                 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
 340         }
 341 
 342         if (on || (sc->pwrsts & PWRSTS_RET))
 343                 gdsc_force_mem_on(sc);
 344         else
 345                 gdsc_clear_mem_on(sc);
 346 
 347         if (!sc->pd.power_off)
 348                 sc->pd.power_off = gdsc_disable;
 349         if (!sc->pd.power_on)
 350                 sc->pd.power_on = gdsc_enable;
 351         pm_genpd_init(&sc->pd, NULL, !on);
 352 
 353         return 0;
 354 }
 355 
 356 int gdsc_register(struct gdsc_desc *desc,
 357                   struct reset_controller_dev *rcdev, struct regmap *regmap)
 358 {
 359         int i, ret;
 360         struct genpd_onecell_data *data;
 361         struct device *dev = desc->dev;
 362         struct gdsc **scs = desc->scs;
 363         size_t num = desc->num;
 364 
 365         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 366         if (!data)
 367                 return -ENOMEM;
 368 
 369         data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
 370                                      GFP_KERNEL);
 371         if (!data->domains)
 372                 return -ENOMEM;
 373 
 374         data->num_domains = num;
 375         for (i = 0; i < num; i++) {
 376                 if (!scs[i])
 377                         continue;
 378                 scs[i]->regmap = regmap;
 379                 scs[i]->rcdev = rcdev;
 380                 ret = gdsc_init(scs[i]);
 381                 if (ret)
 382                         return ret;
 383                 data->domains[i] = &scs[i]->pd;
 384         }
 385 
 386         /* Add subdomains */
 387         for (i = 0; i < num; i++) {
 388                 if (!scs[i])
 389                         continue;
 390                 if (scs[i]->parent)
 391                         pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
 392         }
 393 
 394         return of_genpd_add_provider_onecell(dev->of_node, data);
 395 }
 396 
 397 void gdsc_unregister(struct gdsc_desc *desc)
 398 {
 399         int i;
 400         struct device *dev = desc->dev;
 401         struct gdsc **scs = desc->scs;
 402         size_t num = desc->num;
 403 
 404         /* Remove subdomains */
 405         for (i = 0; i < num; i++) {
 406                 if (!scs[i])
 407                         continue;
 408                 if (scs[i]->parent)
 409                         pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
 410         }
 411         of_genpd_del_provider(dev->of_node);
 412 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/clk/qcom/gdsc.c

DEFINITIONS
