This source file includes following definitions.
- gcc_ipq806x_probe
- gcc_ipq806x_init
- gcc_ipq806x_exit
1
2
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5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
18 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
19
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "clk-hfpll.h"
26 #include "reset.h"
27
28 static struct clk_pll pll0 = {
29 .l_reg = 0x30c4,
30 .m_reg = 0x30c8,
31 .n_reg = 0x30cc,
32 .config_reg = 0x30d4,
33 .mode_reg = 0x30c0,
34 .status_reg = 0x30d8,
35 .status_bit = 16,
36 .clkr.hw.init = &(struct clk_init_data){
37 .name = "pll0",
38 .parent_names = (const char *[]){ "pxo" },
39 .num_parents = 1,
40 .ops = &clk_pll_ops,
41 },
42 };
43
44 static struct clk_regmap pll0_vote = {
45 .enable_reg = 0x34c0,
46 .enable_mask = BIT(0),
47 .hw.init = &(struct clk_init_data){
48 .name = "pll0_vote",
49 .parent_names = (const char *[]){ "pll0" },
50 .num_parents = 1,
51 .ops = &clk_pll_vote_ops,
52 },
53 };
54
55 static struct clk_pll pll3 = {
56 .l_reg = 0x3164,
57 .m_reg = 0x3168,
58 .n_reg = 0x316c,
59 .config_reg = 0x3174,
60 .mode_reg = 0x3160,
61 .status_reg = 0x3178,
62 .status_bit = 16,
63 .clkr.hw.init = &(struct clk_init_data){
64 .name = "pll3",
65 .parent_names = (const char *[]){ "pxo" },
66 .num_parents = 1,
67 .ops = &clk_pll_ops,
68 },
69 };
70
71 static struct clk_regmap pll4_vote = {
72 .enable_reg = 0x34c0,
73 .enable_mask = BIT(4),
74 .hw.init = &(struct clk_init_data){
75 .name = "pll4_vote",
76 .parent_names = (const char *[]){ "pll4" },
77 .num_parents = 1,
78 .ops = &clk_pll_vote_ops,
79 },
80 };
81
82 static struct clk_pll pll8 = {
83 .l_reg = 0x3144,
84 .m_reg = 0x3148,
85 .n_reg = 0x314c,
86 .config_reg = 0x3154,
87 .mode_reg = 0x3140,
88 .status_reg = 0x3158,
89 .status_bit = 16,
90 .clkr.hw.init = &(struct clk_init_data){
91 .name = "pll8",
92 .parent_names = (const char *[]){ "pxo" },
93 .num_parents = 1,
94 .ops = &clk_pll_ops,
95 },
96 };
97
98 static struct clk_regmap pll8_vote = {
99 .enable_reg = 0x34c0,
100 .enable_mask = BIT(8),
101 .hw.init = &(struct clk_init_data){
102 .name = "pll8_vote",
103 .parent_names = (const char *[]){ "pll8" },
104 .num_parents = 1,
105 .ops = &clk_pll_vote_ops,
106 },
107 };
108
109 static struct hfpll_data hfpll0_data = {
110 .mode_reg = 0x3200,
111 .l_reg = 0x3208,
112 .m_reg = 0x320c,
113 .n_reg = 0x3210,
114 .config_reg = 0x3204,
115 .status_reg = 0x321c,
116 .config_val = 0x7845c665,
117 .droop_reg = 0x3214,
118 .droop_val = 0x0108c000,
119 .min_rate = 600000000UL,
120 .max_rate = 1800000000UL,
121 };
122
123 static struct clk_hfpll hfpll0 = {
124 .d = &hfpll0_data,
125 .clkr.hw.init = &(struct clk_init_data){
126 .parent_names = (const char *[]){ "pxo" },
127 .num_parents = 1,
128 .name = "hfpll0",
129 .ops = &clk_ops_hfpll,
130 .flags = CLK_IGNORE_UNUSED,
131 },
132 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
133 };
134
135 static struct hfpll_data hfpll1_data = {
136 .mode_reg = 0x3240,
137 .l_reg = 0x3248,
138 .m_reg = 0x324c,
139 .n_reg = 0x3250,
140 .config_reg = 0x3244,
141 .status_reg = 0x325c,
142 .config_val = 0x7845c665,
143 .droop_reg = 0x3314,
144 .droop_val = 0x0108c000,
145 .min_rate = 600000000UL,
146 .max_rate = 1800000000UL,
147 };
148
149 static struct clk_hfpll hfpll1 = {
150 .d = &hfpll1_data,
151 .clkr.hw.init = &(struct clk_init_data){
152 .parent_names = (const char *[]){ "pxo" },
153 .num_parents = 1,
154 .name = "hfpll1",
155 .ops = &clk_ops_hfpll,
156 .flags = CLK_IGNORE_UNUSED,
157 },
158 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
159 };
160
161 static struct hfpll_data hfpll_l2_data = {
162 .mode_reg = 0x3300,
163 .l_reg = 0x3308,
164 .m_reg = 0x330c,
165 .n_reg = 0x3310,
166 .config_reg = 0x3304,
167 .status_reg = 0x331c,
168 .config_val = 0x7845c665,
169 .droop_reg = 0x3314,
170 .droop_val = 0x0108c000,
171 .min_rate = 600000000UL,
172 .max_rate = 1800000000UL,
173 };
174
175 static struct clk_hfpll hfpll_l2 = {
176 .d = &hfpll_l2_data,
177 .clkr.hw.init = &(struct clk_init_data){
178 .parent_names = (const char *[]){ "pxo" },
179 .num_parents = 1,
180 .name = "hfpll_l2",
181 .ops = &clk_ops_hfpll,
182 .flags = CLK_IGNORE_UNUSED,
183 },
184 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
185 };
186
187 static struct clk_pll pll14 = {
188 .l_reg = 0x31c4,
189 .m_reg = 0x31c8,
190 .n_reg = 0x31cc,
191 .config_reg = 0x31d4,
192 .mode_reg = 0x31c0,
193 .status_reg = 0x31d8,
194 .status_bit = 16,
195 .clkr.hw.init = &(struct clk_init_data){
196 .name = "pll14",
197 .parent_names = (const char *[]){ "pxo" },
198 .num_parents = 1,
199 .ops = &clk_pll_ops,
200 },
201 };
202
203 static struct clk_regmap pll14_vote = {
204 .enable_reg = 0x34c0,
205 .enable_mask = BIT(14),
206 .hw.init = &(struct clk_init_data){
207 .name = "pll14_vote",
208 .parent_names = (const char *[]){ "pll14" },
209 .num_parents = 1,
210 .ops = &clk_pll_vote_ops,
211 },
212 };
213
214 #define NSS_PLL_RATE(f, _l, _m, _n, i) \
215 { \
216 .freq = f, \
217 .l = _l, \
218 .m = _m, \
219 .n = _n, \
220 .ibits = i, \
221 }
222
223 static struct pll_freq_tbl pll18_freq_tbl[] = {
224 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
225 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
226 };
227
228 static struct clk_pll pll18 = {
229 .l_reg = 0x31a4,
230 .m_reg = 0x31a8,
231 .n_reg = 0x31ac,
232 .config_reg = 0x31b4,
233 .mode_reg = 0x31a0,
234 .status_reg = 0x31b8,
235 .status_bit = 16,
236 .post_div_shift = 16,
237 .post_div_width = 1,
238 .freq_tbl = pll18_freq_tbl,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "pll18",
241 .parent_names = (const char *[]){ "pxo" },
242 .num_parents = 1,
243 .ops = &clk_pll_ops,
244 },
245 };
246
247 enum {
248 P_PXO,
249 P_PLL8,
250 P_PLL3,
251 P_PLL0,
252 P_CXO,
253 P_PLL14,
254 P_PLL18,
255 };
256
257 static const struct parent_map gcc_pxo_pll8_map[] = {
258 { P_PXO, 0 },
259 { P_PLL8, 3 }
260 };
261
262 static const char * const gcc_pxo_pll8[] = {
263 "pxo",
264 "pll8_vote",
265 };
266
267 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
268 { P_PXO, 0 },
269 { P_PLL8, 3 },
270 { P_CXO, 5 }
271 };
272
273 static const char * const gcc_pxo_pll8_cxo[] = {
274 "pxo",
275 "pll8_vote",
276 "cxo",
277 };
278
279 static const struct parent_map gcc_pxo_pll3_map[] = {
280 { P_PXO, 0 },
281 { P_PLL3, 1 }
282 };
283
284 static const struct parent_map gcc_pxo_pll3_sata_map[] = {
285 { P_PXO, 0 },
286 { P_PLL3, 6 }
287 };
288
289 static const char * const gcc_pxo_pll3[] = {
290 "pxo",
291 "pll3",
292 };
293
294 static const struct parent_map gcc_pxo_pll8_pll0[] = {
295 { P_PXO, 0 },
296 { P_PLL8, 3 },
297 { P_PLL0, 2 }
298 };
299
300 static const char * const gcc_pxo_pll8_pll0_map[] = {
301 "pxo",
302 "pll8_vote",
303 "pll0_vote",
304 };
305
306 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
307 { P_PXO, 0 },
308 { P_PLL8, 4 },
309 { P_PLL0, 2 },
310 { P_PLL14, 5 },
311 { P_PLL18, 1 }
312 };
313
314 static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
315 "pxo",
316 "pll8_vote",
317 "pll0_vote",
318 "pll14",
319 "pll18",
320 };
321
322 static struct freq_tbl clk_tbl_gsbi_uart[] = {
323 { 1843200, P_PLL8, 2, 6, 625 },
324 { 3686400, P_PLL8, 2, 12, 625 },
325 { 7372800, P_PLL8, 2, 24, 625 },
326 { 14745600, P_PLL8, 2, 48, 625 },
327 { 16000000, P_PLL8, 4, 1, 6 },
328 { 24000000, P_PLL8, 4, 1, 4 },
329 { 32000000, P_PLL8, 4, 1, 3 },
330 { 40000000, P_PLL8, 1, 5, 48 },
331 { 46400000, P_PLL8, 1, 29, 240 },
332 { 48000000, P_PLL8, 4, 1, 2 },
333 { 51200000, P_PLL8, 1, 2, 15 },
334 { 56000000, P_PLL8, 1, 7, 48 },
335 { 58982400, P_PLL8, 1, 96, 625 },
336 { 64000000, P_PLL8, 2, 1, 3 },
337 { }
338 };
339
340 static struct clk_rcg gsbi1_uart_src = {
341 .ns_reg = 0x29d4,
342 .md_reg = 0x29d0,
343 .mn = {
344 .mnctr_en_bit = 8,
345 .mnctr_reset_bit = 7,
346 .mnctr_mode_shift = 5,
347 .n_val_shift = 16,
348 .m_val_shift = 16,
349 .width = 16,
350 },
351 .p = {
352 .pre_div_shift = 3,
353 .pre_div_width = 2,
354 },
355 .s = {
356 .src_sel_shift = 0,
357 .parent_map = gcc_pxo_pll8_map,
358 },
359 .freq_tbl = clk_tbl_gsbi_uart,
360 .clkr = {
361 .enable_reg = 0x29d4,
362 .enable_mask = BIT(11),
363 .hw.init = &(struct clk_init_data){
364 .name = "gsbi1_uart_src",
365 .parent_names = gcc_pxo_pll8,
366 .num_parents = 2,
367 .ops = &clk_rcg_ops,
368 .flags = CLK_SET_PARENT_GATE,
369 },
370 },
371 };
372
373 static struct clk_branch gsbi1_uart_clk = {
374 .halt_reg = 0x2fcc,
375 .halt_bit = 12,
376 .clkr = {
377 .enable_reg = 0x29d4,
378 .enable_mask = BIT(9),
379 .hw.init = &(struct clk_init_data){
380 .name = "gsbi1_uart_clk",
381 .parent_names = (const char *[]){
382 "gsbi1_uart_src",
383 },
384 .num_parents = 1,
385 .ops = &clk_branch_ops,
386 .flags = CLK_SET_RATE_PARENT,
387 },
388 },
389 };
390
391 static struct clk_rcg gsbi2_uart_src = {
392 .ns_reg = 0x29f4,
393 .md_reg = 0x29f0,
394 .mn = {
395 .mnctr_en_bit = 8,
396 .mnctr_reset_bit = 7,
397 .mnctr_mode_shift = 5,
398 .n_val_shift = 16,
399 .m_val_shift = 16,
400 .width = 16,
401 },
402 .p = {
403 .pre_div_shift = 3,
404 .pre_div_width = 2,
405 },
406 .s = {
407 .src_sel_shift = 0,
408 .parent_map = gcc_pxo_pll8_map,
409 },
410 .freq_tbl = clk_tbl_gsbi_uart,
411 .clkr = {
412 .enable_reg = 0x29f4,
413 .enable_mask = BIT(11),
414 .hw.init = &(struct clk_init_data){
415 .name = "gsbi2_uart_src",
416 .parent_names = gcc_pxo_pll8,
417 .num_parents = 2,
418 .ops = &clk_rcg_ops,
419 .flags = CLK_SET_PARENT_GATE,
420 },
421 },
422 };
423
424 static struct clk_branch gsbi2_uart_clk = {
425 .halt_reg = 0x2fcc,
426 .halt_bit = 8,
427 .clkr = {
428 .enable_reg = 0x29f4,
429 .enable_mask = BIT(9),
430 .hw.init = &(struct clk_init_data){
431 .name = "gsbi2_uart_clk",
432 .parent_names = (const char *[]){
433 "gsbi2_uart_src",
434 },
435 .num_parents = 1,
436 .ops = &clk_branch_ops,
437 .flags = CLK_SET_RATE_PARENT,
438 },
439 },
440 };
441
442 static struct clk_rcg gsbi4_uart_src = {
443 .ns_reg = 0x2a34,
444 .md_reg = 0x2a30,
445 .mn = {
446 .mnctr_en_bit = 8,
447 .mnctr_reset_bit = 7,
448 .mnctr_mode_shift = 5,
449 .n_val_shift = 16,
450 .m_val_shift = 16,
451 .width = 16,
452 },
453 .p = {
454 .pre_div_shift = 3,
455 .pre_div_width = 2,
456 },
457 .s = {
458 .src_sel_shift = 0,
459 .parent_map = gcc_pxo_pll8_map,
460 },
461 .freq_tbl = clk_tbl_gsbi_uart,
462 .clkr = {
463 .enable_reg = 0x2a34,
464 .enable_mask = BIT(11),
465 .hw.init = &(struct clk_init_data){
466 .name = "gsbi4_uart_src",
467 .parent_names = gcc_pxo_pll8,
468 .num_parents = 2,
469 .ops = &clk_rcg_ops,
470 .flags = CLK_SET_PARENT_GATE,
471 },
472 },
473 };
474
475 static struct clk_branch gsbi4_uart_clk = {
476 .halt_reg = 0x2fd0,
477 .halt_bit = 26,
478 .clkr = {
479 .enable_reg = 0x2a34,
480 .enable_mask = BIT(9),
481 .hw.init = &(struct clk_init_data){
482 .name = "gsbi4_uart_clk",
483 .parent_names = (const char *[]){
484 "gsbi4_uart_src",
485 },
486 .num_parents = 1,
487 .ops = &clk_branch_ops,
488 .flags = CLK_SET_RATE_PARENT,
489 },
490 },
491 };
492
493 static struct clk_rcg gsbi5_uart_src = {
494 .ns_reg = 0x2a54,
495 .md_reg = 0x2a50,
496 .mn = {
497 .mnctr_en_bit = 8,
498 .mnctr_reset_bit = 7,
499 .mnctr_mode_shift = 5,
500 .n_val_shift = 16,
501 .m_val_shift = 16,
502 .width = 16,
503 },
504 .p = {
505 .pre_div_shift = 3,
506 .pre_div_width = 2,
507 },
508 .s = {
509 .src_sel_shift = 0,
510 .parent_map = gcc_pxo_pll8_map,
511 },
512 .freq_tbl = clk_tbl_gsbi_uart,
513 .clkr = {
514 .enable_reg = 0x2a54,
515 .enable_mask = BIT(11),
516 .hw.init = &(struct clk_init_data){
517 .name = "gsbi5_uart_src",
518 .parent_names = gcc_pxo_pll8,
519 .num_parents = 2,
520 .ops = &clk_rcg_ops,
521 .flags = CLK_SET_PARENT_GATE,
522 },
523 },
524 };
525
526 static struct clk_branch gsbi5_uart_clk = {
527 .halt_reg = 0x2fd0,
528 .halt_bit = 22,
529 .clkr = {
530 .enable_reg = 0x2a54,
531 .enable_mask = BIT(9),
532 .hw.init = &(struct clk_init_data){
533 .name = "gsbi5_uart_clk",
534 .parent_names = (const char *[]){
535 "gsbi5_uart_src",
536 },
537 .num_parents = 1,
538 .ops = &clk_branch_ops,
539 .flags = CLK_SET_RATE_PARENT,
540 },
541 },
542 };
543
544 static struct clk_rcg gsbi6_uart_src = {
545 .ns_reg = 0x2a74,
546 .md_reg = 0x2a70,
547 .mn = {
548 .mnctr_en_bit = 8,
549 .mnctr_reset_bit = 7,
550 .mnctr_mode_shift = 5,
551 .n_val_shift = 16,
552 .m_val_shift = 16,
553 .width = 16,
554 },
555 .p = {
556 .pre_div_shift = 3,
557 .pre_div_width = 2,
558 },
559 .s = {
560 .src_sel_shift = 0,
561 .parent_map = gcc_pxo_pll8_map,
562 },
563 .freq_tbl = clk_tbl_gsbi_uart,
564 .clkr = {
565 .enable_reg = 0x2a74,
566 .enable_mask = BIT(11),
567 .hw.init = &(struct clk_init_data){
568 .name = "gsbi6_uart_src",
569 .parent_names = gcc_pxo_pll8,
570 .num_parents = 2,
571 .ops = &clk_rcg_ops,
572 .flags = CLK_SET_PARENT_GATE,
573 },
574 },
575 };
576
577 static struct clk_branch gsbi6_uart_clk = {
578 .halt_reg = 0x2fd0,
579 .halt_bit = 18,
580 .clkr = {
581 .enable_reg = 0x2a74,
582 .enable_mask = BIT(9),
583 .hw.init = &(struct clk_init_data){
584 .name = "gsbi6_uart_clk",
585 .parent_names = (const char *[]){
586 "gsbi6_uart_src",
587 },
588 .num_parents = 1,
589 .ops = &clk_branch_ops,
590 .flags = CLK_SET_RATE_PARENT,
591 },
592 },
593 };
594
595 static struct clk_rcg gsbi7_uart_src = {
596 .ns_reg = 0x2a94,
597 .md_reg = 0x2a90,
598 .mn = {
599 .mnctr_en_bit = 8,
600 .mnctr_reset_bit = 7,
601 .mnctr_mode_shift = 5,
602 .n_val_shift = 16,
603 .m_val_shift = 16,
604 .width = 16,
605 },
606 .p = {
607 .pre_div_shift = 3,
608 .pre_div_width = 2,
609 },
610 .s = {
611 .src_sel_shift = 0,
612 .parent_map = gcc_pxo_pll8_map,
613 },
614 .freq_tbl = clk_tbl_gsbi_uart,
615 .clkr = {
616 .enable_reg = 0x2a94,
617 .enable_mask = BIT(11),
618 .hw.init = &(struct clk_init_data){
619 .name = "gsbi7_uart_src",
620 .parent_names = gcc_pxo_pll8,
621 .num_parents = 2,
622 .ops = &clk_rcg_ops,
623 .flags = CLK_SET_PARENT_GATE,
624 },
625 },
626 };
627
628 static struct clk_branch gsbi7_uart_clk = {
629 .halt_reg = 0x2fd0,
630 .halt_bit = 14,
631 .clkr = {
632 .enable_reg = 0x2a94,
633 .enable_mask = BIT(9),
634 .hw.init = &(struct clk_init_data){
635 .name = "gsbi7_uart_clk",
636 .parent_names = (const char *[]){
637 "gsbi7_uart_src",
638 },
639 .num_parents = 1,
640 .ops = &clk_branch_ops,
641 .flags = CLK_SET_RATE_PARENT,
642 },
643 },
644 };
645
646 static struct freq_tbl clk_tbl_gsbi_qup[] = {
647 { 1100000, P_PXO, 1, 2, 49 },
648 { 5400000, P_PXO, 1, 1, 5 },
649 { 10800000, P_PXO, 1, 2, 5 },
650 { 15060000, P_PLL8, 1, 2, 51 },
651 { 24000000, P_PLL8, 4, 1, 4 },
652 { 25000000, P_PXO, 1, 0, 0 },
653 { 25600000, P_PLL8, 1, 1, 15 },
654 { 48000000, P_PLL8, 4, 1, 2 },
655 { 51200000, P_PLL8, 1, 2, 15 },
656 { }
657 };
658
659 static struct clk_rcg gsbi1_qup_src = {
660 .ns_reg = 0x29cc,
661 .md_reg = 0x29c8,
662 .mn = {
663 .mnctr_en_bit = 8,
664 .mnctr_reset_bit = 7,
665 .mnctr_mode_shift = 5,
666 .n_val_shift = 16,
667 .m_val_shift = 16,
668 .width = 8,
669 },
670 .p = {
671 .pre_div_shift = 3,
672 .pre_div_width = 2,
673 },
674 .s = {
675 .src_sel_shift = 0,
676 .parent_map = gcc_pxo_pll8_map,
677 },
678 .freq_tbl = clk_tbl_gsbi_qup,
679 .clkr = {
680 .enable_reg = 0x29cc,
681 .enable_mask = BIT(11),
682 .hw.init = &(struct clk_init_data){
683 .name = "gsbi1_qup_src",
684 .parent_names = gcc_pxo_pll8,
685 .num_parents = 2,
686 .ops = &clk_rcg_ops,
687 .flags = CLK_SET_PARENT_GATE,
688 },
689 },
690 };
691
692 static struct clk_branch gsbi1_qup_clk = {
693 .halt_reg = 0x2fcc,
694 .halt_bit = 11,
695 .clkr = {
696 .enable_reg = 0x29cc,
697 .enable_mask = BIT(9),
698 .hw.init = &(struct clk_init_data){
699 .name = "gsbi1_qup_clk",
700 .parent_names = (const char *[]){ "gsbi1_qup_src" },
701 .num_parents = 1,
702 .ops = &clk_branch_ops,
703 .flags = CLK_SET_RATE_PARENT,
704 },
705 },
706 };
707
708 static struct clk_rcg gsbi2_qup_src = {
709 .ns_reg = 0x29ec,
710 .md_reg = 0x29e8,
711 .mn = {
712 .mnctr_en_bit = 8,
713 .mnctr_reset_bit = 7,
714 .mnctr_mode_shift = 5,
715 .n_val_shift = 16,
716 .m_val_shift = 16,
717 .width = 8,
718 },
719 .p = {
720 .pre_div_shift = 3,
721 .pre_div_width = 2,
722 },
723 .s = {
724 .src_sel_shift = 0,
725 .parent_map = gcc_pxo_pll8_map,
726 },
727 .freq_tbl = clk_tbl_gsbi_qup,
728 .clkr = {
729 .enable_reg = 0x29ec,
730 .enable_mask = BIT(11),
731 .hw.init = &(struct clk_init_data){
732 .name = "gsbi2_qup_src",
733 .parent_names = gcc_pxo_pll8,
734 .num_parents = 2,
735 .ops = &clk_rcg_ops,
736 .flags = CLK_SET_PARENT_GATE,
737 },
738 },
739 };
740
741 static struct clk_branch gsbi2_qup_clk = {
742 .halt_reg = 0x2fcc,
743 .halt_bit = 6,
744 .clkr = {
745 .enable_reg = 0x29ec,
746 .enable_mask = BIT(9),
747 .hw.init = &(struct clk_init_data){
748 .name = "gsbi2_qup_clk",
749 .parent_names = (const char *[]){ "gsbi2_qup_src" },
750 .num_parents = 1,
751 .ops = &clk_branch_ops,
752 .flags = CLK_SET_RATE_PARENT,
753 },
754 },
755 };
756
757 static struct clk_rcg gsbi4_qup_src = {
758 .ns_reg = 0x2a2c,
759 .md_reg = 0x2a28,
760 .mn = {
761 .mnctr_en_bit = 8,
762 .mnctr_reset_bit = 7,
763 .mnctr_mode_shift = 5,
764 .n_val_shift = 16,
765 .m_val_shift = 16,
766 .width = 8,
767 },
768 .p = {
769 .pre_div_shift = 3,
770 .pre_div_width = 2,
771 },
772 .s = {
773 .src_sel_shift = 0,
774 .parent_map = gcc_pxo_pll8_map,
775 },
776 .freq_tbl = clk_tbl_gsbi_qup,
777 .clkr = {
778 .enable_reg = 0x2a2c,
779 .enable_mask = BIT(11),
780 .hw.init = &(struct clk_init_data){
781 .name = "gsbi4_qup_src",
782 .parent_names = gcc_pxo_pll8,
783 .num_parents = 2,
784 .ops = &clk_rcg_ops,
785 .flags = CLK_SET_PARENT_GATE,
786 },
787 },
788 };
789
790 static struct clk_branch gsbi4_qup_clk = {
791 .halt_reg = 0x2fd0,
792 .halt_bit = 24,
793 .clkr = {
794 .enable_reg = 0x2a2c,
795 .enable_mask = BIT(9),
796 .hw.init = &(struct clk_init_data){
797 .name = "gsbi4_qup_clk",
798 .parent_names = (const char *[]){ "gsbi4_qup_src" },
799 .num_parents = 1,
800 .ops = &clk_branch_ops,
801 .flags = CLK_SET_RATE_PARENT,
802 },
803 },
804 };
805
806 static struct clk_rcg gsbi5_qup_src = {
807 .ns_reg = 0x2a4c,
808 .md_reg = 0x2a48,
809 .mn = {
810 .mnctr_en_bit = 8,
811 .mnctr_reset_bit = 7,
812 .mnctr_mode_shift = 5,
813 .n_val_shift = 16,
814 .m_val_shift = 16,
815 .width = 8,
816 },
817 .p = {
818 .pre_div_shift = 3,
819 .pre_div_width = 2,
820 },
821 .s = {
822 .src_sel_shift = 0,
823 .parent_map = gcc_pxo_pll8_map,
824 },
825 .freq_tbl = clk_tbl_gsbi_qup,
826 .clkr = {
827 .enable_reg = 0x2a4c,
828 .enable_mask = BIT(11),
829 .hw.init = &(struct clk_init_data){
830 .name = "gsbi5_qup_src",
831 .parent_names = gcc_pxo_pll8,
832 .num_parents = 2,
833 .ops = &clk_rcg_ops,
834 .flags = CLK_SET_PARENT_GATE,
835 },
836 },
837 };
838
839 static struct clk_branch gsbi5_qup_clk = {
840 .halt_reg = 0x2fd0,
841 .halt_bit = 20,
842 .clkr = {
843 .enable_reg = 0x2a4c,
844 .enable_mask = BIT(9),
845 .hw.init = &(struct clk_init_data){
846 .name = "gsbi5_qup_clk",
847 .parent_names = (const char *[]){ "gsbi5_qup_src" },
848 .num_parents = 1,
849 .ops = &clk_branch_ops,
850 .flags = CLK_SET_RATE_PARENT,
851 },
852 },
853 };
854
855 static struct clk_rcg gsbi6_qup_src = {
856 .ns_reg = 0x2a6c,
857 .md_reg = 0x2a68,
858 .mn = {
859 .mnctr_en_bit = 8,
860 .mnctr_reset_bit = 7,
861 .mnctr_mode_shift = 5,
862 .n_val_shift = 16,
863 .m_val_shift = 16,
864 .width = 8,
865 },
866 .p = {
867 .pre_div_shift = 3,
868 .pre_div_width = 2,
869 },
870 .s = {
871 .src_sel_shift = 0,
872 .parent_map = gcc_pxo_pll8_map,
873 },
874 .freq_tbl = clk_tbl_gsbi_qup,
875 .clkr = {
876 .enable_reg = 0x2a6c,
877 .enable_mask = BIT(11),
878 .hw.init = &(struct clk_init_data){
879 .name = "gsbi6_qup_src",
880 .parent_names = gcc_pxo_pll8,
881 .num_parents = 2,
882 .ops = &clk_rcg_ops,
883 .flags = CLK_SET_PARENT_GATE,
884 },
885 },
886 };
887
888 static struct clk_branch gsbi6_qup_clk = {
889 .halt_reg = 0x2fd0,
890 .halt_bit = 16,
891 .clkr = {
892 .enable_reg = 0x2a6c,
893 .enable_mask = BIT(9),
894 .hw.init = &(struct clk_init_data){
895 .name = "gsbi6_qup_clk",
896 .parent_names = (const char *[]){ "gsbi6_qup_src" },
897 .num_parents = 1,
898 .ops = &clk_branch_ops,
899 .flags = CLK_SET_RATE_PARENT,
900 },
901 },
902 };
903
904 static struct clk_rcg gsbi7_qup_src = {
905 .ns_reg = 0x2a8c,
906 .md_reg = 0x2a88,
907 .mn = {
908 .mnctr_en_bit = 8,
909 .mnctr_reset_bit = 7,
910 .mnctr_mode_shift = 5,
911 .n_val_shift = 16,
912 .m_val_shift = 16,
913 .width = 8,
914 },
915 .p = {
916 .pre_div_shift = 3,
917 .pre_div_width = 2,
918 },
919 .s = {
920 .src_sel_shift = 0,
921 .parent_map = gcc_pxo_pll8_map,
922 },
923 .freq_tbl = clk_tbl_gsbi_qup,
924 .clkr = {
925 .enable_reg = 0x2a8c,
926 .enable_mask = BIT(11),
927 .hw.init = &(struct clk_init_data){
928 .name = "gsbi7_qup_src",
929 .parent_names = gcc_pxo_pll8,
930 .num_parents = 2,
931 .ops = &clk_rcg_ops,
932 .flags = CLK_SET_PARENT_GATE,
933 },
934 },
935 };
936
937 static struct clk_branch gsbi7_qup_clk = {
938 .halt_reg = 0x2fd0,
939 .halt_bit = 12,
940 .clkr = {
941 .enable_reg = 0x2a8c,
942 .enable_mask = BIT(9),
943 .hw.init = &(struct clk_init_data){
944 .name = "gsbi7_qup_clk",
945 .parent_names = (const char *[]){ "gsbi7_qup_src" },
946 .num_parents = 1,
947 .ops = &clk_branch_ops,
948 .flags = CLK_SET_RATE_PARENT,
949 },
950 },
951 };
952
953 static struct clk_branch gsbi1_h_clk = {
954 .hwcg_reg = 0x29c0,
955 .hwcg_bit = 6,
956 .halt_reg = 0x2fcc,
957 .halt_bit = 13,
958 .clkr = {
959 .enable_reg = 0x29c0,
960 .enable_mask = BIT(4),
961 .hw.init = &(struct clk_init_data){
962 .name = "gsbi1_h_clk",
963 .ops = &clk_branch_ops,
964 },
965 },
966 };
967
968 static struct clk_branch gsbi2_h_clk = {
969 .hwcg_reg = 0x29e0,
970 .hwcg_bit = 6,
971 .halt_reg = 0x2fcc,
972 .halt_bit = 9,
973 .clkr = {
974 .enable_reg = 0x29e0,
975 .enable_mask = BIT(4),
976 .hw.init = &(struct clk_init_data){
977 .name = "gsbi2_h_clk",
978 .ops = &clk_branch_ops,
979 },
980 },
981 };
982
983 static struct clk_branch gsbi4_h_clk = {
984 .hwcg_reg = 0x2a20,
985 .hwcg_bit = 6,
986 .halt_reg = 0x2fd0,
987 .halt_bit = 27,
988 .clkr = {
989 .enable_reg = 0x2a20,
990 .enable_mask = BIT(4),
991 .hw.init = &(struct clk_init_data){
992 .name = "gsbi4_h_clk",
993 .ops = &clk_branch_ops,
994 },
995 },
996 };
997
998 static struct clk_branch gsbi5_h_clk = {
999 .hwcg_reg = 0x2a40,
1000 .hwcg_bit = 6,
1001 .halt_reg = 0x2fd0,
1002 .halt_bit = 23,
1003 .clkr = {
1004 .enable_reg = 0x2a40,
1005 .enable_mask = BIT(4),
1006 .hw.init = &(struct clk_init_data){
1007 .name = "gsbi5_h_clk",
1008 .ops = &clk_branch_ops,
1009 },
1010 },
1011 };
1012
1013 static struct clk_branch gsbi6_h_clk = {
1014 .hwcg_reg = 0x2a60,
1015 .hwcg_bit = 6,
1016 .halt_reg = 0x2fd0,
1017 .halt_bit = 19,
1018 .clkr = {
1019 .enable_reg = 0x2a60,
1020 .enable_mask = BIT(4),
1021 .hw.init = &(struct clk_init_data){
1022 .name = "gsbi6_h_clk",
1023 .ops = &clk_branch_ops,
1024 },
1025 },
1026 };
1027
1028 static struct clk_branch gsbi7_h_clk = {
1029 .hwcg_reg = 0x2a80,
1030 .hwcg_bit = 6,
1031 .halt_reg = 0x2fd0,
1032 .halt_bit = 15,
1033 .clkr = {
1034 .enable_reg = 0x2a80,
1035 .enable_mask = BIT(4),
1036 .hw.init = &(struct clk_init_data){
1037 .name = "gsbi7_h_clk",
1038 .ops = &clk_branch_ops,
1039 },
1040 },
1041 };
1042
1043 static const struct freq_tbl clk_tbl_gp[] = {
1044 { 12500000, P_PXO, 2, 0, 0 },
1045 { 25000000, P_PXO, 1, 0, 0 },
1046 { 64000000, P_PLL8, 2, 1, 3 },
1047 { 76800000, P_PLL8, 1, 1, 5 },
1048 { 96000000, P_PLL8, 4, 0, 0 },
1049 { 128000000, P_PLL8, 3, 0, 0 },
1050 { 192000000, P_PLL8, 2, 0, 0 },
1051 { }
1052 };
1053
1054 static struct clk_rcg gp0_src = {
1055 .ns_reg = 0x2d24,
1056 .md_reg = 0x2d00,
1057 .mn = {
1058 .mnctr_en_bit = 8,
1059 .mnctr_reset_bit = 7,
1060 .mnctr_mode_shift = 5,
1061 .n_val_shift = 16,
1062 .m_val_shift = 16,
1063 .width = 8,
1064 },
1065 .p = {
1066 .pre_div_shift = 3,
1067 .pre_div_width = 2,
1068 },
1069 .s = {
1070 .src_sel_shift = 0,
1071 .parent_map = gcc_pxo_pll8_cxo_map,
1072 },
1073 .freq_tbl = clk_tbl_gp,
1074 .clkr = {
1075 .enable_reg = 0x2d24,
1076 .enable_mask = BIT(11),
1077 .hw.init = &(struct clk_init_data){
1078 .name = "gp0_src",
1079 .parent_names = gcc_pxo_pll8_cxo,
1080 .num_parents = 3,
1081 .ops = &clk_rcg_ops,
1082 .flags = CLK_SET_PARENT_GATE,
1083 },
1084 }
1085 };
1086
1087 static struct clk_branch gp0_clk = {
1088 .halt_reg = 0x2fd8,
1089 .halt_bit = 7,
1090 .clkr = {
1091 .enable_reg = 0x2d24,
1092 .enable_mask = BIT(9),
1093 .hw.init = &(struct clk_init_data){
1094 .name = "gp0_clk",
1095 .parent_names = (const char *[]){ "gp0_src" },
1096 .num_parents = 1,
1097 .ops = &clk_branch_ops,
1098 .flags = CLK_SET_RATE_PARENT,
1099 },
1100 },
1101 };
1102
1103 static struct clk_rcg gp1_src = {
1104 .ns_reg = 0x2d44,
1105 .md_reg = 0x2d40,
1106 .mn = {
1107 .mnctr_en_bit = 8,
1108 .mnctr_reset_bit = 7,
1109 .mnctr_mode_shift = 5,
1110 .n_val_shift = 16,
1111 .m_val_shift = 16,
1112 .width = 8,
1113 },
1114 .p = {
1115 .pre_div_shift = 3,
1116 .pre_div_width = 2,
1117 },
1118 .s = {
1119 .src_sel_shift = 0,
1120 .parent_map = gcc_pxo_pll8_cxo_map,
1121 },
1122 .freq_tbl = clk_tbl_gp,
1123 .clkr = {
1124 .enable_reg = 0x2d44,
1125 .enable_mask = BIT(11),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gp1_src",
1128 .parent_names = gcc_pxo_pll8_cxo,
1129 .num_parents = 3,
1130 .ops = &clk_rcg_ops,
1131 .flags = CLK_SET_RATE_GATE,
1132 },
1133 }
1134 };
1135
1136 static struct clk_branch gp1_clk = {
1137 .halt_reg = 0x2fd8,
1138 .halt_bit = 6,
1139 .clkr = {
1140 .enable_reg = 0x2d44,
1141 .enable_mask = BIT(9),
1142 .hw.init = &(struct clk_init_data){
1143 .name = "gp1_clk",
1144 .parent_names = (const char *[]){ "gp1_src" },
1145 .num_parents = 1,
1146 .ops = &clk_branch_ops,
1147 .flags = CLK_SET_RATE_PARENT,
1148 },
1149 },
1150 };
1151
1152 static struct clk_rcg gp2_src = {
1153 .ns_reg = 0x2d64,
1154 .md_reg = 0x2d60,
1155 .mn = {
1156 .mnctr_en_bit = 8,
1157 .mnctr_reset_bit = 7,
1158 .mnctr_mode_shift = 5,
1159 .n_val_shift = 16,
1160 .m_val_shift = 16,
1161 .width = 8,
1162 },
1163 .p = {
1164 .pre_div_shift = 3,
1165 .pre_div_width = 2,
1166 },
1167 .s = {
1168 .src_sel_shift = 0,
1169 .parent_map = gcc_pxo_pll8_cxo_map,
1170 },
1171 .freq_tbl = clk_tbl_gp,
1172 .clkr = {
1173 .enable_reg = 0x2d64,
1174 .enable_mask = BIT(11),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "gp2_src",
1177 .parent_names = gcc_pxo_pll8_cxo,
1178 .num_parents = 3,
1179 .ops = &clk_rcg_ops,
1180 .flags = CLK_SET_RATE_GATE,
1181 },
1182 }
1183 };
1184
1185 static struct clk_branch gp2_clk = {
1186 .halt_reg = 0x2fd8,
1187 .halt_bit = 5,
1188 .clkr = {
1189 .enable_reg = 0x2d64,
1190 .enable_mask = BIT(9),
1191 .hw.init = &(struct clk_init_data){
1192 .name = "gp2_clk",
1193 .parent_names = (const char *[]){ "gp2_src" },
1194 .num_parents = 1,
1195 .ops = &clk_branch_ops,
1196 .flags = CLK_SET_RATE_PARENT,
1197 },
1198 },
1199 };
1200
1201 static struct clk_branch pmem_clk = {
1202 .hwcg_reg = 0x25a0,
1203 .hwcg_bit = 6,
1204 .halt_reg = 0x2fc8,
1205 .halt_bit = 20,
1206 .clkr = {
1207 .enable_reg = 0x25a0,
1208 .enable_mask = BIT(4),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "pmem_clk",
1211 .ops = &clk_branch_ops,
1212 },
1213 },
1214 };
1215
1216 static struct clk_rcg prng_src = {
1217 .ns_reg = 0x2e80,
1218 .p = {
1219 .pre_div_shift = 3,
1220 .pre_div_width = 4,
1221 },
1222 .s = {
1223 .src_sel_shift = 0,
1224 .parent_map = gcc_pxo_pll8_map,
1225 },
1226 .clkr = {
1227 .hw.init = &(struct clk_init_data){
1228 .name = "prng_src",
1229 .parent_names = gcc_pxo_pll8,
1230 .num_parents = 2,
1231 .ops = &clk_rcg_ops,
1232 },
1233 },
1234 };
1235
1236 static struct clk_branch prng_clk = {
1237 .halt_reg = 0x2fd8,
1238 .halt_check = BRANCH_HALT_VOTED,
1239 .halt_bit = 10,
1240 .clkr = {
1241 .enable_reg = 0x3080,
1242 .enable_mask = BIT(10),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "prng_clk",
1245 .parent_names = (const char *[]){ "prng_src" },
1246 .num_parents = 1,
1247 .ops = &clk_branch_ops,
1248 },
1249 },
1250 };
1251
1252 static const struct freq_tbl clk_tbl_sdc[] = {
1253 { 200000, P_PXO, 2, 2, 125 },
1254 { 400000, P_PLL8, 4, 1, 240 },
1255 { 16000000, P_PLL8, 4, 1, 6 },
1256 { 17070000, P_PLL8, 1, 2, 45 },
1257 { 20210000, P_PLL8, 1, 1, 19 },
1258 { 24000000, P_PLL8, 4, 1, 4 },
1259 { 48000000, P_PLL8, 4, 1, 2 },
1260 { 64000000, P_PLL8, 3, 1, 2 },
1261 { 96000000, P_PLL8, 4, 0, 0 },
1262 { 192000000, P_PLL8, 2, 0, 0 },
1263 { }
1264 };
1265
1266 static struct clk_rcg sdc1_src = {
1267 .ns_reg = 0x282c,
1268 .md_reg = 0x2828,
1269 .mn = {
1270 .mnctr_en_bit = 8,
1271 .mnctr_reset_bit = 7,
1272 .mnctr_mode_shift = 5,
1273 .n_val_shift = 16,
1274 .m_val_shift = 16,
1275 .width = 8,
1276 },
1277 .p = {
1278 .pre_div_shift = 3,
1279 .pre_div_width = 2,
1280 },
1281 .s = {
1282 .src_sel_shift = 0,
1283 .parent_map = gcc_pxo_pll8_map,
1284 },
1285 .freq_tbl = clk_tbl_sdc,
1286 .clkr = {
1287 .enable_reg = 0x282c,
1288 .enable_mask = BIT(11),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "sdc1_src",
1291 .parent_names = gcc_pxo_pll8,
1292 .num_parents = 2,
1293 .ops = &clk_rcg_ops,
1294 },
1295 }
1296 };
1297
1298 static struct clk_branch sdc1_clk = {
1299 .halt_reg = 0x2fc8,
1300 .halt_bit = 6,
1301 .clkr = {
1302 .enable_reg = 0x282c,
1303 .enable_mask = BIT(9),
1304 .hw.init = &(struct clk_init_data){
1305 .name = "sdc1_clk",
1306 .parent_names = (const char *[]){ "sdc1_src" },
1307 .num_parents = 1,
1308 .ops = &clk_branch_ops,
1309 .flags = CLK_SET_RATE_PARENT,
1310 },
1311 },
1312 };
1313
1314 static struct clk_rcg sdc3_src = {
1315 .ns_reg = 0x286c,
1316 .md_reg = 0x2868,
1317 .mn = {
1318 .mnctr_en_bit = 8,
1319 .mnctr_reset_bit = 7,
1320 .mnctr_mode_shift = 5,
1321 .n_val_shift = 16,
1322 .m_val_shift = 16,
1323 .width = 8,
1324 },
1325 .p = {
1326 .pre_div_shift = 3,
1327 .pre_div_width = 2,
1328 },
1329 .s = {
1330 .src_sel_shift = 0,
1331 .parent_map = gcc_pxo_pll8_map,
1332 },
1333 .freq_tbl = clk_tbl_sdc,
1334 .clkr = {
1335 .enable_reg = 0x286c,
1336 .enable_mask = BIT(11),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "sdc3_src",
1339 .parent_names = gcc_pxo_pll8,
1340 .num_parents = 2,
1341 .ops = &clk_rcg_ops,
1342 },
1343 }
1344 };
1345
1346 static struct clk_branch sdc3_clk = {
1347 .halt_reg = 0x2fc8,
1348 .halt_bit = 4,
1349 .clkr = {
1350 .enable_reg = 0x286c,
1351 .enable_mask = BIT(9),
1352 .hw.init = &(struct clk_init_data){
1353 .name = "sdc3_clk",
1354 .parent_names = (const char *[]){ "sdc3_src" },
1355 .num_parents = 1,
1356 .ops = &clk_branch_ops,
1357 .flags = CLK_SET_RATE_PARENT,
1358 },
1359 },
1360 };
1361
1362 static struct clk_branch sdc1_h_clk = {
1363 .hwcg_reg = 0x2820,
1364 .hwcg_bit = 6,
1365 .halt_reg = 0x2fc8,
1366 .halt_bit = 11,
1367 .clkr = {
1368 .enable_reg = 0x2820,
1369 .enable_mask = BIT(4),
1370 .hw.init = &(struct clk_init_data){
1371 .name = "sdc1_h_clk",
1372 .ops = &clk_branch_ops,
1373 },
1374 },
1375 };
1376
1377 static struct clk_branch sdc3_h_clk = {
1378 .hwcg_reg = 0x2860,
1379 .hwcg_bit = 6,
1380 .halt_reg = 0x2fc8,
1381 .halt_bit = 9,
1382 .clkr = {
1383 .enable_reg = 0x2860,
1384 .enable_mask = BIT(4),
1385 .hw.init = &(struct clk_init_data){
1386 .name = "sdc3_h_clk",
1387 .ops = &clk_branch_ops,
1388 },
1389 },
1390 };
1391
1392 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1393 { 105000, P_PXO, 1, 1, 256 },
1394 { }
1395 };
1396
1397 static struct clk_rcg tsif_ref_src = {
1398 .ns_reg = 0x2710,
1399 .md_reg = 0x270c,
1400 .mn = {
1401 .mnctr_en_bit = 8,
1402 .mnctr_reset_bit = 7,
1403 .mnctr_mode_shift = 5,
1404 .n_val_shift = 16,
1405 .m_val_shift = 16,
1406 .width = 16,
1407 },
1408 .p = {
1409 .pre_div_shift = 3,
1410 .pre_div_width = 2,
1411 },
1412 .s = {
1413 .src_sel_shift = 0,
1414 .parent_map = gcc_pxo_pll8_map,
1415 },
1416 .freq_tbl = clk_tbl_tsif_ref,
1417 .clkr = {
1418 .enable_reg = 0x2710,
1419 .enable_mask = BIT(11),
1420 .hw.init = &(struct clk_init_data){
1421 .name = "tsif_ref_src",
1422 .parent_names = gcc_pxo_pll8,
1423 .num_parents = 2,
1424 .ops = &clk_rcg_ops,
1425 },
1426 }
1427 };
1428
1429 static struct clk_branch tsif_ref_clk = {
1430 .halt_reg = 0x2fd4,
1431 .halt_bit = 5,
1432 .clkr = {
1433 .enable_reg = 0x2710,
1434 .enable_mask = BIT(9),
1435 .hw.init = &(struct clk_init_data){
1436 .name = "tsif_ref_clk",
1437 .parent_names = (const char *[]){ "tsif_ref_src" },
1438 .num_parents = 1,
1439 .ops = &clk_branch_ops,
1440 .flags = CLK_SET_RATE_PARENT,
1441 },
1442 },
1443 };
1444
1445 static struct clk_branch tsif_h_clk = {
1446 .hwcg_reg = 0x2700,
1447 .hwcg_bit = 6,
1448 .halt_reg = 0x2fd4,
1449 .halt_bit = 7,
1450 .clkr = {
1451 .enable_reg = 0x2700,
1452 .enable_mask = BIT(4),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "tsif_h_clk",
1455 .ops = &clk_branch_ops,
1456 },
1457 },
1458 };
1459
1460 static struct clk_branch dma_bam_h_clk = {
1461 .hwcg_reg = 0x25c0,
1462 .hwcg_bit = 6,
1463 .halt_reg = 0x2fc8,
1464 .halt_bit = 12,
1465 .clkr = {
1466 .enable_reg = 0x25c0,
1467 .enable_mask = BIT(4),
1468 .hw.init = &(struct clk_init_data){
1469 .name = "dma_bam_h_clk",
1470 .ops = &clk_branch_ops,
1471 },
1472 },
1473 };
1474
1475 static struct clk_branch adm0_clk = {
1476 .halt_reg = 0x2fdc,
1477 .halt_check = BRANCH_HALT_VOTED,
1478 .halt_bit = 12,
1479 .clkr = {
1480 .enable_reg = 0x3080,
1481 .enable_mask = BIT(2),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "adm0_clk",
1484 .ops = &clk_branch_ops,
1485 },
1486 },
1487 };
1488
1489 static struct clk_branch adm0_pbus_clk = {
1490 .hwcg_reg = 0x2208,
1491 .hwcg_bit = 6,
1492 .halt_reg = 0x2fdc,
1493 .halt_check = BRANCH_HALT_VOTED,
1494 .halt_bit = 11,
1495 .clkr = {
1496 .enable_reg = 0x3080,
1497 .enable_mask = BIT(3),
1498 .hw.init = &(struct clk_init_data){
1499 .name = "adm0_pbus_clk",
1500 .ops = &clk_branch_ops,
1501 },
1502 },
1503 };
1504
1505 static struct clk_branch pmic_arb0_h_clk = {
1506 .halt_reg = 0x2fd8,
1507 .halt_check = BRANCH_HALT_VOTED,
1508 .halt_bit = 22,
1509 .clkr = {
1510 .enable_reg = 0x3080,
1511 .enable_mask = BIT(8),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "pmic_arb0_h_clk",
1514 .ops = &clk_branch_ops,
1515 },
1516 },
1517 };
1518
1519 static struct clk_branch pmic_arb1_h_clk = {
1520 .halt_reg = 0x2fd8,
1521 .halt_check = BRANCH_HALT_VOTED,
1522 .halt_bit = 21,
1523 .clkr = {
1524 .enable_reg = 0x3080,
1525 .enable_mask = BIT(9),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "pmic_arb1_h_clk",
1528 .ops = &clk_branch_ops,
1529 },
1530 },
1531 };
1532
1533 static struct clk_branch pmic_ssbi2_clk = {
1534 .halt_reg = 0x2fd8,
1535 .halt_check = BRANCH_HALT_VOTED,
1536 .halt_bit = 23,
1537 .clkr = {
1538 .enable_reg = 0x3080,
1539 .enable_mask = BIT(7),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "pmic_ssbi2_clk",
1542 .ops = &clk_branch_ops,
1543 },
1544 },
1545 };
1546
1547 static struct clk_branch rpm_msg_ram_h_clk = {
1548 .hwcg_reg = 0x27e0,
1549 .hwcg_bit = 6,
1550 .halt_reg = 0x2fd8,
1551 .halt_check = BRANCH_HALT_VOTED,
1552 .halt_bit = 12,
1553 .clkr = {
1554 .enable_reg = 0x3080,
1555 .enable_mask = BIT(6),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "rpm_msg_ram_h_clk",
1558 .ops = &clk_branch_ops,
1559 },
1560 },
1561 };
1562
1563 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1564 { 100000000, P_PLL3, 12, 0, 0 },
1565 { }
1566 };
1567
1568 static struct clk_rcg pcie_ref_src = {
1569 .ns_reg = 0x3860,
1570 .p = {
1571 .pre_div_shift = 3,
1572 .pre_div_width = 4,
1573 },
1574 .s = {
1575 .src_sel_shift = 0,
1576 .parent_map = gcc_pxo_pll3_map,
1577 },
1578 .freq_tbl = clk_tbl_pcie_ref,
1579 .clkr = {
1580 .enable_reg = 0x3860,
1581 .enable_mask = BIT(11),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "pcie_ref_src",
1584 .parent_names = gcc_pxo_pll3,
1585 .num_parents = 2,
1586 .ops = &clk_rcg_ops,
1587 .flags = CLK_SET_RATE_GATE,
1588 },
1589 },
1590 };
1591
1592 static struct clk_branch pcie_ref_src_clk = {
1593 .halt_reg = 0x2fdc,
1594 .halt_bit = 30,
1595 .clkr = {
1596 .enable_reg = 0x3860,
1597 .enable_mask = BIT(9),
1598 .hw.init = &(struct clk_init_data){
1599 .name = "pcie_ref_src_clk",
1600 .parent_names = (const char *[]){ "pcie_ref_src" },
1601 .num_parents = 1,
1602 .ops = &clk_branch_ops,
1603 .flags = CLK_SET_RATE_PARENT,
1604 },
1605 },
1606 };
1607
1608 static struct clk_branch pcie_a_clk = {
1609 .halt_reg = 0x2fc0,
1610 .halt_bit = 13,
1611 .clkr = {
1612 .enable_reg = 0x22c0,
1613 .enable_mask = BIT(4),
1614 .hw.init = &(struct clk_init_data){
1615 .name = "pcie_a_clk",
1616 .ops = &clk_branch_ops,
1617 },
1618 },
1619 };
1620
1621 static struct clk_branch pcie_aux_clk = {
1622 .halt_reg = 0x2fdc,
1623 .halt_bit = 31,
1624 .clkr = {
1625 .enable_reg = 0x22c8,
1626 .enable_mask = BIT(4),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "pcie_aux_clk",
1629 .ops = &clk_branch_ops,
1630 },
1631 },
1632 };
1633
1634 static struct clk_branch pcie_h_clk = {
1635 .halt_reg = 0x2fd4,
1636 .halt_bit = 8,
1637 .clkr = {
1638 .enable_reg = 0x22cc,
1639 .enable_mask = BIT(4),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "pcie_h_clk",
1642 .ops = &clk_branch_ops,
1643 },
1644 },
1645 };
1646
1647 static struct clk_branch pcie_phy_clk = {
1648 .halt_reg = 0x2fdc,
1649 .halt_bit = 29,
1650 .clkr = {
1651 .enable_reg = 0x22d0,
1652 .enable_mask = BIT(4),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "pcie_phy_clk",
1655 .ops = &clk_branch_ops,
1656 },
1657 },
1658 };
1659
1660 static struct clk_rcg pcie1_ref_src = {
1661 .ns_reg = 0x3aa0,
1662 .p = {
1663 .pre_div_shift = 3,
1664 .pre_div_width = 4,
1665 },
1666 .s = {
1667 .src_sel_shift = 0,
1668 .parent_map = gcc_pxo_pll3_map,
1669 },
1670 .freq_tbl = clk_tbl_pcie_ref,
1671 .clkr = {
1672 .enable_reg = 0x3aa0,
1673 .enable_mask = BIT(11),
1674 .hw.init = &(struct clk_init_data){
1675 .name = "pcie1_ref_src",
1676 .parent_names = gcc_pxo_pll3,
1677 .num_parents = 2,
1678 .ops = &clk_rcg_ops,
1679 .flags = CLK_SET_RATE_GATE,
1680 },
1681 },
1682 };
1683
1684 static struct clk_branch pcie1_ref_src_clk = {
1685 .halt_reg = 0x2fdc,
1686 .halt_bit = 27,
1687 .clkr = {
1688 .enable_reg = 0x3aa0,
1689 .enable_mask = BIT(9),
1690 .hw.init = &(struct clk_init_data){
1691 .name = "pcie1_ref_src_clk",
1692 .parent_names = (const char *[]){ "pcie1_ref_src" },
1693 .num_parents = 1,
1694 .ops = &clk_branch_ops,
1695 .flags = CLK_SET_RATE_PARENT,
1696 },
1697 },
1698 };
1699
1700 static struct clk_branch pcie1_a_clk = {
1701 .halt_reg = 0x2fc0,
1702 .halt_bit = 10,
1703 .clkr = {
1704 .enable_reg = 0x3a80,
1705 .enable_mask = BIT(4),
1706 .hw.init = &(struct clk_init_data){
1707 .name = "pcie1_a_clk",
1708 .ops = &clk_branch_ops,
1709 },
1710 },
1711 };
1712
1713 static struct clk_branch pcie1_aux_clk = {
1714 .halt_reg = 0x2fdc,
1715 .halt_bit = 28,
1716 .clkr = {
1717 .enable_reg = 0x3a88,
1718 .enable_mask = BIT(4),
1719 .hw.init = &(struct clk_init_data){
1720 .name = "pcie1_aux_clk",
1721 .ops = &clk_branch_ops,
1722 },
1723 },
1724 };
1725
1726 static struct clk_branch pcie1_h_clk = {
1727 .halt_reg = 0x2fd4,
1728 .halt_bit = 9,
1729 .clkr = {
1730 .enable_reg = 0x3a8c,
1731 .enable_mask = BIT(4),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "pcie1_h_clk",
1734 .ops = &clk_branch_ops,
1735 },
1736 },
1737 };
1738
1739 static struct clk_branch pcie1_phy_clk = {
1740 .halt_reg = 0x2fdc,
1741 .halt_bit = 26,
1742 .clkr = {
1743 .enable_reg = 0x3a90,
1744 .enable_mask = BIT(4),
1745 .hw.init = &(struct clk_init_data){
1746 .name = "pcie1_phy_clk",
1747 .ops = &clk_branch_ops,
1748 },
1749 },
1750 };
1751
1752 static struct clk_rcg pcie2_ref_src = {
1753 .ns_reg = 0x3ae0,
1754 .p = {
1755 .pre_div_shift = 3,
1756 .pre_div_width = 4,
1757 },
1758 .s = {
1759 .src_sel_shift = 0,
1760 .parent_map = gcc_pxo_pll3_map,
1761 },
1762 .freq_tbl = clk_tbl_pcie_ref,
1763 .clkr = {
1764 .enable_reg = 0x3ae0,
1765 .enable_mask = BIT(11),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "pcie2_ref_src",
1768 .parent_names = gcc_pxo_pll3,
1769 .num_parents = 2,
1770 .ops = &clk_rcg_ops,
1771 .flags = CLK_SET_RATE_GATE,
1772 },
1773 },
1774 };
1775
1776 static struct clk_branch pcie2_ref_src_clk = {
1777 .halt_reg = 0x2fdc,
1778 .halt_bit = 24,
1779 .clkr = {
1780 .enable_reg = 0x3ae0,
1781 .enable_mask = BIT(9),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "pcie2_ref_src_clk",
1784 .parent_names = (const char *[]){ "pcie2_ref_src" },
1785 .num_parents = 1,
1786 .ops = &clk_branch_ops,
1787 .flags = CLK_SET_RATE_PARENT,
1788 },
1789 },
1790 };
1791
1792 static struct clk_branch pcie2_a_clk = {
1793 .halt_reg = 0x2fc0,
1794 .halt_bit = 9,
1795 .clkr = {
1796 .enable_reg = 0x3ac0,
1797 .enable_mask = BIT(4),
1798 .hw.init = &(struct clk_init_data){
1799 .name = "pcie2_a_clk",
1800 .ops = &clk_branch_ops,
1801 },
1802 },
1803 };
1804
1805 static struct clk_branch pcie2_aux_clk = {
1806 .halt_reg = 0x2fdc,
1807 .halt_bit = 25,
1808 .clkr = {
1809 .enable_reg = 0x3ac8,
1810 .enable_mask = BIT(4),
1811 .hw.init = &(struct clk_init_data){
1812 .name = "pcie2_aux_clk",
1813 .ops = &clk_branch_ops,
1814 },
1815 },
1816 };
1817
1818 static struct clk_branch pcie2_h_clk = {
1819 .halt_reg = 0x2fd4,
1820 .halt_bit = 10,
1821 .clkr = {
1822 .enable_reg = 0x3acc,
1823 .enable_mask = BIT(4),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "pcie2_h_clk",
1826 .ops = &clk_branch_ops,
1827 },
1828 },
1829 };
1830
1831 static struct clk_branch pcie2_phy_clk = {
1832 .halt_reg = 0x2fdc,
1833 .halt_bit = 23,
1834 .clkr = {
1835 .enable_reg = 0x3ad0,
1836 .enable_mask = BIT(4),
1837 .hw.init = &(struct clk_init_data){
1838 .name = "pcie2_phy_clk",
1839 .ops = &clk_branch_ops,
1840 },
1841 },
1842 };
1843
1844 static const struct freq_tbl clk_tbl_sata_ref[] = {
1845 { 100000000, P_PLL3, 12, 0, 0 },
1846 { }
1847 };
1848
1849 static struct clk_rcg sata_ref_src = {
1850 .ns_reg = 0x2c08,
1851 .p = {
1852 .pre_div_shift = 3,
1853 .pre_div_width = 4,
1854 },
1855 .s = {
1856 .src_sel_shift = 0,
1857 .parent_map = gcc_pxo_pll3_sata_map,
1858 },
1859 .freq_tbl = clk_tbl_sata_ref,
1860 .clkr = {
1861 .enable_reg = 0x2c08,
1862 .enable_mask = BIT(7),
1863 .hw.init = &(struct clk_init_data){
1864 .name = "sata_ref_src",
1865 .parent_names = gcc_pxo_pll3,
1866 .num_parents = 2,
1867 .ops = &clk_rcg_ops,
1868 .flags = CLK_SET_RATE_GATE,
1869 },
1870 },
1871 };
1872
1873 static struct clk_branch sata_rxoob_clk = {
1874 .halt_reg = 0x2fdc,
1875 .halt_bit = 20,
1876 .clkr = {
1877 .enable_reg = 0x2c0c,
1878 .enable_mask = BIT(4),
1879 .hw.init = &(struct clk_init_data){
1880 .name = "sata_rxoob_clk",
1881 .parent_names = (const char *[]){ "sata_ref_src" },
1882 .num_parents = 1,
1883 .ops = &clk_branch_ops,
1884 .flags = CLK_SET_RATE_PARENT,
1885 },
1886 },
1887 };
1888
1889 static struct clk_branch sata_pmalive_clk = {
1890 .halt_reg = 0x2fdc,
1891 .halt_bit = 19,
1892 .clkr = {
1893 .enable_reg = 0x2c10,
1894 .enable_mask = BIT(4),
1895 .hw.init = &(struct clk_init_data){
1896 .name = "sata_pmalive_clk",
1897 .parent_names = (const char *[]){ "sata_ref_src" },
1898 .num_parents = 1,
1899 .ops = &clk_branch_ops,
1900 .flags = CLK_SET_RATE_PARENT,
1901 },
1902 },
1903 };
1904
1905 static struct clk_branch sata_phy_ref_clk = {
1906 .halt_reg = 0x2fdc,
1907 .halt_bit = 18,
1908 .clkr = {
1909 .enable_reg = 0x2c14,
1910 .enable_mask = BIT(4),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "sata_phy_ref_clk",
1913 .parent_names = (const char *[]){ "pxo" },
1914 .num_parents = 1,
1915 .ops = &clk_branch_ops,
1916 },
1917 },
1918 };
1919
1920 static struct clk_branch sata_a_clk = {
1921 .halt_reg = 0x2fc0,
1922 .halt_bit = 12,
1923 .clkr = {
1924 .enable_reg = 0x2c20,
1925 .enable_mask = BIT(4),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "sata_a_clk",
1928 .ops = &clk_branch_ops,
1929 },
1930 },
1931 };
1932
1933 static struct clk_branch sata_h_clk = {
1934 .halt_reg = 0x2fdc,
1935 .halt_bit = 21,
1936 .clkr = {
1937 .enable_reg = 0x2c00,
1938 .enable_mask = BIT(4),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "sata_h_clk",
1941 .ops = &clk_branch_ops,
1942 },
1943 },
1944 };
1945
1946 static struct clk_branch sfab_sata_s_h_clk = {
1947 .halt_reg = 0x2fc4,
1948 .halt_bit = 14,
1949 .clkr = {
1950 .enable_reg = 0x2480,
1951 .enable_mask = BIT(4),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "sfab_sata_s_h_clk",
1954 .ops = &clk_branch_ops,
1955 },
1956 },
1957 };
1958
1959 static struct clk_branch sata_phy_cfg_clk = {
1960 .halt_reg = 0x2fcc,
1961 .halt_bit = 14,
1962 .clkr = {
1963 .enable_reg = 0x2c40,
1964 .enable_mask = BIT(4),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "sata_phy_cfg_clk",
1967 .ops = &clk_branch_ops,
1968 },
1969 },
1970 };
1971
1972 static const struct freq_tbl clk_tbl_usb30_master[] = {
1973 { 125000000, P_PLL0, 1, 5, 32 },
1974 { }
1975 };
1976
1977 static struct clk_rcg usb30_master_clk_src = {
1978 .ns_reg = 0x3b2c,
1979 .md_reg = 0x3b28,
1980 .mn = {
1981 .mnctr_en_bit = 8,
1982 .mnctr_reset_bit = 7,
1983 .mnctr_mode_shift = 5,
1984 .n_val_shift = 16,
1985 .m_val_shift = 16,
1986 .width = 8,
1987 },
1988 .p = {
1989 .pre_div_shift = 3,
1990 .pre_div_width = 2,
1991 },
1992 .s = {
1993 .src_sel_shift = 0,
1994 .parent_map = gcc_pxo_pll8_pll0,
1995 },
1996 .freq_tbl = clk_tbl_usb30_master,
1997 .clkr = {
1998 .enable_reg = 0x3b2c,
1999 .enable_mask = BIT(11),
2000 .hw.init = &(struct clk_init_data){
2001 .name = "usb30_master_ref_src",
2002 .parent_names = gcc_pxo_pll8_pll0_map,
2003 .num_parents = 3,
2004 .ops = &clk_rcg_ops,
2005 .flags = CLK_SET_RATE_GATE,
2006 },
2007 },
2008 };
2009
2010 static struct clk_branch usb30_0_branch_clk = {
2011 .halt_reg = 0x2fc4,
2012 .halt_bit = 22,
2013 .clkr = {
2014 .enable_reg = 0x3b24,
2015 .enable_mask = BIT(4),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "usb30_0_branch_clk",
2018 .parent_names = (const char *[]){ "usb30_master_ref_src", },
2019 .num_parents = 1,
2020 .ops = &clk_branch_ops,
2021 .flags = CLK_SET_RATE_PARENT,
2022 },
2023 },
2024 };
2025
2026 static struct clk_branch usb30_1_branch_clk = {
2027 .halt_reg = 0x2fc4,
2028 .halt_bit = 17,
2029 .clkr = {
2030 .enable_reg = 0x3b34,
2031 .enable_mask = BIT(4),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "usb30_1_branch_clk",
2034 .parent_names = (const char *[]){ "usb30_master_ref_src", },
2035 .num_parents = 1,
2036 .ops = &clk_branch_ops,
2037 .flags = CLK_SET_RATE_PARENT,
2038 },
2039 },
2040 };
2041
2042 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
2043 { 60000000, P_PLL8, 1, 5, 32 },
2044 { }
2045 };
2046
2047 static struct clk_rcg usb30_utmi_clk = {
2048 .ns_reg = 0x3b44,
2049 .md_reg = 0x3b40,
2050 .mn = {
2051 .mnctr_en_bit = 8,
2052 .mnctr_reset_bit = 7,
2053 .mnctr_mode_shift = 5,
2054 .n_val_shift = 16,
2055 .m_val_shift = 16,
2056 .width = 8,
2057 },
2058 .p = {
2059 .pre_div_shift = 3,
2060 .pre_div_width = 2,
2061 },
2062 .s = {
2063 .src_sel_shift = 0,
2064 .parent_map = gcc_pxo_pll8_pll0,
2065 },
2066 .freq_tbl = clk_tbl_usb30_utmi,
2067 .clkr = {
2068 .enable_reg = 0x3b44,
2069 .enable_mask = BIT(11),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "usb30_utmi_clk",
2072 .parent_names = gcc_pxo_pll8_pll0_map,
2073 .num_parents = 3,
2074 .ops = &clk_rcg_ops,
2075 .flags = CLK_SET_RATE_GATE,
2076 },
2077 },
2078 };
2079
2080 static struct clk_branch usb30_0_utmi_clk_ctl = {
2081 .halt_reg = 0x2fc4,
2082 .halt_bit = 21,
2083 .clkr = {
2084 .enable_reg = 0x3b48,
2085 .enable_mask = BIT(4),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "usb30_0_utmi_clk_ctl",
2088 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2089 .num_parents = 1,
2090 .ops = &clk_branch_ops,
2091 .flags = CLK_SET_RATE_PARENT,
2092 },
2093 },
2094 };
2095
2096 static struct clk_branch usb30_1_utmi_clk_ctl = {
2097 .halt_reg = 0x2fc4,
2098 .halt_bit = 15,
2099 .clkr = {
2100 .enable_reg = 0x3b4c,
2101 .enable_mask = BIT(4),
2102 .hw.init = &(struct clk_init_data){
2103 .name = "usb30_1_utmi_clk_ctl",
2104 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2105 .num_parents = 1,
2106 .ops = &clk_branch_ops,
2107 .flags = CLK_SET_RATE_PARENT,
2108 },
2109 },
2110 };
2111
2112 static const struct freq_tbl clk_tbl_usb[] = {
2113 { 60000000, P_PLL8, 1, 5, 32 },
2114 { }
2115 };
2116
2117 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2118 .ns_reg = 0x290C,
2119 .md_reg = 0x2908,
2120 .mn = {
2121 .mnctr_en_bit = 8,
2122 .mnctr_reset_bit = 7,
2123 .mnctr_mode_shift = 5,
2124 .n_val_shift = 16,
2125 .m_val_shift = 16,
2126 .width = 8,
2127 },
2128 .p = {
2129 .pre_div_shift = 3,
2130 .pre_div_width = 2,
2131 },
2132 .s = {
2133 .src_sel_shift = 0,
2134 .parent_map = gcc_pxo_pll8_pll0,
2135 },
2136 .freq_tbl = clk_tbl_usb,
2137 .clkr = {
2138 .enable_reg = 0x2968,
2139 .enable_mask = BIT(11),
2140 .hw.init = &(struct clk_init_data){
2141 .name = "usb_hs1_xcvr_src",
2142 .parent_names = gcc_pxo_pll8_pll0_map,
2143 .num_parents = 3,
2144 .ops = &clk_rcg_ops,
2145 .flags = CLK_SET_RATE_GATE,
2146 },
2147 },
2148 };
2149
2150 static struct clk_branch usb_hs1_xcvr_clk = {
2151 .halt_reg = 0x2fcc,
2152 .halt_bit = 17,
2153 .clkr = {
2154 .enable_reg = 0x290c,
2155 .enable_mask = BIT(9),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "usb_hs1_xcvr_clk",
2158 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2159 .num_parents = 1,
2160 .ops = &clk_branch_ops,
2161 .flags = CLK_SET_RATE_PARENT,
2162 },
2163 },
2164 };
2165
2166 static struct clk_branch usb_hs1_h_clk = {
2167 .hwcg_reg = 0x2900,
2168 .hwcg_bit = 6,
2169 .halt_reg = 0x2fc8,
2170 .halt_bit = 1,
2171 .clkr = {
2172 .enable_reg = 0x2900,
2173 .enable_mask = BIT(4),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "usb_hs1_h_clk",
2176 .ops = &clk_branch_ops,
2177 },
2178 },
2179 };
2180
2181 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2182 .ns_reg = 0x2968,
2183 .md_reg = 0x2964,
2184 .mn = {
2185 .mnctr_en_bit = 8,
2186 .mnctr_reset_bit = 7,
2187 .mnctr_mode_shift = 5,
2188 .n_val_shift = 16,
2189 .m_val_shift = 16,
2190 .width = 8,
2191 },
2192 .p = {
2193 .pre_div_shift = 3,
2194 .pre_div_width = 2,
2195 },
2196 .s = {
2197 .src_sel_shift = 0,
2198 .parent_map = gcc_pxo_pll8_pll0,
2199 },
2200 .freq_tbl = clk_tbl_usb,
2201 .clkr = {
2202 .enable_reg = 0x2968,
2203 .enable_mask = BIT(11),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "usb_fs1_xcvr_src",
2206 .parent_names = gcc_pxo_pll8_pll0_map,
2207 .num_parents = 3,
2208 .ops = &clk_rcg_ops,
2209 .flags = CLK_SET_RATE_GATE,
2210 },
2211 },
2212 };
2213
2214 static struct clk_branch usb_fs1_xcvr_clk = {
2215 .halt_reg = 0x2fcc,
2216 .halt_bit = 17,
2217 .clkr = {
2218 .enable_reg = 0x2968,
2219 .enable_mask = BIT(9),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "usb_fs1_xcvr_clk",
2222 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2223 .num_parents = 1,
2224 .ops = &clk_branch_ops,
2225 .flags = CLK_SET_RATE_PARENT,
2226 },
2227 },
2228 };
2229
2230 static struct clk_branch usb_fs1_sys_clk = {
2231 .halt_reg = 0x2fcc,
2232 .halt_bit = 18,
2233 .clkr = {
2234 .enable_reg = 0x296c,
2235 .enable_mask = BIT(4),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "usb_fs1_sys_clk",
2238 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2239 .num_parents = 1,
2240 .ops = &clk_branch_ops,
2241 .flags = CLK_SET_RATE_PARENT,
2242 },
2243 },
2244 };
2245
2246 static struct clk_branch usb_fs1_h_clk = {
2247 .halt_reg = 0x2fcc,
2248 .halt_bit = 19,
2249 .clkr = {
2250 .enable_reg = 0x2960,
2251 .enable_mask = BIT(4),
2252 .hw.init = &(struct clk_init_data){
2253 .name = "usb_fs1_h_clk",
2254 .ops = &clk_branch_ops,
2255 },
2256 },
2257 };
2258
2259 static struct clk_branch ebi2_clk = {
2260 .hwcg_reg = 0x3b00,
2261 .hwcg_bit = 6,
2262 .halt_reg = 0x2fcc,
2263 .halt_bit = 1,
2264 .clkr = {
2265 .enable_reg = 0x3b00,
2266 .enable_mask = BIT(4),
2267 .hw.init = &(struct clk_init_data){
2268 .name = "ebi2_clk",
2269 .ops = &clk_branch_ops,
2270 },
2271 },
2272 };
2273
2274 static struct clk_branch ebi2_aon_clk = {
2275 .halt_reg = 0x2fcc,
2276 .halt_bit = 0,
2277 .clkr = {
2278 .enable_reg = 0x3b00,
2279 .enable_mask = BIT(8),
2280 .hw.init = &(struct clk_init_data){
2281 .name = "ebi2_always_on_clk",
2282 .ops = &clk_branch_ops,
2283 },
2284 },
2285 };
2286
2287 static const struct freq_tbl clk_tbl_gmac[] = {
2288 { 133000000, P_PLL0, 1, 50, 301 },
2289 { 266000000, P_PLL0, 1, 127, 382 },
2290 { }
2291 };
2292
2293 static struct clk_dyn_rcg gmac_core1_src = {
2294 .ns_reg[0] = 0x3cac,
2295 .ns_reg[1] = 0x3cb0,
2296 .md_reg[0] = 0x3ca4,
2297 .md_reg[1] = 0x3ca8,
2298 .bank_reg = 0x3ca0,
2299 .mn[0] = {
2300 .mnctr_en_bit = 8,
2301 .mnctr_reset_bit = 7,
2302 .mnctr_mode_shift = 5,
2303 .n_val_shift = 16,
2304 .m_val_shift = 16,
2305 .width = 8,
2306 },
2307 .mn[1] = {
2308 .mnctr_en_bit = 8,
2309 .mnctr_reset_bit = 7,
2310 .mnctr_mode_shift = 5,
2311 .n_val_shift = 16,
2312 .m_val_shift = 16,
2313 .width = 8,
2314 },
2315 .s[0] = {
2316 .src_sel_shift = 0,
2317 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2318 },
2319 .s[1] = {
2320 .src_sel_shift = 0,
2321 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2322 },
2323 .p[0] = {
2324 .pre_div_shift = 3,
2325 .pre_div_width = 2,
2326 },
2327 .p[1] = {
2328 .pre_div_shift = 3,
2329 .pre_div_width = 2,
2330 },
2331 .mux_sel_bit = 0,
2332 .freq_tbl = clk_tbl_gmac,
2333 .clkr = {
2334 .enable_reg = 0x3ca0,
2335 .enable_mask = BIT(1),
2336 .hw.init = &(struct clk_init_data){
2337 .name = "gmac_core1_src",
2338 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2339 .num_parents = 5,
2340 .ops = &clk_dyn_rcg_ops,
2341 },
2342 },
2343 };
2344
2345 static struct clk_branch gmac_core1_clk = {
2346 .halt_reg = 0x3c20,
2347 .halt_bit = 4,
2348 .hwcg_reg = 0x3cb4,
2349 .hwcg_bit = 6,
2350 .clkr = {
2351 .enable_reg = 0x3cb4,
2352 .enable_mask = BIT(4),
2353 .hw.init = &(struct clk_init_data){
2354 .name = "gmac_core1_clk",
2355 .parent_names = (const char *[]){
2356 "gmac_core1_src",
2357 },
2358 .num_parents = 1,
2359 .ops = &clk_branch_ops,
2360 .flags = CLK_SET_RATE_PARENT,
2361 },
2362 },
2363 };
2364
2365 static struct clk_dyn_rcg gmac_core2_src = {
2366 .ns_reg[0] = 0x3ccc,
2367 .ns_reg[1] = 0x3cd0,
2368 .md_reg[0] = 0x3cc4,
2369 .md_reg[1] = 0x3cc8,
2370 .bank_reg = 0x3ca0,
2371 .mn[0] = {
2372 .mnctr_en_bit = 8,
2373 .mnctr_reset_bit = 7,
2374 .mnctr_mode_shift = 5,
2375 .n_val_shift = 16,
2376 .m_val_shift = 16,
2377 .width = 8,
2378 },
2379 .mn[1] = {
2380 .mnctr_en_bit = 8,
2381 .mnctr_reset_bit = 7,
2382 .mnctr_mode_shift = 5,
2383 .n_val_shift = 16,
2384 .m_val_shift = 16,
2385 .width = 8,
2386 },
2387 .s[0] = {
2388 .src_sel_shift = 0,
2389 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2390 },
2391 .s[1] = {
2392 .src_sel_shift = 0,
2393 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2394 },
2395 .p[0] = {
2396 .pre_div_shift = 3,
2397 .pre_div_width = 2,
2398 },
2399 .p[1] = {
2400 .pre_div_shift = 3,
2401 .pre_div_width = 2,
2402 },
2403 .mux_sel_bit = 0,
2404 .freq_tbl = clk_tbl_gmac,
2405 .clkr = {
2406 .enable_reg = 0x3cc0,
2407 .enable_mask = BIT(1),
2408 .hw.init = &(struct clk_init_data){
2409 .name = "gmac_core2_src",
2410 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2411 .num_parents = 5,
2412 .ops = &clk_dyn_rcg_ops,
2413 },
2414 },
2415 };
2416
2417 static struct clk_branch gmac_core2_clk = {
2418 .halt_reg = 0x3c20,
2419 .halt_bit = 5,
2420 .hwcg_reg = 0x3cd4,
2421 .hwcg_bit = 6,
2422 .clkr = {
2423 .enable_reg = 0x3cd4,
2424 .enable_mask = BIT(4),
2425 .hw.init = &(struct clk_init_data){
2426 .name = "gmac_core2_clk",
2427 .parent_names = (const char *[]){
2428 "gmac_core2_src",
2429 },
2430 .num_parents = 1,
2431 .ops = &clk_branch_ops,
2432 .flags = CLK_SET_RATE_PARENT,
2433 },
2434 },
2435 };
2436
2437 static struct clk_dyn_rcg gmac_core3_src = {
2438 .ns_reg[0] = 0x3cec,
2439 .ns_reg[1] = 0x3cf0,
2440 .md_reg[0] = 0x3ce4,
2441 .md_reg[1] = 0x3ce8,
2442 .bank_reg = 0x3ce0,
2443 .mn[0] = {
2444 .mnctr_en_bit = 8,
2445 .mnctr_reset_bit = 7,
2446 .mnctr_mode_shift = 5,
2447 .n_val_shift = 16,
2448 .m_val_shift = 16,
2449 .width = 8,
2450 },
2451 .mn[1] = {
2452 .mnctr_en_bit = 8,
2453 .mnctr_reset_bit = 7,
2454 .mnctr_mode_shift = 5,
2455 .n_val_shift = 16,
2456 .m_val_shift = 16,
2457 .width = 8,
2458 },
2459 .s[0] = {
2460 .src_sel_shift = 0,
2461 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2462 },
2463 .s[1] = {
2464 .src_sel_shift = 0,
2465 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2466 },
2467 .p[0] = {
2468 .pre_div_shift = 3,
2469 .pre_div_width = 2,
2470 },
2471 .p[1] = {
2472 .pre_div_shift = 3,
2473 .pre_div_width = 2,
2474 },
2475 .mux_sel_bit = 0,
2476 .freq_tbl = clk_tbl_gmac,
2477 .clkr = {
2478 .enable_reg = 0x3ce0,
2479 .enable_mask = BIT(1),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "gmac_core3_src",
2482 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2483 .num_parents = 5,
2484 .ops = &clk_dyn_rcg_ops,
2485 },
2486 },
2487 };
2488
2489 static struct clk_branch gmac_core3_clk = {
2490 .halt_reg = 0x3c20,
2491 .halt_bit = 6,
2492 .hwcg_reg = 0x3cf4,
2493 .hwcg_bit = 6,
2494 .clkr = {
2495 .enable_reg = 0x3cf4,
2496 .enable_mask = BIT(4),
2497 .hw.init = &(struct clk_init_data){
2498 .name = "gmac_core3_clk",
2499 .parent_names = (const char *[]){
2500 "gmac_core3_src",
2501 },
2502 .num_parents = 1,
2503 .ops = &clk_branch_ops,
2504 .flags = CLK_SET_RATE_PARENT,
2505 },
2506 },
2507 };
2508
2509 static struct clk_dyn_rcg gmac_core4_src = {
2510 .ns_reg[0] = 0x3d0c,
2511 .ns_reg[1] = 0x3d10,
2512 .md_reg[0] = 0x3d04,
2513 .md_reg[1] = 0x3d08,
2514 .bank_reg = 0x3d00,
2515 .mn[0] = {
2516 .mnctr_en_bit = 8,
2517 .mnctr_reset_bit = 7,
2518 .mnctr_mode_shift = 5,
2519 .n_val_shift = 16,
2520 .m_val_shift = 16,
2521 .width = 8,
2522 },
2523 .mn[1] = {
2524 .mnctr_en_bit = 8,
2525 .mnctr_reset_bit = 7,
2526 .mnctr_mode_shift = 5,
2527 .n_val_shift = 16,
2528 .m_val_shift = 16,
2529 .width = 8,
2530 },
2531 .s[0] = {
2532 .src_sel_shift = 0,
2533 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2534 },
2535 .s[1] = {
2536 .src_sel_shift = 0,
2537 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2538 },
2539 .p[0] = {
2540 .pre_div_shift = 3,
2541 .pre_div_width = 2,
2542 },
2543 .p[1] = {
2544 .pre_div_shift = 3,
2545 .pre_div_width = 2,
2546 },
2547 .mux_sel_bit = 0,
2548 .freq_tbl = clk_tbl_gmac,
2549 .clkr = {
2550 .enable_reg = 0x3d00,
2551 .enable_mask = BIT(1),
2552 .hw.init = &(struct clk_init_data){
2553 .name = "gmac_core4_src",
2554 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2555 .num_parents = 5,
2556 .ops = &clk_dyn_rcg_ops,
2557 },
2558 },
2559 };
2560
2561 static struct clk_branch gmac_core4_clk = {
2562 .halt_reg = 0x3c20,
2563 .halt_bit = 7,
2564 .hwcg_reg = 0x3d14,
2565 .hwcg_bit = 6,
2566 .clkr = {
2567 .enable_reg = 0x3d14,
2568 .enable_mask = BIT(4),
2569 .hw.init = &(struct clk_init_data){
2570 .name = "gmac_core4_clk",
2571 .parent_names = (const char *[]){
2572 "gmac_core4_src",
2573 },
2574 .num_parents = 1,
2575 .ops = &clk_branch_ops,
2576 .flags = CLK_SET_RATE_PARENT,
2577 },
2578 },
2579 };
2580
2581 static const struct freq_tbl clk_tbl_nss_tcm[] = {
2582 { 266000000, P_PLL0, 3, 0, 0 },
2583 { 400000000, P_PLL0, 2, 0, 0 },
2584 { }
2585 };
2586
2587 static struct clk_dyn_rcg nss_tcm_src = {
2588 .ns_reg[0] = 0x3dc4,
2589 .ns_reg[1] = 0x3dc8,
2590 .bank_reg = 0x3dc0,
2591 .s[0] = {
2592 .src_sel_shift = 0,
2593 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2594 },
2595 .s[1] = {
2596 .src_sel_shift = 0,
2597 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2598 },
2599 .p[0] = {
2600 .pre_div_shift = 3,
2601 .pre_div_width = 4,
2602 },
2603 .p[1] = {
2604 .pre_div_shift = 3,
2605 .pre_div_width = 4,
2606 },
2607 .mux_sel_bit = 0,
2608 .freq_tbl = clk_tbl_nss_tcm,
2609 .clkr = {
2610 .enable_reg = 0x3dc0,
2611 .enable_mask = BIT(1),
2612 .hw.init = &(struct clk_init_data){
2613 .name = "nss_tcm_src",
2614 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2615 .num_parents = 5,
2616 .ops = &clk_dyn_rcg_ops,
2617 },
2618 },
2619 };
2620
2621 static struct clk_branch nss_tcm_clk = {
2622 .halt_reg = 0x3c20,
2623 .halt_bit = 14,
2624 .clkr = {
2625 .enable_reg = 0x3dd0,
2626 .enable_mask = BIT(6) | BIT(4),
2627 .hw.init = &(struct clk_init_data){
2628 .name = "nss_tcm_clk",
2629 .parent_names = (const char *[]){
2630 "nss_tcm_src",
2631 },
2632 .num_parents = 1,
2633 .ops = &clk_branch_ops,
2634 .flags = CLK_SET_RATE_PARENT,
2635 },
2636 },
2637 };
2638
2639 static const struct freq_tbl clk_tbl_nss[] = {
2640 { 110000000, P_PLL18, 1, 1, 5 },
2641 { 275000000, P_PLL18, 2, 0, 0 },
2642 { 550000000, P_PLL18, 1, 0, 0 },
2643 { 733000000, P_PLL18, 1, 0, 0 },
2644 { }
2645 };
2646
2647 static struct clk_dyn_rcg ubi32_core1_src_clk = {
2648 .ns_reg[0] = 0x3d2c,
2649 .ns_reg[1] = 0x3d30,
2650 .md_reg[0] = 0x3d24,
2651 .md_reg[1] = 0x3d28,
2652 .bank_reg = 0x3d20,
2653 .mn[0] = {
2654 .mnctr_en_bit = 8,
2655 .mnctr_reset_bit = 7,
2656 .mnctr_mode_shift = 5,
2657 .n_val_shift = 16,
2658 .m_val_shift = 16,
2659 .width = 8,
2660 },
2661 .mn[1] = {
2662 .mnctr_en_bit = 8,
2663 .mnctr_reset_bit = 7,
2664 .mnctr_mode_shift = 5,
2665 .n_val_shift = 16,
2666 .m_val_shift = 16,
2667 .width = 8,
2668 },
2669 .s[0] = {
2670 .src_sel_shift = 0,
2671 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2672 },
2673 .s[1] = {
2674 .src_sel_shift = 0,
2675 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2676 },
2677 .p[0] = {
2678 .pre_div_shift = 3,
2679 .pre_div_width = 2,
2680 },
2681 .p[1] = {
2682 .pre_div_shift = 3,
2683 .pre_div_width = 2,
2684 },
2685 .mux_sel_bit = 0,
2686 .freq_tbl = clk_tbl_nss,
2687 .clkr = {
2688 .enable_reg = 0x3d20,
2689 .enable_mask = BIT(1),
2690 .hw.init = &(struct clk_init_data){
2691 .name = "ubi32_core1_src_clk",
2692 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2693 .num_parents = 5,
2694 .ops = &clk_dyn_rcg_ops,
2695 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2696 },
2697 },
2698 };
2699
2700 static struct clk_dyn_rcg ubi32_core2_src_clk = {
2701 .ns_reg[0] = 0x3d4c,
2702 .ns_reg[1] = 0x3d50,
2703 .md_reg[0] = 0x3d44,
2704 .md_reg[1] = 0x3d48,
2705 .bank_reg = 0x3d40,
2706 .mn[0] = {
2707 .mnctr_en_bit = 8,
2708 .mnctr_reset_bit = 7,
2709 .mnctr_mode_shift = 5,
2710 .n_val_shift = 16,
2711 .m_val_shift = 16,
2712 .width = 8,
2713 },
2714 .mn[1] = {
2715 .mnctr_en_bit = 8,
2716 .mnctr_reset_bit = 7,
2717 .mnctr_mode_shift = 5,
2718 .n_val_shift = 16,
2719 .m_val_shift = 16,
2720 .width = 8,
2721 },
2722 .s[0] = {
2723 .src_sel_shift = 0,
2724 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2725 },
2726 .s[1] = {
2727 .src_sel_shift = 0,
2728 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2729 },
2730 .p[0] = {
2731 .pre_div_shift = 3,
2732 .pre_div_width = 2,
2733 },
2734 .p[1] = {
2735 .pre_div_shift = 3,
2736 .pre_div_width = 2,
2737 },
2738 .mux_sel_bit = 0,
2739 .freq_tbl = clk_tbl_nss,
2740 .clkr = {
2741 .enable_reg = 0x3d40,
2742 .enable_mask = BIT(1),
2743 .hw.init = &(struct clk_init_data){
2744 .name = "ubi32_core2_src_clk",
2745 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2746 .num_parents = 5,
2747 .ops = &clk_dyn_rcg_ops,
2748 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2749 },
2750 },
2751 };
2752
2753 static struct clk_regmap *gcc_ipq806x_clks[] = {
2754 [PLL0] = &pll0.clkr,
2755 [PLL0_VOTE] = &pll0_vote,
2756 [PLL3] = &pll3.clkr,
2757 [PLL4_VOTE] = &pll4_vote,
2758 [PLL8] = &pll8.clkr,
2759 [PLL8_VOTE] = &pll8_vote,
2760 [PLL14] = &pll14.clkr,
2761 [PLL14_VOTE] = &pll14_vote,
2762 [PLL18] = &pll18.clkr,
2763 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2764 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2765 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2766 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2767 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2768 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2769 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2770 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2771 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2772 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2773 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2774 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2775 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2776 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2777 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2778 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2779 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2780 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2781 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2782 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2783 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2784 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2785 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2786 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2787 [GP0_SRC] = &gp0_src.clkr,
2788 [GP0_CLK] = &gp0_clk.clkr,
2789 [GP1_SRC] = &gp1_src.clkr,
2790 [GP1_CLK] = &gp1_clk.clkr,
2791 [GP2_SRC] = &gp2_src.clkr,
2792 [GP2_CLK] = &gp2_clk.clkr,
2793 [PMEM_A_CLK] = &pmem_clk.clkr,
2794 [PRNG_SRC] = &prng_src.clkr,
2795 [PRNG_CLK] = &prng_clk.clkr,
2796 [SDC1_SRC] = &sdc1_src.clkr,
2797 [SDC1_CLK] = &sdc1_clk.clkr,
2798 [SDC3_SRC] = &sdc3_src.clkr,
2799 [SDC3_CLK] = &sdc3_clk.clkr,
2800 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2801 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2802 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2803 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2804 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2805 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2806 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2807 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2808 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2809 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2810 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2811 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2812 [ADM0_CLK] = &adm0_clk.clkr,
2813 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2814 [PCIE_A_CLK] = &pcie_a_clk.clkr,
2815 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2816 [PCIE_H_CLK] = &pcie_h_clk.clkr,
2817 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2818 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2819 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2820 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2821 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2822 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2823 [SATA_H_CLK] = &sata_h_clk.clkr,
2824 [SATA_CLK_SRC] = &sata_ref_src.clkr,
2825 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2826 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2827 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2828 [SATA_A_CLK] = &sata_a_clk.clkr,
2829 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2830 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2831 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2832 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2833 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2834 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2835 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2836 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2837 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2838 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2839 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2840 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2841 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2842 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2843 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2844 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2845 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2846 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2847 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2848 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2849 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2850 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2851 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2852 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2853 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2854 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2855 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2856 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2857 [EBI2_CLK] = &ebi2_clk.clkr,
2858 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
2859 [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
2860 [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
2861 [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
2862 [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
2863 [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
2864 [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
2865 [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
2866 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
2867 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
2868 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
2869 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
2870 [NSSTCM_CLK] = &nss_tcm_clk.clkr,
2871 [PLL9] = &hfpll0.clkr,
2872 [PLL10] = &hfpll1.clkr,
2873 [PLL12] = &hfpll_l2.clkr,
2874 };
2875
2876 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2877 [QDSS_STM_RESET] = { 0x2060, 6 },
2878 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2879 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2880 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2881 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2882 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2883 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2884 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2885 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2886 [ADM0_C2_RESET] = { 0x220c, 4 },
2887 [ADM0_C1_RESET] = { 0x220c, 3 },
2888 [ADM0_C0_RESET] = { 0x220c, 2 },
2889 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2890 [ADM0_RESET] = { 0x220c, 0 },
2891 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2892 [QDSS_POR_RESET] = { 0x2260, 4 },
2893 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2894 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2895 [QDSS_AXI_RESET] = { 0x2260, 1 },
2896 [QDSS_DBG_RESET] = { 0x2260, 0 },
2897 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2898 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2899 [PCIE_EXT_RESET] = { 0x22dc, 6 },
2900 [PCIE_PHY_RESET] = { 0x22dc, 5 },
2901 [PCIE_PCI_RESET] = { 0x22dc, 4 },
2902 [PCIE_POR_RESET] = { 0x22dc, 3 },
2903 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2904 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2905 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2906 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2907 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2908 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2909 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2910 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2911 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2912 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2913 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2914 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2915 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2916 [PPSS_PROC_RESET] = { 0x2594, 1 },
2917 [PPSS_RESET] = { 0x2594, 0 },
2918 [DMA_BAM_RESET] = { 0x25c0, 7 },
2919 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2920 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2921 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2922 [TSIF_H_RESET] = { 0x2700, 7 },
2923 [CE1_H_RESET] = { 0x2720, 7 },
2924 [CE1_CORE_RESET] = { 0x2724, 7 },
2925 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2926 [CE2_H_RESET] = { 0x2740, 7 },
2927 [CE2_CORE_RESET] = { 0x2744, 7 },
2928 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2929 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2930 [RPM_PROC_RESET] = { 0x27c0, 7 },
2931 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2932 [SDC1_RESET] = { 0x2830, 0 },
2933 [SDC2_RESET] = { 0x2850, 0 },
2934 [SDC3_RESET] = { 0x2870, 0 },
2935 [SDC4_RESET] = { 0x2890, 0 },
2936 [USB_HS1_RESET] = { 0x2910, 0 },
2937 [USB_HSIC_RESET] = { 0x2934, 0 },
2938 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2939 [USB_FS1_RESET] = { 0x2974, 0 },
2940 [GSBI1_RESET] = { 0x29dc, 0 },
2941 [GSBI2_RESET] = { 0x29fc, 0 },
2942 [GSBI3_RESET] = { 0x2a1c, 0 },
2943 [GSBI4_RESET] = { 0x2a3c, 0 },
2944 [GSBI5_RESET] = { 0x2a5c, 0 },
2945 [GSBI6_RESET] = { 0x2a7c, 0 },
2946 [GSBI7_RESET] = { 0x2a9c, 0 },
2947 [SPDM_RESET] = { 0x2b6c, 0 },
2948 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2949 [TLMM_H_RESET] = { 0x2ba0, 7 },
2950 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2951 [SATA_RESET] = { 0x2c1c, 0 },
2952 [TSSC_RESET] = { 0x2ca0, 7 },
2953 [PDM_RESET] = { 0x2cc0, 12 },
2954 [MPM_H_RESET] = { 0x2da0, 7 },
2955 [MPM_RESET] = { 0x2da4, 0 },
2956 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2957 [PRNG_RESET] = { 0x2e80, 12 },
2958 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2959 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2960 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2961 [PCIE_1_M_RESET] = { 0x3a98, 1 },
2962 [PCIE_1_S_RESET] = { 0x3a98, 0 },
2963 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2964 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2965 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2966 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2967 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2968 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2969 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2970 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2971 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2972 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2973 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2974 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2975 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2976 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2977 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2978 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2979 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2980 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2981 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2982 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2983 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2984 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2985 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2986 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2987 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2988 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2989 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2990 [NSSFB0_RESET] = { 0x3b60, 6 },
2991 [NSSFB1_RESET] = { 0x3b60, 7 },
2992 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
2993 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
2994 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
2995 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
2996 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
2997 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
2998 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
2999 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
3000 [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
3001 [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
3002 [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
3003 [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
3004 [GMAC_AHB_RESET] = { 0x3e24, 0 },
3005 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
3006 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
3007 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
3008 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
3009 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
3010 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
3011 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
3012 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
3013 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
3014 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
3015 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
3016 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
3017 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
3018 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
3019 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
3020 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
3021 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
3022 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
3023 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
3024 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
3025 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
3026 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
3027 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
3028 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
3029 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
3030 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
3031 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
3032 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
3033 [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
3034 };
3035
3036 static const struct regmap_config gcc_ipq806x_regmap_config = {
3037 .reg_bits = 32,
3038 .reg_stride = 4,
3039 .val_bits = 32,
3040 .max_register = 0x3e40,
3041 .fast_io = true,
3042 };
3043
3044 static const struct qcom_cc_desc gcc_ipq806x_desc = {
3045 .config = &gcc_ipq806x_regmap_config,
3046 .clks = gcc_ipq806x_clks,
3047 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
3048 .resets = gcc_ipq806x_resets,
3049 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
3050 };
3051
3052 static const struct of_device_id gcc_ipq806x_match_table[] = {
3053 { .compatible = "qcom,gcc-ipq8064" },
3054 { }
3055 };
3056 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
3057
3058 static int gcc_ipq806x_probe(struct platform_device *pdev)
3059 {
3060 struct device *dev = &pdev->dev;
3061 struct regmap *regmap;
3062 int ret;
3063
3064 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
3065 if (ret)
3066 return ret;
3067
3068 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
3069 if (ret)
3070 return ret;
3071
3072 ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
3073 if (ret)
3074 return ret;
3075
3076 regmap = dev_get_regmap(dev, NULL);
3077 if (!regmap)
3078 return -ENODEV;
3079
3080
3081 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
3082 regmap_write(regmap, 0x31b0, 0x3080);
3083
3084
3085 regmap_write(regmap, 0x3cb8, 8);
3086 regmap_write(regmap, 0x3cd8, 8);
3087 regmap_write(regmap, 0x3cf8, 8);
3088 regmap_write(regmap, 0x3d18, 8);
3089
3090 return 0;
3091 }
3092
3093 static struct platform_driver gcc_ipq806x_driver = {
3094 .probe = gcc_ipq806x_probe,
3095 .driver = {
3096 .name = "gcc-ipq806x",
3097 .of_match_table = gcc_ipq806x_match_table,
3098 },
3099 };
3100
3101 static int __init gcc_ipq806x_init(void)
3102 {
3103 return platform_driver_register(&gcc_ipq806x_driver);
3104 }
3105 core_initcall(gcc_ipq806x_init);
3106
3107 static void __exit gcc_ipq806x_exit(void)
3108 {
3109 platform_driver_unregister(&gcc_ipq806x_driver);
3110 }
3111 module_exit(gcc_ipq806x_exit);
3112
3113 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3114 MODULE_LICENSE("GPL v2");
3115 MODULE_ALIAS("platform:gcc-ipq806x");