This source file includes following definitions.
- gcc_sm8150_probe
- gcc_sm8150_init
- gcc_sm8150_exit
1
2
3
4 #include <linux/kernel.h>
5 #include <linux/bitops.h>
6 #include <linux/err.h>
7 #include <linux/platform_device.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/clk-provider.h>
12 #include <linux/regmap.h>
13 #include <linux/reset-controller.h>
14
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16
17 #include "common.h"
18 #include "clk-alpha-pll.h"
19 #include "clk-branch.h"
20 #include "clk-pll.h"
21 #include "clk-rcg.h"
22 #include "clk-regmap.h"
23 #include "reset.h"
24
25 enum {
26 P_BI_TCXO,
27 P_AUD_REF_CLK,
28 P_CORE_BI_PLL_TEST_SE,
29 P_GPLL0_OUT_EVEN,
30 P_GPLL0_OUT_MAIN,
31 P_GPLL7_OUT_MAIN,
32 P_GPLL9_OUT_MAIN,
33 P_SLEEP_CLK,
34 };
35
36 static const struct pll_vco trion_vco[] = {
37 { 249600000, 2000000000, 0 },
38 };
39
40 static struct clk_alpha_pll gpll0 = {
41 .offset = 0x0,
42 .vco_table = trion_vco,
43 .num_vco = ARRAY_SIZE(trion_vco),
44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
45 .clkr = {
46 .enable_reg = 0x52000,
47 .enable_mask = BIT(0),
48 .hw.init = &(struct clk_init_data){
49 .name = "gpll0",
50 .parent_data = &(const struct clk_parent_data){
51 .fw_name = "bi_tcxo",
52 .name = "bi_tcxo",
53 },
54 .num_parents = 1,
55 .ops = &clk_trion_fixed_pll_ops,
56 },
57 },
58 };
59
60 static const struct clk_div_table post_div_table_trion_even[] = {
61 { 0x0, 1 },
62 { 0x1, 2 },
63 { 0x3, 4 },
64 { 0x7, 8 },
65 { }
66 };
67
68 static struct clk_alpha_pll_postdiv gpll0_out_even = {
69 .offset = 0x0,
70 .post_div_shift = 8,
71 .post_div_table = post_div_table_trion_even,
72 .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
74 .width = 4,
75 .clkr.hw.init = &(struct clk_init_data){
76 .name = "gpll0_out_even",
77 .parent_data = &(const struct clk_parent_data){
78 .hw = &gpll0.clkr.hw,
79 },
80 .num_parents = 1,
81 .ops = &clk_trion_pll_postdiv_ops,
82 },
83 };
84
85 static struct clk_alpha_pll gpll7 = {
86 .offset = 0x1a000,
87 .vco_table = trion_vco,
88 .num_vco = ARRAY_SIZE(trion_vco),
89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
90 .clkr = {
91 .enable_reg = 0x52000,
92 .enable_mask = BIT(7),
93 .hw.init = &(struct clk_init_data){
94 .name = "gpll7",
95 .parent_data = &(const struct clk_parent_data){
96 .fw_name = "bi_tcxo",
97 .name = "bi_tcxo",
98 },
99 .num_parents = 1,
100 .ops = &clk_trion_fixed_pll_ops,
101 },
102 },
103 };
104
105 static struct clk_alpha_pll gpll9 = {
106 .offset = 0x1c000,
107 .vco_table = trion_vco,
108 .num_vco = ARRAY_SIZE(trion_vco),
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
110 .clkr = {
111 .enable_reg = 0x52000,
112 .enable_mask = BIT(9),
113 .hw.init = &(struct clk_init_data){
114 .name = "gpll9",
115 .parent_data = &(const struct clk_parent_data){
116 .fw_name = "bi_tcxo",
117 .name = "bi_tcxo",
118 },
119 .num_parents = 1,
120 .ops = &clk_trion_fixed_pll_ops,
121 },
122 },
123 };
124
125 static const struct parent_map gcc_parent_map_0[] = {
126 { P_BI_TCXO, 0 },
127 { P_GPLL0_OUT_MAIN, 1 },
128 { P_GPLL0_OUT_EVEN, 6 },
129 { P_CORE_BI_PLL_TEST_SE, 7 },
130 };
131
132 static const struct clk_parent_data gcc_parents_0[] = {
133 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
134 { .hw = &gpll0.clkr.hw },
135 { .hw = &gpll0_out_even.clkr.hw },
136 { .fw_name = "core_bi_pll_test_se" },
137 };
138
139 static const struct parent_map gcc_parent_map_1[] = {
140 { P_BI_TCXO, 0 },
141 { P_GPLL0_OUT_MAIN, 1 },
142 { P_SLEEP_CLK, 5 },
143 { P_GPLL0_OUT_EVEN, 6 },
144 { P_CORE_BI_PLL_TEST_SE, 7 },
145 };
146
147 static const struct clk_parent_data gcc_parents_1[] = {
148 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
149 { .hw = &gpll0.clkr.hw },
150 { .fw_name = "sleep_clk", .name = "sleep_clk" },
151 { .hw = &gpll0_out_even.clkr.hw },
152 { .fw_name = "core_bi_pll_test_se" },
153 };
154
155 static const struct parent_map gcc_parent_map_2[] = {
156 { P_BI_TCXO, 0 },
157 { P_SLEEP_CLK, 5 },
158 { P_CORE_BI_PLL_TEST_SE, 7 },
159 };
160
161 static const struct clk_parent_data gcc_parents_2[] = {
162 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
163 { .fw_name = "sleep_clk", .name = "sleep_clk" },
164 { .fw_name = "core_bi_pll_test_se" },
165 };
166
167 static const struct parent_map gcc_parent_map_3[] = {
168 { P_BI_TCXO, 0 },
169 { P_GPLL0_OUT_MAIN, 1 },
170 { P_CORE_BI_PLL_TEST_SE, 7 },
171 };
172
173 static const struct clk_parent_data gcc_parents_3[] = {
174 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
175 { .hw = &gpll0.clkr.hw },
176 { .fw_name = "core_bi_pll_test_se"},
177 };
178
179 static const struct parent_map gcc_parent_map_4[] = {
180 { P_BI_TCXO, 0 },
181 { P_CORE_BI_PLL_TEST_SE, 7 },
182 };
183
184 static const struct clk_parent_data gcc_parents_4[] = {
185 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
186 { .fw_name = "core_bi_pll_test_se" },
187 };
188
189 static const struct parent_map gcc_parent_map_5[] = {
190 { P_BI_TCXO, 0 },
191 { P_GPLL0_OUT_MAIN, 1 },
192 { P_GPLL7_OUT_MAIN, 3 },
193 { P_GPLL0_OUT_EVEN, 6 },
194 { P_CORE_BI_PLL_TEST_SE, 7 },
195 };
196
197 static const struct clk_parent_data gcc_parents_5[] = {
198 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
199 { .hw = &gpll0.clkr.hw },
200 { .hw = &gpll7.clkr.hw },
201 { .hw = &gpll0_out_even.clkr.hw },
202 { .fw_name = "core_bi_pll_test_se" },
203 };
204
205 static const struct parent_map gcc_parent_map_6[] = {
206 { P_BI_TCXO, 0 },
207 { P_GPLL0_OUT_MAIN, 1 },
208 { P_GPLL9_OUT_MAIN, 2 },
209 { P_GPLL0_OUT_EVEN, 6 },
210 { P_CORE_BI_PLL_TEST_SE, 7 },
211 };
212
213 static const struct clk_parent_data gcc_parents_6[] = {
214 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
215 { .hw = &gpll0.clkr.hw },
216 { .hw = &gpll9.clkr.hw },
217 { .hw = &gpll0_out_even.clkr.hw },
218 { .fw_name = "core_bi_pll_test_se" },
219 };
220
221 static const struct parent_map gcc_parent_map_7[] = {
222 { P_BI_TCXO, 0 },
223 { P_GPLL0_OUT_MAIN, 1 },
224 { P_AUD_REF_CLK, 2 },
225 { P_GPLL0_OUT_EVEN, 6 },
226 { P_CORE_BI_PLL_TEST_SE, 7 },
227 };
228
229 static const struct clk_parent_data gcc_parents_7[] = {
230 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
231 { .hw = &gpll0.clkr.hw },
232 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
233 { .hw = &gpll0_out_even.clkr.hw },
234 { .fw_name = "core_bi_pll_test_se" },
235 };
236
237 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
238 F(19200000, P_BI_TCXO, 1, 0, 0),
239 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
240 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
241 { }
242 };
243
244 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
245 .cmd_rcgr = 0x48014,
246 .mnd_width = 0,
247 .hid_width = 5,
248 .parent_map = gcc_parent_map_0,
249 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "gcc_cpuss_ahb_clk_src",
252 .parent_data = gcc_parents_0,
253 .num_parents = 4,
254 .flags = CLK_SET_RATE_PARENT,
255 .ops = &clk_rcg2_ops,
256 },
257 };
258
259 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
260 F(19200000, P_BI_TCXO, 1, 0, 0),
261 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
262 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
263 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
264 { }
265 };
266
267 static struct clk_rcg2 gcc_emac_ptp_clk_src = {
268 .cmd_rcgr = 0x6038,
269 .mnd_width = 0,
270 .hid_width = 5,
271 .parent_map = gcc_parent_map_5,
272 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
273 .clkr.hw.init = &(struct clk_init_data){
274 .name = "gcc_emac_ptp_clk_src",
275 .parent_data = gcc_parents_5,
276 .num_parents = 5,
277 .flags = CLK_SET_RATE_PARENT,
278 .ops = &clk_rcg2_ops,
279 },
280 };
281
282 static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
283 F(2500000, P_BI_TCXO, 1, 25, 192),
284 F(5000000, P_BI_TCXO, 1, 25, 96),
285 F(19200000, P_BI_TCXO, 1, 0, 0),
286 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
287 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
288 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
289 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
290 { }
291 };
292
293 static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
294 .cmd_rcgr = 0x601c,
295 .mnd_width = 8,
296 .hid_width = 5,
297 .parent_map = gcc_parent_map_5,
298 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
299 .clkr.hw.init = &(struct clk_init_data){
300 .name = "gcc_emac_rgmii_clk_src",
301 .parent_data = gcc_parents_5,
302 .num_parents = 5,
303 .flags = CLK_SET_RATE_PARENT,
304 .ops = &clk_rcg2_ops,
305 },
306 };
307
308 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
309 F(19200000, P_BI_TCXO, 1, 0, 0),
310 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
311 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
312 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
313 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
314 { }
315 };
316
317 static struct clk_rcg2 gcc_gp1_clk_src = {
318 .cmd_rcgr = 0x64004,
319 .mnd_width = 8,
320 .hid_width = 5,
321 .parent_map = gcc_parent_map_1,
322 .freq_tbl = ftbl_gcc_gp1_clk_src,
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "gcc_gp1_clk_src",
325 .parent_data = gcc_parents_1,
326 .num_parents = 5,
327 .flags = CLK_SET_RATE_PARENT,
328 .ops = &clk_rcg2_ops,
329 },
330 };
331
332 static struct clk_rcg2 gcc_gp2_clk_src = {
333 .cmd_rcgr = 0x65004,
334 .mnd_width = 8,
335 .hid_width = 5,
336 .parent_map = gcc_parent_map_1,
337 .freq_tbl = ftbl_gcc_gp1_clk_src,
338 .clkr.hw.init = &(struct clk_init_data){
339 .name = "gcc_gp2_clk_src",
340 .parent_data = gcc_parents_1,
341 .num_parents = 5,
342 .flags = CLK_SET_RATE_PARENT,
343 .ops = &clk_rcg2_ops,
344 },
345 };
346
347 static struct clk_rcg2 gcc_gp3_clk_src = {
348 .cmd_rcgr = 0x66004,
349 .mnd_width = 8,
350 .hid_width = 5,
351 .parent_map = gcc_parent_map_1,
352 .freq_tbl = ftbl_gcc_gp1_clk_src,
353 .clkr.hw.init = &(struct clk_init_data){
354 .name = "gcc_gp3_clk_src",
355 .parent_data = gcc_parents_1,
356 .num_parents = 5,
357 .flags = CLK_SET_RATE_PARENT,
358 .ops = &clk_rcg2_ops,
359 },
360 };
361
362 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
363 F(9600000, P_BI_TCXO, 2, 0, 0),
364 F(19200000, P_BI_TCXO, 1, 0, 0),
365 { }
366 };
367
368 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
369 .cmd_rcgr = 0x6b02c,
370 .mnd_width = 16,
371 .hid_width = 5,
372 .parent_map = gcc_parent_map_2,
373 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "gcc_pcie_0_aux_clk_src",
376 .parent_data = gcc_parents_2,
377 .num_parents = 3,
378 .flags = CLK_SET_RATE_PARENT,
379 .ops = &clk_rcg2_ops,
380 },
381 };
382
383 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
384 .cmd_rcgr = 0x8d02c,
385 .mnd_width = 16,
386 .hid_width = 5,
387 .parent_map = gcc_parent_map_2,
388 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
389 .clkr.hw.init = &(struct clk_init_data){
390 .name = "gcc_pcie_1_aux_clk_src",
391 .parent_data = gcc_parents_2,
392 .num_parents = 3,
393 .flags = CLK_SET_RATE_PARENT,
394 .ops = &clk_rcg2_ops,
395 },
396 };
397
398 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
399 F(19200000, P_BI_TCXO, 1, 0, 0),
400 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
401 { }
402 };
403
404 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
405 .cmd_rcgr = 0x6f014,
406 .mnd_width = 0,
407 .hid_width = 5,
408 .parent_map = gcc_parent_map_0,
409 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
410 .clkr.hw.init = &(struct clk_init_data){
411 .name = "gcc_pcie_phy_refgen_clk_src",
412 .parent_data = gcc_parents_0,
413 .num_parents = 4,
414 .flags = CLK_SET_RATE_PARENT,
415 .ops = &clk_rcg2_ops,
416 },
417 };
418
419 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
420 F(9600000, P_BI_TCXO, 2, 0, 0),
421 F(19200000, P_BI_TCXO, 1, 0, 0),
422 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
423 { }
424 };
425
426 static struct clk_rcg2 gcc_pdm2_clk_src = {
427 .cmd_rcgr = 0x33010,
428 .mnd_width = 0,
429 .hid_width = 5,
430 .parent_map = gcc_parent_map_0,
431 .freq_tbl = ftbl_gcc_pdm2_clk_src,
432 .clkr.hw.init = &(struct clk_init_data){
433 .name = "gcc_pdm2_clk_src",
434 .parent_data = gcc_parents_0,
435 .num_parents = 4,
436 .flags = CLK_SET_RATE_PARENT,
437 .ops = &clk_rcg2_ops,
438 },
439 };
440
441 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
442 F(19200000, P_BI_TCXO, 1, 0, 0),
443 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
444 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
445 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
446 { }
447 };
448
449 static struct clk_rcg2 gcc_qspi_core_clk_src = {
450 .cmd_rcgr = 0x4b008,
451 .mnd_width = 0,
452 .hid_width = 5,
453 .parent_map = gcc_parent_map_0,
454 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
455 .clkr.hw.init = &(struct clk_init_data){
456 .name = "gcc_qspi_core_clk_src",
457 .parent_data = gcc_parents_0,
458 .num_parents = 4,
459 .flags = CLK_SET_RATE_PARENT,
460 .ops = &clk_rcg2_ops,
461 },
462 };
463
464 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
465 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
466 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
467 F(19200000, P_BI_TCXO, 1, 0, 0),
468 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
469 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
470 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
471 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
472 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
473 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
474 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
475 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
476 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
477 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
478 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
479 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
480 { }
481 };
482
483 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
484 .cmd_rcgr = 0x17148,
485 .mnd_width = 16,
486 .hid_width = 5,
487 .parent_map = gcc_parent_map_0,
488 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
489 .clkr.hw.init = &(struct clk_init_data){
490 .name = "gcc_qupv3_wrap0_s0_clk_src",
491 .parent_data = gcc_parents_0,
492 .num_parents = 4,
493 .flags = CLK_SET_RATE_PARENT,
494 .ops = &clk_rcg2_ops,
495 },
496 };
497
498 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
499 .cmd_rcgr = 0x17278,
500 .mnd_width = 16,
501 .hid_width = 5,
502 .parent_map = gcc_parent_map_0,
503 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
504 .clkr.hw.init = &(struct clk_init_data){
505 .name = "gcc_qupv3_wrap0_s1_clk_src",
506 .parent_data = gcc_parents_0,
507 .num_parents = 4,
508 .flags = CLK_SET_RATE_PARENT,
509 .ops = &clk_rcg2_ops,
510 },
511 };
512
513 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
514 .cmd_rcgr = 0x173a8,
515 .mnd_width = 16,
516 .hid_width = 5,
517 .parent_map = gcc_parent_map_0,
518 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
519 .clkr.hw.init = &(struct clk_init_data){
520 .name = "gcc_qupv3_wrap0_s2_clk_src",
521 .parent_data = gcc_parents_0,
522 .num_parents = 4,
523 .flags = CLK_SET_RATE_PARENT,
524 .ops = &clk_rcg2_ops,
525 },
526 };
527
528 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
529 .cmd_rcgr = 0x174d8,
530 .mnd_width = 16,
531 .hid_width = 5,
532 .parent_map = gcc_parent_map_0,
533 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "gcc_qupv3_wrap0_s3_clk_src",
536 .parent_data = gcc_parents_0,
537 .num_parents = 4,
538 .flags = CLK_SET_RATE_PARENT,
539 .ops = &clk_rcg2_ops,
540 },
541 };
542
543 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
544 .cmd_rcgr = 0x17608,
545 .mnd_width = 16,
546 .hid_width = 5,
547 .parent_map = gcc_parent_map_0,
548 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
549 .clkr.hw.init = &(struct clk_init_data){
550 .name = "gcc_qupv3_wrap0_s4_clk_src",
551 .parent_data = gcc_parents_0,
552 .num_parents = 4,
553 .flags = CLK_SET_RATE_PARENT,
554 .ops = &clk_rcg2_ops,
555 },
556 };
557
558 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
559 .cmd_rcgr = 0x17738,
560 .mnd_width = 16,
561 .hid_width = 5,
562 .parent_map = gcc_parent_map_0,
563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
564 .clkr.hw.init = &(struct clk_init_data){
565 .name = "gcc_qupv3_wrap0_s5_clk_src",
566 .parent_data = gcc_parents_0,
567 .num_parents = 4,
568 .flags = CLK_SET_RATE_PARENT,
569 .ops = &clk_rcg2_ops,
570 },
571 };
572
573 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
574 .cmd_rcgr = 0x17868,
575 .mnd_width = 16,
576 .hid_width = 5,
577 .parent_map = gcc_parent_map_0,
578 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
579 .clkr.hw.init = &(struct clk_init_data){
580 .name = "gcc_qupv3_wrap0_s6_clk_src",
581 .parent_data = gcc_parents_0,
582 .num_parents = 4,
583 .flags = CLK_SET_RATE_PARENT,
584 .ops = &clk_rcg2_ops,
585 },
586 };
587
588 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
589 .cmd_rcgr = 0x17998,
590 .mnd_width = 16,
591 .hid_width = 5,
592 .parent_map = gcc_parent_map_0,
593 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
594 .clkr.hw.init = &(struct clk_init_data){
595 .name = "gcc_qupv3_wrap0_s7_clk_src",
596 .parent_data = gcc_parents_0,
597 .num_parents = 4,
598 .flags = CLK_SET_RATE_PARENT,
599 .ops = &clk_rcg2_ops,
600 },
601 };
602
603 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
604 .cmd_rcgr = 0x18148,
605 .mnd_width = 16,
606 .hid_width = 5,
607 .parent_map = gcc_parent_map_0,
608 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
609 .clkr.hw.init = &(struct clk_init_data){
610 .name = "gcc_qupv3_wrap1_s0_clk_src",
611 .parent_data = gcc_parents_0,
612 .num_parents = 4,
613 .flags = CLK_SET_RATE_PARENT,
614 .ops = &clk_rcg2_ops,
615 },
616 };
617
618 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
619 .cmd_rcgr = 0x18278,
620 .mnd_width = 16,
621 .hid_width = 5,
622 .parent_map = gcc_parent_map_0,
623 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
624 .clkr.hw.init = &(struct clk_init_data){
625 .name = "gcc_qupv3_wrap1_s1_clk_src",
626 .parent_data = gcc_parents_0,
627 .num_parents = 4,
628 .flags = CLK_SET_RATE_PARENT,
629 .ops = &clk_rcg2_ops,
630 },
631 };
632
633 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
634 .cmd_rcgr = 0x183a8,
635 .mnd_width = 16,
636 .hid_width = 5,
637 .parent_map = gcc_parent_map_0,
638 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
639 .clkr.hw.init = &(struct clk_init_data){
640 .name = "gcc_qupv3_wrap1_s2_clk_src",
641 .parent_data = gcc_parents_0,
642 .num_parents = 4,
643 .flags = CLK_SET_RATE_PARENT,
644 .ops = &clk_rcg2_ops,
645 },
646 };
647
648 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
649 .cmd_rcgr = 0x184d8,
650 .mnd_width = 16,
651 .hid_width = 5,
652 .parent_map = gcc_parent_map_0,
653 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
654 .clkr.hw.init = &(struct clk_init_data){
655 .name = "gcc_qupv3_wrap1_s3_clk_src",
656 .parent_data = gcc_parents_0,
657 .num_parents = 4,
658 .flags = CLK_SET_RATE_PARENT,
659 .ops = &clk_rcg2_ops,
660 },
661 };
662
663 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
664 .cmd_rcgr = 0x18608,
665 .mnd_width = 16,
666 .hid_width = 5,
667 .parent_map = gcc_parent_map_0,
668 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
669 .clkr.hw.init = &(struct clk_init_data){
670 .name = "gcc_qupv3_wrap1_s4_clk_src",
671 .parent_data = gcc_parents_0,
672 .num_parents = 4,
673 .flags = CLK_SET_RATE_PARENT,
674 .ops = &clk_rcg2_ops,
675 },
676 };
677
678 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
679 .cmd_rcgr = 0x18738,
680 .mnd_width = 16,
681 .hid_width = 5,
682 .parent_map = gcc_parent_map_0,
683 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
684 .clkr.hw.init = &(struct clk_init_data){
685 .name = "gcc_qupv3_wrap1_s5_clk_src",
686 .parent_data = gcc_parents_0,
687 .num_parents = 4,
688 .flags = CLK_SET_RATE_PARENT,
689 .ops = &clk_rcg2_ops,
690 },
691 };
692
693 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
694 .cmd_rcgr = 0x1e148,
695 .mnd_width = 16,
696 .hid_width = 5,
697 .parent_map = gcc_parent_map_0,
698 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
699 .clkr.hw.init = &(struct clk_init_data){
700 .name = "gcc_qupv3_wrap2_s0_clk_src",
701 .parent_data = gcc_parents_0,
702 .num_parents = 4,
703 .flags = CLK_SET_RATE_PARENT,
704 .ops = &clk_rcg2_ops,
705 },
706 };
707
708 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
709 .cmd_rcgr = 0x1e278,
710 .mnd_width = 16,
711 .hid_width = 5,
712 .parent_map = gcc_parent_map_0,
713 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
714 .clkr.hw.init = &(struct clk_init_data){
715 .name = "gcc_qupv3_wrap2_s1_clk_src",
716 .parent_data = gcc_parents_0,
717 .num_parents = 4,
718 .flags = CLK_SET_RATE_PARENT,
719 .ops = &clk_rcg2_ops,
720 },
721 };
722
723 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
724 .cmd_rcgr = 0x1e3a8,
725 .mnd_width = 16,
726 .hid_width = 5,
727 .parent_map = gcc_parent_map_0,
728 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "gcc_qupv3_wrap2_s2_clk_src",
731 .parent_data = gcc_parents_0,
732 .num_parents = 4,
733 .flags = CLK_SET_RATE_PARENT,
734 .ops = &clk_rcg2_ops,
735 },
736 };
737
738 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
739 .cmd_rcgr = 0x1e4d8,
740 .mnd_width = 16,
741 .hid_width = 5,
742 .parent_map = gcc_parent_map_0,
743 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
744 .clkr.hw.init = &(struct clk_init_data){
745 .name = "gcc_qupv3_wrap2_s3_clk_src",
746 .parent_data = gcc_parents_0,
747 .num_parents = 4,
748 .flags = CLK_SET_RATE_PARENT,
749 .ops = &clk_rcg2_ops,
750 },
751 };
752
753 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
754 .cmd_rcgr = 0x1e608,
755 .mnd_width = 16,
756 .hid_width = 5,
757 .parent_map = gcc_parent_map_0,
758 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
759 .clkr.hw.init = &(struct clk_init_data){
760 .name = "gcc_qupv3_wrap2_s4_clk_src",
761 .parent_data = gcc_parents_0,
762 .num_parents = 4,
763 .flags = CLK_SET_RATE_PARENT,
764 .ops = &clk_rcg2_ops,
765 },
766 };
767
768 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
769 .cmd_rcgr = 0x1e738,
770 .mnd_width = 16,
771 .hid_width = 5,
772 .parent_map = gcc_parent_map_0,
773 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "gcc_qupv3_wrap2_s5_clk_src",
776 .parent_data = gcc_parents_0,
777 .num_parents = 4,
778 .flags = CLK_SET_RATE_PARENT,
779 .ops = &clk_rcg2_ops,
780 },
781 };
782
783 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
784 F(400000, P_BI_TCXO, 12, 1, 4),
785 F(9600000, P_BI_TCXO, 2, 0, 0),
786 F(19200000, P_BI_TCXO, 1, 0, 0),
787 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
788 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
789 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
790 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
791 { }
792 };
793
794 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
795 .cmd_rcgr = 0x1400c,
796 .mnd_width = 8,
797 .hid_width = 5,
798 .parent_map = gcc_parent_map_6,
799 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "gcc_sdcc2_apps_clk_src",
802 .parent_data = gcc_parents_6,
803 .num_parents = 5,
804 .flags = CLK_SET_RATE_PARENT,
805 .ops = &clk_rcg2_floor_ops,
806 },
807 };
808
809 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
810 F(400000, P_BI_TCXO, 12, 1, 4),
811 F(9600000, P_BI_TCXO, 2, 0, 0),
812 F(19200000, P_BI_TCXO, 1, 0, 0),
813 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
814 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
815 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
816 { }
817 };
818
819 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
820 .cmd_rcgr = 0x1600c,
821 .mnd_width = 8,
822 .hid_width = 5,
823 .parent_map = gcc_parent_map_3,
824 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
825 .clkr.hw.init = &(struct clk_init_data){
826 .name = "gcc_sdcc4_apps_clk_src",
827 .parent_data = gcc_parents_3,
828 .num_parents = 3,
829 .flags = CLK_SET_RATE_PARENT,
830 .ops = &clk_rcg2_floor_ops,
831 },
832 };
833
834 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
835 F(105495, P_BI_TCXO, 2, 1, 91),
836 { }
837 };
838
839 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
840 .cmd_rcgr = 0x36010,
841 .mnd_width = 8,
842 .hid_width = 5,
843 .parent_map = gcc_parent_map_7,
844 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
845 .clkr.hw.init = &(struct clk_init_data){
846 .name = "gcc_tsif_ref_clk_src",
847 .parent_data = gcc_parents_7,
848 .num_parents = 5,
849 .flags = CLK_SET_RATE_PARENT,
850 .ops = &clk_rcg2_ops,
851 },
852 };
853
854 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
855 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
856 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
857 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
858 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
859 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
860 { }
861 };
862
863 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
864 .cmd_rcgr = 0x75020,
865 .mnd_width = 8,
866 .hid_width = 5,
867 .parent_map = gcc_parent_map_0,
868 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "gcc_ufs_card_axi_clk_src",
871 .parent_data = gcc_parents_0,
872 .num_parents = 4,
873 .flags = CLK_SET_RATE_PARENT,
874 .ops = &clk_rcg2_ops,
875 },
876 };
877
878 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
879 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
880 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
881 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
882 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
883 { }
884 };
885
886 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
887 .cmd_rcgr = 0x75060,
888 .mnd_width = 0,
889 .hid_width = 5,
890 .parent_map = gcc_parent_map_0,
891 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
892 .clkr.hw.init = &(struct clk_init_data){
893 .name = "gcc_ufs_card_ice_core_clk_src",
894 .parent_data = gcc_parents_0,
895 .num_parents = 4,
896 .flags = CLK_SET_RATE_PARENT,
897 .ops = &clk_rcg2_ops,
898 },
899 };
900
901 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
902 F(19200000, P_BI_TCXO, 1, 0, 0),
903 { }
904 };
905
906 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
907 .cmd_rcgr = 0x75094,
908 .mnd_width = 0,
909 .hid_width = 5,
910 .parent_map = gcc_parent_map_4,
911 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
912 .clkr.hw.init = &(struct clk_init_data){
913 .name = "gcc_ufs_card_phy_aux_clk_src",
914 .parent_data = gcc_parents_4,
915 .num_parents = 2,
916 .flags = CLK_SET_RATE_PARENT,
917 .ops = &clk_rcg2_ops,
918 },
919 };
920
921 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
922 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
923 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
924 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
925 { }
926 };
927
928 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
929 .cmd_rcgr = 0x75078,
930 .mnd_width = 0,
931 .hid_width = 5,
932 .parent_map = gcc_parent_map_0,
933 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "gcc_ufs_card_unipro_core_clk_src",
936 .parent_data = gcc_parents_0,
937 .num_parents = 4,
938 .flags = CLK_SET_RATE_PARENT,
939 .ops = &clk_rcg2_ops,
940 },
941 };
942
943 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
944 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
945 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
946 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
947 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
948 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
949 { }
950 };
951
952 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
953 .cmd_rcgr = 0x77020,
954 .mnd_width = 8,
955 .hid_width = 5,
956 .parent_map = gcc_parent_map_0,
957 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "gcc_ufs_phy_axi_clk_src",
960 .parent_data = gcc_parents_0,
961 .num_parents = 4,
962 .flags = CLK_SET_RATE_PARENT,
963 .ops = &clk_rcg2_ops,
964 },
965 };
966
967 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
968 .cmd_rcgr = 0x77060,
969 .mnd_width = 0,
970 .hid_width = 5,
971 .parent_map = gcc_parent_map_0,
972 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
973 .clkr.hw.init = &(struct clk_init_data){
974 .name = "gcc_ufs_phy_ice_core_clk_src",
975 .parent_data = gcc_parents_0,
976 .num_parents = 4,
977 .flags = CLK_SET_RATE_PARENT,
978 .ops = &clk_rcg2_ops,
979 },
980 };
981
982 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
983 .cmd_rcgr = 0x77094,
984 .mnd_width = 0,
985 .hid_width = 5,
986 .parent_map = gcc_parent_map_4,
987 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
988 .clkr.hw.init = &(struct clk_init_data){
989 .name = "gcc_ufs_phy_phy_aux_clk_src",
990 .parent_data = gcc_parents_4,
991 .num_parents = 2,
992 .flags = CLK_SET_RATE_PARENT,
993 .ops = &clk_rcg2_ops,
994 },
995 };
996
997 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
998 .cmd_rcgr = 0x77078,
999 .mnd_width = 0,
1000 .hid_width = 5,
1001 .parent_map = gcc_parent_map_0,
1002 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1003 .clkr.hw.init = &(struct clk_init_data){
1004 .name = "gcc_ufs_phy_unipro_core_clk_src",
1005 .parent_data = gcc_parents_0,
1006 .num_parents = 4,
1007 .flags = CLK_SET_RATE_PARENT,
1008 .ops = &clk_rcg2_ops,
1009 },
1010 };
1011
1012 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1013 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1014 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1015 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1016 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1017 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1018 { }
1019 };
1020
1021 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1022 .cmd_rcgr = 0xf01c,
1023 .mnd_width = 8,
1024 .hid_width = 5,
1025 .parent_map = gcc_parent_map_0,
1026 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1027 .clkr.hw.init = &(struct clk_init_data){
1028 .name = "gcc_usb30_prim_master_clk_src",
1029 .parent_data = gcc_parents_0,
1030 .num_parents = 4,
1031 .flags = CLK_SET_RATE_PARENT,
1032 .ops = &clk_rcg2_ops,
1033 },
1034 };
1035
1036 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1037 F(19200000, P_BI_TCXO, 1, 0, 0),
1038 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1039 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1040 { }
1041 };
1042
1043 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1044 .cmd_rcgr = 0xf034,
1045 .mnd_width = 0,
1046 .hid_width = 5,
1047 .parent_map = gcc_parent_map_0,
1048 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1049 .clkr.hw.init = &(struct clk_init_data){
1050 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1051 .parent_data = gcc_parents_0,
1052 .num_parents = 4,
1053 .flags = CLK_SET_RATE_PARENT,
1054 .ops = &clk_rcg2_ops,
1055 },
1056 };
1057
1058 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1059 .cmd_rcgr = 0x1001c,
1060 .mnd_width = 8,
1061 .hid_width = 5,
1062 .parent_map = gcc_parent_map_0,
1063 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1064 .clkr.hw.init = &(struct clk_init_data){
1065 .name = "gcc_usb30_sec_master_clk_src",
1066 .parent_data = gcc_parents_0,
1067 .num_parents = 4,
1068 .flags = CLK_SET_RATE_PARENT,
1069 .ops = &clk_rcg2_ops,
1070 },
1071 };
1072
1073 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1074 .cmd_rcgr = 0x10034,
1075 .mnd_width = 0,
1076 .hid_width = 5,
1077 .parent_map = gcc_parent_map_0,
1078 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1079 .clkr.hw.init = &(struct clk_init_data){
1080 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1081 .parent_data = gcc_parents_0,
1082 .num_parents = 4,
1083 .flags = CLK_SET_RATE_PARENT,
1084 .ops = &clk_rcg2_ops,
1085 },
1086 };
1087
1088 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1089 .cmd_rcgr = 0xf060,
1090 .mnd_width = 0,
1091 .hid_width = 5,
1092 .parent_map = gcc_parent_map_2,
1093 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1094 .clkr.hw.init = &(struct clk_init_data){
1095 .name = "gcc_usb3_prim_phy_aux_clk_src",
1096 .parent_data = gcc_parents_2,
1097 .num_parents = 3,
1098 .flags = CLK_SET_RATE_PARENT,
1099 .ops = &clk_rcg2_ops,
1100 },
1101 };
1102
1103 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1104 .cmd_rcgr = 0x10060,
1105 .mnd_width = 0,
1106 .hid_width = 5,
1107 .parent_map = gcc_parent_map_2,
1108 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1109 .clkr.hw.init = &(struct clk_init_data){
1110 .name = "gcc_usb3_sec_phy_aux_clk_src",
1111 .parent_data = gcc_parents_2,
1112 .num_parents = 3,
1113 .flags = CLK_SET_RATE_PARENT,
1114 .ops = &clk_rcg2_ops,
1115 },
1116 };
1117
1118 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1119 .halt_reg = 0x90018,
1120 .halt_check = BRANCH_HALT,
1121 .clkr = {
1122 .enable_reg = 0x90018,
1123 .enable_mask = BIT(0),
1124 .hw.init = &(struct clk_init_data){
1125 .name = "gcc_aggre_noc_pcie_tbu_clk",
1126 .ops = &clk_branch2_ops,
1127 },
1128 },
1129 };
1130
1131 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1132 .halt_reg = 0x750c0,
1133 .halt_check = BRANCH_HALT,
1134 .hwcg_reg = 0x750c0,
1135 .hwcg_bit = 1,
1136 .clkr = {
1137 .enable_reg = 0x750c0,
1138 .enable_mask = BIT(0),
1139 .hw.init = &(struct clk_init_data){
1140 .name = "gcc_aggre_ufs_card_axi_clk",
1141 .parent_hws = (const struct clk_hw *[]){
1142 &gcc_ufs_card_axi_clk_src.clkr.hw },
1143 .num_parents = 1,
1144 .flags = CLK_SET_RATE_PARENT,
1145 .ops = &clk_branch2_ops,
1146 },
1147 },
1148 };
1149
1150 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1151 .halt_reg = 0x750c0,
1152 .halt_check = BRANCH_HALT,
1153 .hwcg_reg = 0x750c0,
1154 .hwcg_bit = 1,
1155 .clkr = {
1156 .enable_reg = 0x750c0,
1157 .enable_mask = BIT(1),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1160 .parent_hws = (const struct clk_hw *[]){
1161 &gcc_aggre_ufs_card_axi_clk.clkr.hw },
1162 .num_parents = 1,
1163 .flags = CLK_SET_RATE_PARENT,
1164 .ops = &clk_branch_simple_ops,
1165 },
1166 },
1167 };
1168
1169 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1170 .halt_reg = 0x770c0,
1171 .halt_check = BRANCH_HALT,
1172 .hwcg_reg = 0x770c0,
1173 .hwcg_bit = 1,
1174 .clkr = {
1175 .enable_reg = 0x770c0,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gcc_aggre_ufs_phy_axi_clk",
1179 .parent_hws = (const struct clk_hw *[]){
1180 &gcc_ufs_phy_axi_clk_src.clkr.hw },
1181 .num_parents = 1,
1182 .flags = CLK_SET_RATE_PARENT,
1183 .ops = &clk_branch2_ops,
1184 },
1185 },
1186 };
1187
1188 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1189 .halt_reg = 0x770c0,
1190 .halt_check = BRANCH_HALT,
1191 .hwcg_reg = 0x770c0,
1192 .hwcg_bit = 1,
1193 .clkr = {
1194 .enable_reg = 0x770c0,
1195 .enable_mask = BIT(1),
1196 .hw.init = &(struct clk_init_data){
1197 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1198 .parent_hws = (const struct clk_hw *[]){
1199 &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
1200 .num_parents = 1,
1201 .flags = CLK_SET_RATE_PARENT,
1202 .ops = &clk_branch_simple_ops,
1203 },
1204 },
1205 };
1206
1207 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1208 .halt_reg = 0xf07c,
1209 .halt_check = BRANCH_HALT,
1210 .clkr = {
1211 .enable_reg = 0xf07c,
1212 .enable_mask = BIT(0),
1213 .hw.init = &(struct clk_init_data){
1214 .name = "gcc_aggre_usb3_prim_axi_clk",
1215 .parent_hws = (const struct clk_hw *[]){
1216 &gcc_usb30_prim_master_clk_src.clkr.hw },
1217 .num_parents = 1,
1218 .flags = CLK_SET_RATE_PARENT,
1219 .ops = &clk_branch2_ops,
1220 },
1221 },
1222 };
1223
1224 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1225 .halt_reg = 0x1007c,
1226 .halt_check = BRANCH_HALT,
1227 .clkr = {
1228 .enable_reg = 0x1007c,
1229 .enable_mask = BIT(0),
1230 .hw.init = &(struct clk_init_data){
1231 .name = "gcc_aggre_usb3_sec_axi_clk",
1232 .parent_hws = (const struct clk_hw *[]){
1233 &gcc_usb30_sec_master_clk_src.clkr.hw },
1234 .num_parents = 1,
1235 .flags = CLK_SET_RATE_PARENT,
1236 .ops = &clk_branch2_ops,
1237 },
1238 },
1239 };
1240
1241 static struct clk_branch gcc_boot_rom_ahb_clk = {
1242 .halt_reg = 0x38004,
1243 .halt_check = BRANCH_HALT_VOTED,
1244 .hwcg_reg = 0x38004,
1245 .hwcg_bit = 1,
1246 .clkr = {
1247 .enable_reg = 0x52004,
1248 .enable_mask = BIT(10),
1249 .hw.init = &(struct clk_init_data){
1250 .name = "gcc_boot_rom_ahb_clk",
1251 .ops = &clk_branch2_ops,
1252 },
1253 },
1254 };
1255
1256
1257
1258
1259
1260 static struct clk_branch gcc_camera_ahb_clk = {
1261 .halt_reg = 0xb008,
1262 .halt_check = BRANCH_HALT_DELAY,
1263 .hwcg_reg = 0xb008,
1264 .hwcg_bit = 1,
1265 .clkr = {
1266 .enable_reg = 0xb008,
1267 .enable_mask = BIT(0),
1268 .hw.init = &(struct clk_init_data){
1269 .name = "gcc_camera_ahb_clk",
1270 .flags = CLK_IS_CRITICAL,
1271 .ops = &clk_branch2_ops,
1272 },
1273 },
1274 };
1275
1276 static struct clk_branch gcc_camera_hf_axi_clk = {
1277 .halt_reg = 0xb030,
1278 .halt_check = BRANCH_HALT,
1279 .clkr = {
1280 .enable_reg = 0xb030,
1281 .enable_mask = BIT(0),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "gcc_camera_hf_axi_clk",
1284 .ops = &clk_branch2_ops,
1285 },
1286 },
1287 };
1288
1289 static struct clk_branch gcc_camera_sf_axi_clk = {
1290 .halt_reg = 0xb034,
1291 .halt_check = BRANCH_HALT,
1292 .clkr = {
1293 .enable_reg = 0xb034,
1294 .enable_mask = BIT(0),
1295 .hw.init = &(struct clk_init_data){
1296 .name = "gcc_camera_sf_axi_clk",
1297 .ops = &clk_branch2_ops,
1298 },
1299 },
1300 };
1301
1302
1303 static struct clk_branch gcc_camera_xo_clk = {
1304 .halt_reg = 0xb044,
1305 .halt_check = BRANCH_HALT_DELAY,
1306 .clkr = {
1307 .enable_reg = 0xb044,
1308 .enable_mask = BIT(0),
1309 .hw.init = &(struct clk_init_data){
1310 .name = "gcc_camera_xo_clk",
1311 .flags = CLK_IS_CRITICAL,
1312 .ops = &clk_branch2_ops,
1313 },
1314 },
1315 };
1316
1317 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1318 .halt_reg = 0xf078,
1319 .halt_check = BRANCH_HALT,
1320 .clkr = {
1321 .enable_reg = 0xf078,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1325 .parent_hws = (const struct clk_hw *[]){
1326 &gcc_usb30_prim_master_clk_src.clkr.hw },
1327 .num_parents = 1,
1328 .flags = CLK_SET_RATE_PARENT,
1329 .ops = &clk_branch2_ops,
1330 },
1331 },
1332 };
1333
1334 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1335 .halt_reg = 0x10078,
1336 .halt_check = BRANCH_HALT,
1337 .clkr = {
1338 .enable_reg = 0x10078,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data){
1341 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1342 .parent_hws = (const struct clk_hw *[]){
1343 &gcc_usb30_sec_master_clk_src.clkr.hw },
1344 .num_parents = 1,
1345 .flags = CLK_SET_RATE_PARENT,
1346 .ops = &clk_branch2_ops,
1347 },
1348 },
1349 };
1350
1351 static struct clk_branch gcc_cpuss_ahb_clk = {
1352 .halt_reg = 0x48000,
1353 .halt_check = BRANCH_HALT_VOTED,
1354 .clkr = {
1355 .enable_reg = 0x52004,
1356 .enable_mask = BIT(21),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "gcc_cpuss_ahb_clk",
1359 .parent_hws = (const struct clk_hw *[]){
1360 &gcc_cpuss_ahb_clk_src.clkr.hw },
1361 .num_parents = 1,
1362
1363 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1364 .ops = &clk_branch2_ops,
1365 },
1366 },
1367 };
1368
1369 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
1370 .halt_reg = 0x48190,
1371 .halt_check = BRANCH_HALT,
1372 .clkr = {
1373 .enable_reg = 0x48190,
1374 .enable_mask = BIT(0),
1375 .hw.init = &(struct clk_init_data){
1376 .name = "gcc_cpuss_dvm_bus_clk",
1377
1378 .flags = CLK_IS_CRITICAL,
1379 .ops = &clk_branch2_ops,
1380 },
1381 },
1382 };
1383
1384 static struct clk_branch gcc_cpuss_gnoc_clk = {
1385 .halt_reg = 0x48004,
1386 .halt_check = BRANCH_HALT_VOTED,
1387 .hwcg_reg = 0x48004,
1388 .hwcg_bit = 1,
1389 .clkr = {
1390 .enable_reg = 0x52004,
1391 .enable_mask = BIT(22),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "gcc_cpuss_gnoc_clk",
1394
1395 .flags = CLK_IS_CRITICAL,
1396 .ops = &clk_branch2_ops,
1397 },
1398 },
1399 };
1400
1401 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1402 .halt_reg = 0x48008,
1403 .halt_check = BRANCH_HALT,
1404 .clkr = {
1405 .enable_reg = 0x48008,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "gcc_cpuss_rbcpr_clk",
1409 .ops = &clk_branch2_ops,
1410 },
1411 },
1412 };
1413
1414 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1415 .halt_reg = 0x71154,
1416 .halt_check = BRANCH_VOTED,
1417 .clkr = {
1418 .enable_reg = 0x71154,
1419 .enable_mask = BIT(0),
1420 .hw.init = &(struct clk_init_data){
1421 .name = "gcc_ddrss_gpu_axi_clk",
1422 .ops = &clk_branch2_ops,
1423 },
1424 },
1425 };
1426
1427
1428
1429
1430
1431 static struct clk_branch gcc_disp_ahb_clk = {
1432 .halt_reg = 0xb00c,
1433 .halt_check = BRANCH_HALT_DELAY,
1434 .hwcg_reg = 0xb00c,
1435 .hwcg_bit = 1,
1436 .clkr = {
1437 .enable_reg = 0xb00c,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_disp_ahb_clk",
1441 .flags = CLK_IS_CRITICAL,
1442 .ops = &clk_branch2_ops,
1443 },
1444 },
1445 };
1446
1447 static struct clk_branch gcc_disp_hf_axi_clk = {
1448 .halt_reg = 0xb038,
1449 .halt_check = BRANCH_HALT,
1450 .clkr = {
1451 .enable_reg = 0xb038,
1452 .enable_mask = BIT(0),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "gcc_disp_hf_axi_clk",
1455 .ops = &clk_branch2_ops,
1456 },
1457 },
1458 };
1459
1460 static struct clk_branch gcc_disp_sf_axi_clk = {
1461 .halt_reg = 0xb03c,
1462 .halt_check = BRANCH_HALT,
1463 .clkr = {
1464 .enable_reg = 0xb03c,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "gcc_disp_sf_axi_clk",
1468 .ops = &clk_branch2_ops,
1469 },
1470 },
1471 };
1472
1473
1474 static struct clk_branch gcc_disp_xo_clk = {
1475 .halt_reg = 0xb048,
1476 .halt_check = BRANCH_HALT_DELAY,
1477 .clkr = {
1478 .enable_reg = 0xb048,
1479 .enable_mask = BIT(0),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "gcc_disp_xo_clk",
1482 .flags = CLK_IS_CRITICAL,
1483 .ops = &clk_branch2_ops,
1484 },
1485 },
1486 };
1487
1488 static struct clk_branch gcc_emac_axi_clk = {
1489 .halt_reg = 0x6010,
1490 .halt_check = BRANCH_HALT,
1491 .clkr = {
1492 .enable_reg = 0x6010,
1493 .enable_mask = BIT(0),
1494 .hw.init = &(struct clk_init_data){
1495 .name = "gcc_emac_axi_clk",
1496 .ops = &clk_branch2_ops,
1497 },
1498 },
1499 };
1500
1501 static struct clk_branch gcc_emac_ptp_clk = {
1502 .halt_reg = 0x6034,
1503 .halt_check = BRANCH_HALT,
1504 .clkr = {
1505 .enable_reg = 0x6034,
1506 .enable_mask = BIT(0),
1507 .hw.init = &(struct clk_init_data){
1508 .name = "gcc_emac_ptp_clk",
1509 .parent_hws = (const struct clk_hw *[]){
1510 &gcc_emac_ptp_clk_src.clkr.hw },
1511 .num_parents = 1,
1512 .flags = CLK_SET_RATE_PARENT,
1513 .ops = &clk_branch2_ops,
1514 },
1515 },
1516 };
1517
1518 static struct clk_branch gcc_emac_rgmii_clk = {
1519 .halt_reg = 0x6018,
1520 .halt_check = BRANCH_HALT,
1521 .clkr = {
1522 .enable_reg = 0x6018,
1523 .enable_mask = BIT(0),
1524 .hw.init = &(struct clk_init_data){
1525 .name = "gcc_emac_rgmii_clk",
1526 .parent_hws = (const struct clk_hw *[]){
1527 &gcc_emac_rgmii_clk_src.clkr.hw },
1528 .num_parents = 1,
1529 .flags = CLK_SET_RATE_PARENT,
1530 .ops = &clk_branch2_ops,
1531 },
1532 },
1533 };
1534
1535 static struct clk_branch gcc_emac_slv_ahb_clk = {
1536 .halt_reg = 0x6014,
1537 .halt_check = BRANCH_HALT,
1538 .hwcg_reg = 0x6014,
1539 .hwcg_bit = 1,
1540 .clkr = {
1541 .enable_reg = 0x6014,
1542 .enable_mask = BIT(0),
1543 .hw.init = &(struct clk_init_data){
1544 .name = "gcc_emac_slv_ahb_clk",
1545 .ops = &clk_branch2_ops,
1546 },
1547 },
1548 };
1549
1550 static struct clk_branch gcc_gp1_clk = {
1551 .halt_reg = 0x64000,
1552 .halt_check = BRANCH_HALT,
1553 .clkr = {
1554 .enable_reg = 0x64000,
1555 .enable_mask = BIT(0),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "gcc_gp1_clk",
1558 .parent_hws = (const struct clk_hw *[]){
1559 &gcc_gp1_clk_src.clkr.hw },
1560 .num_parents = 1,
1561 .flags = CLK_SET_RATE_PARENT,
1562 .ops = &clk_branch2_ops,
1563 },
1564 },
1565 };
1566
1567 static struct clk_branch gcc_gp2_clk = {
1568 .halt_reg = 0x65000,
1569 .halt_check = BRANCH_HALT,
1570 .clkr = {
1571 .enable_reg = 0x65000,
1572 .enable_mask = BIT(0),
1573 .hw.init = &(struct clk_init_data){
1574 .name = "gcc_gp2_clk",
1575 .parent_hws = (const struct clk_hw *[]){
1576 &gcc_gp2_clk_src.clkr.hw },
1577 .num_parents = 1,
1578 .flags = CLK_SET_RATE_PARENT,
1579 .ops = &clk_branch2_ops,
1580 },
1581 },
1582 };
1583
1584 static struct clk_branch gcc_gp3_clk = {
1585 .halt_reg = 0x66000,
1586 .halt_check = BRANCH_HALT,
1587 .clkr = {
1588 .enable_reg = 0x66000,
1589 .enable_mask = BIT(0),
1590 .hw.init = &(struct clk_init_data){
1591 .name = "gcc_gp3_clk",
1592 .parent_hws = (const struct clk_hw *[]){
1593 &gcc_gp3_clk_src.clkr.hw },
1594 .num_parents = 1,
1595 .flags = CLK_SET_RATE_PARENT,
1596 .ops = &clk_branch2_ops,
1597 },
1598 },
1599 };
1600
1601 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1602 .halt_reg = 0x71004,
1603 .halt_check = BRANCH_HALT,
1604 .hwcg_reg = 0x71004,
1605 .hwcg_bit = 1,
1606 .clkr = {
1607 .enable_reg = 0x71004,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "gcc_gpu_cfg_ahb_clk",
1611
1612 .flags = CLK_IS_CRITICAL,
1613 .ops = &clk_branch2_ops,
1614 },
1615 },
1616 };
1617
1618 static struct clk_branch gcc_gpu_iref_clk = {
1619 .halt_reg = 0x8c010,
1620 .halt_check = BRANCH_HALT,
1621 .clkr = {
1622 .enable_reg = 0x8c010,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data){
1625 .name = "gcc_gpu_iref_clk",
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629 };
1630
1631 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1632 .halt_reg = 0x7100c,
1633 .halt_check = BRANCH_VOTED,
1634 .clkr = {
1635 .enable_reg = 0x7100c,
1636 .enable_mask = BIT(0),
1637 .hw.init = &(struct clk_init_data){
1638 .name = "gcc_gpu_memnoc_gfx_clk",
1639 .ops = &clk_branch2_ops,
1640 },
1641 },
1642 };
1643
1644 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1645 .halt_reg = 0x71018,
1646 .halt_check = BRANCH_HALT,
1647 .clkr = {
1648 .enable_reg = 0x71018,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1652 .ops = &clk_branch2_ops,
1653 },
1654 },
1655 };
1656
1657 static struct clk_branch gcc_npu_at_clk = {
1658 .halt_reg = 0x4d010,
1659 .halt_check = BRANCH_VOTED,
1660 .clkr = {
1661 .enable_reg = 0x4d010,
1662 .enable_mask = BIT(0),
1663 .hw.init = &(struct clk_init_data){
1664 .name = "gcc_npu_at_clk",
1665 .ops = &clk_branch2_ops,
1666 },
1667 },
1668 };
1669
1670 static struct clk_branch gcc_npu_axi_clk = {
1671 .halt_reg = 0x4d008,
1672 .halt_check = BRANCH_VOTED,
1673 .clkr = {
1674 .enable_reg = 0x4d008,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "gcc_npu_axi_clk",
1678 .ops = &clk_branch2_ops,
1679 },
1680 },
1681 };
1682
1683 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1684 .halt_reg = 0x4d004,
1685 .halt_check = BRANCH_HALT,
1686 .hwcg_reg = 0x4d004,
1687 .hwcg_bit = 1,
1688 .clkr = {
1689 .enable_reg = 0x4d004,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(struct clk_init_data){
1692 .name = "gcc_npu_cfg_ahb_clk",
1693
1694 .flags = CLK_IS_CRITICAL,
1695 .ops = &clk_branch2_ops,
1696 },
1697 },
1698 };
1699
1700 static struct clk_branch gcc_npu_trig_clk = {
1701 .halt_reg = 0x4d00c,
1702 .halt_check = BRANCH_VOTED,
1703 .clkr = {
1704 .enable_reg = 0x4d00c,
1705 .enable_mask = BIT(0),
1706 .hw.init = &(struct clk_init_data){
1707 .name = "gcc_npu_trig_clk",
1708 .ops = &clk_branch2_ops,
1709 },
1710 },
1711 };
1712
1713 static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1714 .halt_reg = 0x6f02c,
1715 .halt_check = BRANCH_HALT,
1716 .clkr = {
1717 .enable_reg = 0x6f02c,
1718 .enable_mask = BIT(0),
1719 .hw.init = &(struct clk_init_data){
1720 .name = "gcc_pcie0_phy_refgen_clk",
1721 .parent_hws = (const struct clk_hw *[]){
1722 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1723 .num_parents = 1,
1724 .flags = CLK_SET_RATE_PARENT,
1725 .ops = &clk_branch2_ops,
1726 },
1727 },
1728 };
1729
1730 static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1731 .halt_reg = 0x6f030,
1732 .halt_check = BRANCH_HALT,
1733 .clkr = {
1734 .enable_reg = 0x6f030,
1735 .enable_mask = BIT(0),
1736 .hw.init = &(struct clk_init_data){
1737 .name = "gcc_pcie1_phy_refgen_clk",
1738 .parent_hws = (const struct clk_hw *[]){
1739 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1740 .num_parents = 1,
1741 .flags = CLK_SET_RATE_PARENT,
1742 .ops = &clk_branch2_ops,
1743 },
1744 },
1745 };
1746
1747 static struct clk_branch gcc_pcie_0_aux_clk = {
1748 .halt_reg = 0x6b020,
1749 .halt_check = BRANCH_HALT_VOTED,
1750 .clkr = {
1751 .enable_reg = 0x5200c,
1752 .enable_mask = BIT(3),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_pcie_0_aux_clk",
1755 .parent_hws = (const struct clk_hw *[]){
1756 &gcc_pcie_0_aux_clk_src.clkr.hw },
1757 .num_parents = 1,
1758 .flags = CLK_SET_RATE_PARENT,
1759 .ops = &clk_branch2_ops,
1760 },
1761 },
1762 };
1763
1764 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1765 .halt_reg = 0x6b01c,
1766 .halt_check = BRANCH_HALT_VOTED,
1767 .hwcg_reg = 0x6b01c,
1768 .hwcg_bit = 1,
1769 .clkr = {
1770 .enable_reg = 0x5200c,
1771 .enable_mask = BIT(2),
1772 .hw.init = &(struct clk_init_data){
1773 .name = "gcc_pcie_0_cfg_ahb_clk",
1774 .ops = &clk_branch2_ops,
1775 },
1776 },
1777 };
1778
1779 static struct clk_branch gcc_pcie_0_clkref_clk = {
1780 .halt_reg = 0x8c00c,
1781 .halt_check = BRANCH_HALT,
1782 .clkr = {
1783 .enable_reg = 0x8c00c,
1784 .enable_mask = BIT(0),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "gcc_pcie_0_clkref_clk",
1787 .ops = &clk_branch2_ops,
1788 },
1789 },
1790 };
1791
1792 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1793 .halt_reg = 0x6b018,
1794 .halt_check = BRANCH_HALT_VOTED,
1795 .clkr = {
1796 .enable_reg = 0x5200c,
1797 .enable_mask = BIT(1),
1798 .hw.init = &(struct clk_init_data){
1799 .name = "gcc_pcie_0_mstr_axi_clk",
1800 .ops = &clk_branch2_ops,
1801 },
1802 },
1803 };
1804
1805
1806 static struct clk_branch gcc_pcie_0_pipe_clk = {
1807 .halt_reg = 0x6b024,
1808 .halt_check = BRANCH_HALT_DELAY,
1809 .clkr = {
1810 .enable_reg = 0x5200c,
1811 .enable_mask = BIT(4),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "gcc_pcie_0_pipe_clk",
1814 .ops = &clk_branch2_ops,
1815 },
1816 },
1817 };
1818
1819 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1820 .halt_reg = 0x6b014,
1821 .halt_check = BRANCH_HALT_VOTED,
1822 .hwcg_reg = 0x6b014,
1823 .hwcg_bit = 1,
1824 .clkr = {
1825 .enable_reg = 0x5200c,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "gcc_pcie_0_slv_axi_clk",
1829 .ops = &clk_branch2_ops,
1830 },
1831 },
1832 };
1833
1834 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1835 .halt_reg = 0x6b010,
1836 .halt_check = BRANCH_HALT_VOTED,
1837 .clkr = {
1838 .enable_reg = 0x5200c,
1839 .enable_mask = BIT(5),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1842 .ops = &clk_branch2_ops,
1843 },
1844 },
1845 };
1846
1847 static struct clk_branch gcc_pcie_1_aux_clk = {
1848 .halt_reg = 0x8d020,
1849 .halt_check = BRANCH_HALT_VOTED,
1850 .clkr = {
1851 .enable_reg = 0x52004,
1852 .enable_mask = BIT(29),
1853 .hw.init = &(struct clk_init_data){
1854 .name = "gcc_pcie_1_aux_clk",
1855 .parent_hws = (const struct clk_hw *[]){
1856 &gcc_pcie_1_aux_clk_src.clkr.hw },
1857 .num_parents = 1,
1858 .flags = CLK_SET_RATE_PARENT,
1859 .ops = &clk_branch2_ops,
1860 },
1861 },
1862 };
1863
1864 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1865 .halt_reg = 0x8d01c,
1866 .halt_check = BRANCH_HALT_VOTED,
1867 .hwcg_reg = 0x8d01c,
1868 .hwcg_bit = 1,
1869 .clkr = {
1870 .enable_reg = 0x52004,
1871 .enable_mask = BIT(28),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_pcie_1_cfg_ahb_clk",
1874 .ops = &clk_branch2_ops,
1875 },
1876 },
1877 };
1878
1879 static struct clk_branch gcc_pcie_1_clkref_clk = {
1880 .halt_reg = 0x8c02c,
1881 .halt_check = BRANCH_HALT,
1882 .clkr = {
1883 .enable_reg = 0x8c02c,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "gcc_pcie_1_clkref_clk",
1887 .ops = &clk_branch2_ops,
1888 },
1889 },
1890 };
1891
1892 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1893 .halt_reg = 0x8d018,
1894 .halt_check = BRANCH_HALT_VOTED,
1895 .clkr = {
1896 .enable_reg = 0x52004,
1897 .enable_mask = BIT(27),
1898 .hw.init = &(struct clk_init_data){
1899 .name = "gcc_pcie_1_mstr_axi_clk",
1900 .ops = &clk_branch2_ops,
1901 },
1902 },
1903 };
1904
1905
1906 static struct clk_branch gcc_pcie_1_pipe_clk = {
1907 .halt_reg = 0x8d024,
1908 .halt_check = BRANCH_HALT_DELAY,
1909 .clkr = {
1910 .enable_reg = 0x52004,
1911 .enable_mask = BIT(30),
1912 .hw.init = &(struct clk_init_data){
1913 .name = "gcc_pcie_1_pipe_clk",
1914 .ops = &clk_branch2_ops,
1915 },
1916 },
1917 };
1918
1919 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1920 .halt_reg = 0x8d014,
1921 .halt_check = BRANCH_HALT_VOTED,
1922 .hwcg_reg = 0x8d014,
1923 .hwcg_bit = 1,
1924 .clkr = {
1925 .enable_reg = 0x52004,
1926 .enable_mask = BIT(26),
1927 .hw.init = &(struct clk_init_data){
1928 .name = "gcc_pcie_1_slv_axi_clk",
1929 .ops = &clk_branch2_ops,
1930 },
1931 },
1932 };
1933
1934 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1935 .halt_reg = 0x8d010,
1936 .halt_check = BRANCH_HALT_VOTED,
1937 .clkr = {
1938 .enable_reg = 0x52004,
1939 .enable_mask = BIT(25),
1940 .hw.init = &(struct clk_init_data){
1941 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1942 .ops = &clk_branch2_ops,
1943 },
1944 },
1945 };
1946
1947 static struct clk_branch gcc_pcie_phy_aux_clk = {
1948 .halt_reg = 0x6f004,
1949 .halt_check = BRANCH_HALT,
1950 .clkr = {
1951 .enable_reg = 0x6f004,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_pcie_phy_aux_clk",
1955 .parent_hws = (const struct clk_hw *[]){
1956 &gcc_pcie_0_aux_clk_src.clkr.hw },
1957 .num_parents = 1,
1958 .flags = CLK_SET_RATE_PARENT,
1959 .ops = &clk_branch2_ops,
1960 },
1961 },
1962 };
1963
1964 static struct clk_branch gcc_pdm2_clk = {
1965 .halt_reg = 0x3300c,
1966 .halt_check = BRANCH_HALT,
1967 .clkr = {
1968 .enable_reg = 0x3300c,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "gcc_pdm2_clk",
1972 .parent_hws = (const struct clk_hw *[]){
1973 &gcc_pdm2_clk_src.clkr.hw },
1974 .num_parents = 1,
1975 .flags = CLK_SET_RATE_PARENT,
1976 .ops = &clk_branch2_ops,
1977 },
1978 },
1979 };
1980
1981 static struct clk_branch gcc_pdm_ahb_clk = {
1982 .halt_reg = 0x33004,
1983 .halt_check = BRANCH_HALT,
1984 .hwcg_reg = 0x33004,
1985 .hwcg_bit = 1,
1986 .clkr = {
1987 .enable_reg = 0x33004,
1988 .enable_mask = BIT(0),
1989 .hw.init = &(struct clk_init_data){
1990 .name = "gcc_pdm_ahb_clk",
1991 .ops = &clk_branch2_ops,
1992 },
1993 },
1994 };
1995
1996 static struct clk_branch gcc_pdm_xo4_clk = {
1997 .halt_reg = 0x33008,
1998 .halt_check = BRANCH_HALT,
1999 .clkr = {
2000 .enable_reg = 0x33008,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "gcc_pdm_xo4_clk",
2004 .ops = &clk_branch2_ops,
2005 },
2006 },
2007 };
2008
2009 static struct clk_branch gcc_prng_ahb_clk = {
2010 .halt_reg = 0x34004,
2011 .halt_check = BRANCH_HALT_VOTED,
2012 .clkr = {
2013 .enable_reg = 0x52004,
2014 .enable_mask = BIT(13),
2015 .hw.init = &(struct clk_init_data){
2016 .name = "gcc_prng_ahb_clk",
2017 .ops = &clk_branch2_ops,
2018 },
2019 },
2020 };
2021
2022 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2023 .halt_reg = 0xb018,
2024 .halt_check = BRANCH_HALT,
2025 .hwcg_reg = 0xb018,
2026 .hwcg_bit = 1,
2027 .clkr = {
2028 .enable_reg = 0xb018,
2029 .enable_mask = BIT(0),
2030 .hw.init = &(struct clk_init_data){
2031 .name = "gcc_qmip_camera_nrt_ahb_clk",
2032 .ops = &clk_branch2_ops,
2033 },
2034 },
2035 };
2036
2037 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2038 .halt_reg = 0xb01c,
2039 .halt_check = BRANCH_HALT,
2040 .hwcg_reg = 0xb01c,
2041 .hwcg_bit = 1,
2042 .clkr = {
2043 .enable_reg = 0xb01c,
2044 .enable_mask = BIT(0),
2045 .hw.init = &(struct clk_init_data){
2046 .name = "gcc_qmip_camera_rt_ahb_clk",
2047 .ops = &clk_branch2_ops,
2048 },
2049 },
2050 };
2051
2052 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2053 .halt_reg = 0xb020,
2054 .halt_check = BRANCH_HALT,
2055 .hwcg_reg = 0xb020,
2056 .hwcg_bit = 1,
2057 .clkr = {
2058 .enable_reg = 0xb020,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "gcc_qmip_disp_ahb_clk",
2062 .ops = &clk_branch2_ops,
2063 },
2064 },
2065 };
2066
2067 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2068 .halt_reg = 0xb010,
2069 .halt_check = BRANCH_HALT,
2070 .hwcg_reg = 0xb010,
2071 .hwcg_bit = 1,
2072 .clkr = {
2073 .enable_reg = 0xb010,
2074 .enable_mask = BIT(0),
2075 .hw.init = &(struct clk_init_data){
2076 .name = "gcc_qmip_video_cvp_ahb_clk",
2077 .ops = &clk_branch2_ops,
2078 },
2079 },
2080 };
2081
2082 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2083 .halt_reg = 0xb014,
2084 .halt_check = BRANCH_HALT,
2085 .hwcg_reg = 0xb014,
2086 .hwcg_bit = 1,
2087 .clkr = {
2088 .enable_reg = 0xb014,
2089 .enable_mask = BIT(0),
2090 .hw.init = &(struct clk_init_data){
2091 .name = "gcc_qmip_video_vcodec_ahb_clk",
2092 .ops = &clk_branch2_ops,
2093 },
2094 },
2095 };
2096
2097 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2098 .halt_reg = 0x4b000,
2099 .halt_check = BRANCH_HALT,
2100 .clkr = {
2101 .enable_reg = 0x4b000,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "gcc_qspi_cnoc_periph_ahb_clk",
2105 .ops = &clk_branch2_ops,
2106 },
2107 },
2108 };
2109
2110 static struct clk_branch gcc_qspi_core_clk = {
2111 .halt_reg = 0x4b004,
2112 .halt_check = BRANCH_HALT,
2113 .clkr = {
2114 .enable_reg = 0x4b004,
2115 .enable_mask = BIT(0),
2116 .hw.init = &(struct clk_init_data){
2117 .name = "gcc_qspi_core_clk",
2118 .parent_hws = (const struct clk_hw *[]){
2119 &gcc_qspi_core_clk_src.clkr.hw },
2120 .num_parents = 1,
2121 .flags = CLK_SET_RATE_PARENT,
2122 .ops = &clk_branch2_ops,
2123 },
2124 },
2125 };
2126
2127 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2128 .halt_reg = 0x17144,
2129 .halt_check = BRANCH_HALT_VOTED,
2130 .clkr = {
2131 .enable_reg = 0x5200c,
2132 .enable_mask = BIT(10),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "gcc_qupv3_wrap0_s0_clk",
2135 .parent_hws = (const struct clk_hw *[]){
2136 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2137 .num_parents = 1,
2138 .flags = CLK_SET_RATE_PARENT,
2139 .ops = &clk_branch2_ops,
2140 },
2141 },
2142 };
2143
2144 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2145 .halt_reg = 0x17274,
2146 .halt_check = BRANCH_HALT_VOTED,
2147 .clkr = {
2148 .enable_reg = 0x5200c,
2149 .enable_mask = BIT(11),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "gcc_qupv3_wrap0_s1_clk",
2152 .parent_hws = (const struct clk_hw *[]){
2153 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2154 .num_parents = 1,
2155 .flags = CLK_SET_RATE_PARENT,
2156 .ops = &clk_branch2_ops,
2157 },
2158 },
2159 };
2160
2161 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2162 .halt_reg = 0x173a4,
2163 .halt_check = BRANCH_HALT_VOTED,
2164 .clkr = {
2165 .enable_reg = 0x5200c,
2166 .enable_mask = BIT(12),
2167 .hw.init = &(struct clk_init_data){
2168 .name = "gcc_qupv3_wrap0_s2_clk",
2169 .parent_hws = (const struct clk_hw *[]){
2170 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2171 .num_parents = 1,
2172 .flags = CLK_SET_RATE_PARENT,
2173 .ops = &clk_branch2_ops,
2174 },
2175 },
2176 };
2177
2178 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2179 .halt_reg = 0x174d4,
2180 .halt_check = BRANCH_HALT_VOTED,
2181 .clkr = {
2182 .enable_reg = 0x5200c,
2183 .enable_mask = BIT(13),
2184 .hw.init = &(struct clk_init_data){
2185 .name = "gcc_qupv3_wrap0_s3_clk",
2186 .parent_hws = (const struct clk_hw *[]){
2187 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2188 .num_parents = 1,
2189 .flags = CLK_SET_RATE_PARENT,
2190 .ops = &clk_branch2_ops,
2191 },
2192 },
2193 };
2194
2195 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2196 .halt_reg = 0x17604,
2197 .halt_check = BRANCH_HALT_VOTED,
2198 .clkr = {
2199 .enable_reg = 0x5200c,
2200 .enable_mask = BIT(14),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "gcc_qupv3_wrap0_s4_clk",
2203 .parent_hws = (const struct clk_hw *[]){
2204 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2205 .num_parents = 1,
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2208 },
2209 },
2210 };
2211
2212 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2213 .halt_reg = 0x17734,
2214 .halt_check = BRANCH_HALT_VOTED,
2215 .clkr = {
2216 .enable_reg = 0x5200c,
2217 .enable_mask = BIT(15),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "gcc_qupv3_wrap0_s5_clk",
2220 .parent_hws = (const struct clk_hw *[]){
2221 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2222 .num_parents = 1,
2223 .flags = CLK_SET_RATE_PARENT,
2224 .ops = &clk_branch2_ops,
2225 },
2226 },
2227 };
2228
2229 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2230 .halt_reg = 0x17864,
2231 .halt_check = BRANCH_HALT_VOTED,
2232 .clkr = {
2233 .enable_reg = 0x5200c,
2234 .enable_mask = BIT(16),
2235 .hw.init = &(struct clk_init_data){
2236 .name = "gcc_qupv3_wrap0_s6_clk",
2237 .parent_hws = (const struct clk_hw *[]){
2238 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
2239 .num_parents = 1,
2240 .flags = CLK_SET_RATE_PARENT,
2241 .ops = &clk_branch2_ops,
2242 },
2243 },
2244 };
2245
2246 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2247 .halt_reg = 0x17994,
2248 .halt_check = BRANCH_HALT_VOTED,
2249 .clkr = {
2250 .enable_reg = 0x5200c,
2251 .enable_mask = BIT(17),
2252 .hw.init = &(struct clk_init_data){
2253 .name = "gcc_qupv3_wrap0_s7_clk",
2254 .parent_hws = (const struct clk_hw *[]){
2255 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
2256 .num_parents = 1,
2257 .flags = CLK_SET_RATE_PARENT,
2258 .ops = &clk_branch2_ops,
2259 },
2260 },
2261 };
2262
2263 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2264 .halt_reg = 0x18144,
2265 .halt_check = BRANCH_HALT_VOTED,
2266 .clkr = {
2267 .enable_reg = 0x5200c,
2268 .enable_mask = BIT(22),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "gcc_qupv3_wrap1_s0_clk",
2271 .parent_hws = (const struct clk_hw *[]){
2272 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
2273 .num_parents = 1,
2274 .flags = CLK_SET_RATE_PARENT,
2275 .ops = &clk_branch2_ops,
2276 },
2277 },
2278 };
2279
2280 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2281 .halt_reg = 0x18274,
2282 .halt_check = BRANCH_HALT_VOTED,
2283 .clkr = {
2284 .enable_reg = 0x5200c,
2285 .enable_mask = BIT(23),
2286 .hw.init = &(struct clk_init_data){
2287 .name = "gcc_qupv3_wrap1_s1_clk",
2288 .parent_hws = (const struct clk_hw *[]){
2289 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
2290 .num_parents = 1,
2291 .flags = CLK_SET_RATE_PARENT,
2292 .ops = &clk_branch2_ops,
2293 },
2294 },
2295 };
2296
2297 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2298 .halt_reg = 0x183a4,
2299 .halt_check = BRANCH_HALT_VOTED,
2300 .clkr = {
2301 .enable_reg = 0x5200c,
2302 .enable_mask = BIT(24),
2303 .hw.init = &(struct clk_init_data){
2304 .name = "gcc_qupv3_wrap1_s2_clk",
2305 .parent_hws = (const struct clk_hw *[]){
2306 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
2307 .num_parents = 1,
2308 .flags = CLK_SET_RATE_PARENT,
2309 .ops = &clk_branch2_ops,
2310 },
2311 },
2312 };
2313
2314 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2315 .halt_reg = 0x184d4,
2316 .halt_check = BRANCH_HALT_VOTED,
2317 .clkr = {
2318 .enable_reg = 0x5200c,
2319 .enable_mask = BIT(25),
2320 .hw.init = &(struct clk_init_data){
2321 .name = "gcc_qupv3_wrap1_s3_clk",
2322 .parent_hws = (const struct clk_hw *[]){
2323 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
2324 .num_parents = 1,
2325 .flags = CLK_SET_RATE_PARENT,
2326 .ops = &clk_branch2_ops,
2327 },
2328 },
2329 };
2330
2331 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2332 .halt_reg = 0x18604,
2333 .halt_check = BRANCH_HALT_VOTED,
2334 .clkr = {
2335 .enable_reg = 0x5200c,
2336 .enable_mask = BIT(26),
2337 .hw.init = &(struct clk_init_data){
2338 .name = "gcc_qupv3_wrap1_s4_clk",
2339 .parent_hws = (const struct clk_hw *[]){
2340 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
2341 .num_parents = 1,
2342 .flags = CLK_SET_RATE_PARENT,
2343 .ops = &clk_branch2_ops,
2344 },
2345 },
2346 };
2347
2348 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2349 .halt_reg = 0x18734,
2350 .halt_check = BRANCH_HALT_VOTED,
2351 .clkr = {
2352 .enable_reg = 0x5200c,
2353 .enable_mask = BIT(27),
2354 .hw.init = &(struct clk_init_data){
2355 .name = "gcc_qupv3_wrap1_s5_clk",
2356 .parent_hws = (const struct clk_hw *[]){
2357 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
2358 .num_parents = 1,
2359 .flags = CLK_SET_RATE_PARENT,
2360 .ops = &clk_branch2_ops,
2361 },
2362 },
2363 };
2364
2365 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2366 .halt_reg = 0x1e144,
2367 .halt_check = BRANCH_HALT_VOTED,
2368 .clkr = {
2369 .enable_reg = 0x52014,
2370 .enable_mask = BIT(4),
2371 .hw.init = &(struct clk_init_data){
2372 .name = "gcc_qupv3_wrap2_s0_clk",
2373 .parent_hws = (const struct clk_hw *[]){
2374 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
2375 .num_parents = 1,
2376 .flags = CLK_SET_RATE_PARENT,
2377 .ops = &clk_branch2_ops,
2378 },
2379 },
2380 };
2381
2382 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2383 .halt_reg = 0x1e274,
2384 .halt_check = BRANCH_HALT_VOTED,
2385 .clkr = {
2386 .enable_reg = 0x52014,
2387 .enable_mask = BIT(5),
2388 .hw.init = &(struct clk_init_data){
2389 .name = "gcc_qupv3_wrap2_s1_clk",
2390 .parent_hws = (const struct clk_hw *[]){
2391 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
2392 .num_parents = 1,
2393 .flags = CLK_SET_RATE_PARENT,
2394 .ops = &clk_branch2_ops,
2395 },
2396 },
2397 };
2398
2399 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2400 .halt_reg = 0x1e3a4,
2401 .halt_check = BRANCH_HALT_VOTED,
2402 .clkr = {
2403 .enable_reg = 0x52014,
2404 .enable_mask = BIT(6),
2405 .hw.init = &(struct clk_init_data){
2406 .name = "gcc_qupv3_wrap2_s2_clk",
2407 .parent_hws = (const struct clk_hw *[]){
2408 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
2409 .num_parents = 1,
2410 .flags = CLK_SET_RATE_PARENT,
2411 .ops = &clk_branch2_ops,
2412 },
2413 },
2414 };
2415
2416 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2417 .halt_reg = 0x1e4d4,
2418 .halt_check = BRANCH_HALT_VOTED,
2419 .clkr = {
2420 .enable_reg = 0x52014,
2421 .enable_mask = BIT(7),
2422 .hw.init = &(struct clk_init_data){
2423 .name = "gcc_qupv3_wrap2_s3_clk",
2424 .parent_hws = (const struct clk_hw *[]){
2425 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
2426 .num_parents = 1,
2427 .flags = CLK_SET_RATE_PARENT,
2428 .ops = &clk_branch2_ops,
2429 },
2430 },
2431 };
2432
2433 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2434 .halt_reg = 0x1e604,
2435 .halt_check = BRANCH_HALT_VOTED,
2436 .clkr = {
2437 .enable_reg = 0x52014,
2438 .enable_mask = BIT(8),
2439 .hw.init = &(struct clk_init_data){
2440 .name = "gcc_qupv3_wrap2_s4_clk",
2441 .parent_hws = (const struct clk_hw *[]){
2442 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
2443 .num_parents = 1,
2444 .flags = CLK_SET_RATE_PARENT,
2445 .ops = &clk_branch2_ops,
2446 },
2447 },
2448 };
2449
2450 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2451 .halt_reg = 0x1e734,
2452 .halt_check = BRANCH_HALT_VOTED,
2453 .clkr = {
2454 .enable_reg = 0x52014,
2455 .enable_mask = BIT(9),
2456 .hw.init = &(struct clk_init_data){
2457 .name = "gcc_qupv3_wrap2_s5_clk",
2458 .parent_hws = (const struct clk_hw *[]){
2459 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
2460 .num_parents = 1,
2461 .flags = CLK_SET_RATE_PARENT,
2462 .ops = &clk_branch2_ops,
2463 },
2464 },
2465 };
2466
2467 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2468 .halt_reg = 0x17004,
2469 .halt_check = BRANCH_HALT_VOTED,
2470 .clkr = {
2471 .enable_reg = 0x5200c,
2472 .enable_mask = BIT(6),
2473 .hw.init = &(struct clk_init_data){
2474 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2475 .ops = &clk_branch2_ops,
2476 },
2477 },
2478 };
2479
2480 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2481 .halt_reg = 0x17008,
2482 .halt_check = BRANCH_HALT_VOTED,
2483 .hwcg_reg = 0x17008,
2484 .hwcg_bit = 1,
2485 .clkr = {
2486 .enable_reg = 0x5200c,
2487 .enable_mask = BIT(7),
2488 .hw.init = &(struct clk_init_data){
2489 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2490 .ops = &clk_branch2_ops,
2491 },
2492 },
2493 };
2494
2495 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2496 .halt_reg = 0x18004,
2497 .halt_check = BRANCH_HALT_VOTED,
2498 .clkr = {
2499 .enable_reg = 0x5200c,
2500 .enable_mask = BIT(20),
2501 .hw.init = &(struct clk_init_data){
2502 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2503 .ops = &clk_branch2_ops,
2504 },
2505 },
2506 };
2507
2508 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2509 .halt_reg = 0x18008,
2510 .halt_check = BRANCH_HALT_VOTED,
2511 .hwcg_reg = 0x18008,
2512 .hwcg_bit = 1,
2513 .clkr = {
2514 .enable_reg = 0x5200c,
2515 .enable_mask = BIT(21),
2516 .hw.init = &(struct clk_init_data){
2517 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2518 .ops = &clk_branch2_ops,
2519 },
2520 },
2521 };
2522
2523 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2524 .halt_reg = 0x1e004,
2525 .halt_check = BRANCH_HALT_VOTED,
2526 .clkr = {
2527 .enable_reg = 0x52014,
2528 .enable_mask = BIT(2),
2529 .hw.init = &(struct clk_init_data){
2530 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2531 .ops = &clk_branch2_ops,
2532 },
2533 },
2534 };
2535
2536 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2537 .halt_reg = 0x1e008,
2538 .halt_check = BRANCH_HALT_VOTED,
2539 .hwcg_reg = 0x1e008,
2540 .hwcg_bit = 1,
2541 .clkr = {
2542 .enable_reg = 0x52014,
2543 .enable_mask = BIT(1),
2544 .hw.init = &(struct clk_init_data){
2545 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2546 .ops = &clk_branch2_ops,
2547 },
2548 },
2549 };
2550
2551 static struct clk_branch gcc_sdcc2_ahb_clk = {
2552 .halt_reg = 0x14008,
2553 .halt_check = BRANCH_HALT,
2554 .clkr = {
2555 .enable_reg = 0x14008,
2556 .enable_mask = BIT(0),
2557 .hw.init = &(struct clk_init_data){
2558 .name = "gcc_sdcc2_ahb_clk",
2559 .ops = &clk_branch2_ops,
2560 },
2561 },
2562 };
2563
2564 static struct clk_branch gcc_sdcc2_apps_clk = {
2565 .halt_reg = 0x14004,
2566 .halt_check = BRANCH_HALT,
2567 .clkr = {
2568 .enable_reg = 0x14004,
2569 .enable_mask = BIT(0),
2570 .hw.init = &(struct clk_init_data){
2571 .name = "gcc_sdcc2_apps_clk",
2572 .parent_hws = (const struct clk_hw *[]){
2573 &gcc_sdcc2_apps_clk_src.clkr.hw },
2574 .num_parents = 1,
2575 .flags = CLK_SET_RATE_PARENT,
2576 .ops = &clk_branch2_ops,
2577 },
2578 },
2579 };
2580
2581 static struct clk_branch gcc_sdcc4_ahb_clk = {
2582 .halt_reg = 0x16008,
2583 .halt_check = BRANCH_HALT,
2584 .clkr = {
2585 .enable_reg = 0x16008,
2586 .enable_mask = BIT(0),
2587 .hw.init = &(struct clk_init_data){
2588 .name = "gcc_sdcc4_ahb_clk",
2589 .ops = &clk_branch2_ops,
2590 },
2591 },
2592 };
2593
2594 static struct clk_branch gcc_sdcc4_apps_clk = {
2595 .halt_reg = 0x16004,
2596 .halt_check = BRANCH_HALT,
2597 .clkr = {
2598 .enable_reg = 0x16004,
2599 .enable_mask = BIT(0),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gcc_sdcc4_apps_clk",
2602 .parent_hws = (const struct clk_hw *[]){
2603 &gcc_sdcc4_apps_clk_src.clkr.hw },
2604 .num_parents = 1,
2605 .flags = CLK_SET_RATE_PARENT,
2606 .ops = &clk_branch2_ops,
2607 },
2608 },
2609 };
2610
2611 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2612 .halt_reg = 0x4819c,
2613 .halt_check = BRANCH_HALT_VOTED,
2614 .clkr = {
2615 .enable_reg = 0x52004,
2616 .enable_mask = BIT(0),
2617 .hw.init = &(struct clk_init_data){
2618 .name = "gcc_sys_noc_cpuss_ahb_clk",
2619 .parent_hws = (const struct clk_hw *[]){
2620 &gcc_cpuss_ahb_clk_src.clkr.hw },
2621 .num_parents = 1,
2622
2623 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2624 .ops = &clk_branch2_ops,
2625 },
2626 },
2627 };
2628
2629 static struct clk_branch gcc_tsif_ahb_clk = {
2630 .halt_reg = 0x36004,
2631 .halt_check = BRANCH_HALT,
2632 .clkr = {
2633 .enable_reg = 0x36004,
2634 .enable_mask = BIT(0),
2635 .hw.init = &(struct clk_init_data){
2636 .name = "gcc_tsif_ahb_clk",
2637 .ops = &clk_branch2_ops,
2638 },
2639 },
2640 };
2641
2642 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2643 .halt_reg = 0x3600c,
2644 .halt_check = BRANCH_HALT,
2645 .clkr = {
2646 .enable_reg = 0x3600c,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "gcc_tsif_inactivity_timers_clk",
2650 .ops = &clk_branch2_ops,
2651 },
2652 },
2653 };
2654
2655 static struct clk_branch gcc_tsif_ref_clk = {
2656 .halt_reg = 0x36008,
2657 .halt_check = BRANCH_HALT,
2658 .clkr = {
2659 .enable_reg = 0x36008,
2660 .enable_mask = BIT(0),
2661 .hw.init = &(struct clk_init_data){
2662 .name = "gcc_tsif_ref_clk",
2663 .parent_hws = (const struct clk_hw *[]){
2664 &gcc_tsif_ref_clk_src.clkr.hw },
2665 .num_parents = 1,
2666 .flags = CLK_SET_RATE_PARENT,
2667 .ops = &clk_branch2_ops,
2668 },
2669 },
2670 };
2671
2672 static struct clk_branch gcc_ufs_card_ahb_clk = {
2673 .halt_reg = 0x75014,
2674 .halt_check = BRANCH_HALT,
2675 .hwcg_reg = 0x75014,
2676 .hwcg_bit = 1,
2677 .clkr = {
2678 .enable_reg = 0x75014,
2679 .enable_mask = BIT(0),
2680 .hw.init = &(struct clk_init_data){
2681 .name = "gcc_ufs_card_ahb_clk",
2682 .ops = &clk_branch2_ops,
2683 },
2684 },
2685 };
2686
2687 static struct clk_branch gcc_ufs_card_axi_clk = {
2688 .halt_reg = 0x75010,
2689 .halt_check = BRANCH_HALT,
2690 .hwcg_reg = 0x75010,
2691 .hwcg_bit = 1,
2692 .clkr = {
2693 .enable_reg = 0x75010,
2694 .enable_mask = BIT(0),
2695 .hw.init = &(struct clk_init_data){
2696 .name = "gcc_ufs_card_axi_clk",
2697 .parent_hws = (const struct clk_hw *[]){
2698 &gcc_ufs_card_axi_clk_src.clkr.hw },
2699 .num_parents = 1,
2700 .flags = CLK_SET_RATE_PARENT,
2701 .ops = &clk_branch2_ops,
2702 },
2703 },
2704 };
2705
2706 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2707 .halt_reg = 0x75010,
2708 .halt_check = BRANCH_HALT,
2709 .hwcg_reg = 0x75010,
2710 .hwcg_bit = 1,
2711 .clkr = {
2712 .enable_reg = 0x75010,
2713 .enable_mask = BIT(1),
2714 .hw.init = &(struct clk_init_data){
2715 .name = "gcc_ufs_card_axi_hw_ctl_clk",
2716 .parent_hws = (const struct clk_hw *[]){
2717 &gcc_ufs_card_axi_clk.clkr.hw },
2718 .num_parents = 1,
2719 .flags = CLK_SET_RATE_PARENT,
2720 .ops = &clk_branch_simple_ops,
2721 },
2722 },
2723 };
2724
2725 static struct clk_branch gcc_ufs_card_clkref_clk = {
2726 .halt_reg = 0x8c004,
2727 .halt_check = BRANCH_HALT,
2728 .clkr = {
2729 .enable_reg = 0x8c004,
2730 .enable_mask = BIT(0),
2731 .hw.init = &(struct clk_init_data){
2732 .name = "gcc_ufs_card_clkref_clk",
2733 .ops = &clk_branch2_ops,
2734 },
2735 },
2736 };
2737
2738 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2739 .halt_reg = 0x7505c,
2740 .halt_check = BRANCH_HALT,
2741 .hwcg_reg = 0x7505c,
2742 .hwcg_bit = 1,
2743 .clkr = {
2744 .enable_reg = 0x7505c,
2745 .enable_mask = BIT(0),
2746 .hw.init = &(struct clk_init_data){
2747 .name = "gcc_ufs_card_ice_core_clk",
2748 .parent_hws = (const struct clk_hw *[]){
2749 &gcc_ufs_card_ice_core_clk_src.clkr.hw },
2750 .num_parents = 1,
2751 .flags = CLK_SET_RATE_PARENT,
2752 .ops = &clk_branch2_ops,
2753 },
2754 },
2755 };
2756
2757 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2758 .halt_reg = 0x7505c,
2759 .halt_check = BRANCH_HALT,
2760 .hwcg_reg = 0x7505c,
2761 .hwcg_bit = 1,
2762 .clkr = {
2763 .enable_reg = 0x7505c,
2764 .enable_mask = BIT(1),
2765 .hw.init = &(struct clk_init_data){
2766 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2767 .parent_hws = (const struct clk_hw *[]){
2768 &gcc_ufs_card_ice_core_clk.clkr.hw },
2769 .num_parents = 1,
2770 .flags = CLK_SET_RATE_PARENT,
2771 .ops = &clk_branch_simple_ops,
2772 },
2773 },
2774 };
2775
2776 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2777 .halt_reg = 0x75090,
2778 .halt_check = BRANCH_HALT,
2779 .hwcg_reg = 0x75090,
2780 .hwcg_bit = 1,
2781 .clkr = {
2782 .enable_reg = 0x75090,
2783 .enable_mask = BIT(0),
2784 .hw.init = &(struct clk_init_data){
2785 .name = "gcc_ufs_card_phy_aux_clk",
2786 .parent_hws = (const struct clk_hw *[]){
2787 &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
2788 .num_parents = 1,
2789 .flags = CLK_SET_RATE_PARENT,
2790 .ops = &clk_branch2_ops,
2791 },
2792 },
2793 };
2794
2795 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2796 .halt_reg = 0x75090,
2797 .halt_check = BRANCH_HALT,
2798 .hwcg_reg = 0x75090,
2799 .hwcg_bit = 1,
2800 .clkr = {
2801 .enable_reg = 0x75090,
2802 .enable_mask = BIT(1),
2803 .hw.init = &(struct clk_init_data){
2804 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2805 .parent_hws = (const struct clk_hw *[]){
2806 &gcc_ufs_card_phy_aux_clk.clkr.hw },
2807 .num_parents = 1,
2808 .flags = CLK_SET_RATE_PARENT,
2809 .ops = &clk_branch_simple_ops,
2810 },
2811 },
2812 };
2813
2814 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2815 .halt_reg = 0x75058,
2816 .halt_check = BRANCH_HALT,
2817 .hwcg_reg = 0x75058,
2818 .hwcg_bit = 1,
2819 .clkr = {
2820 .enable_reg = 0x75058,
2821 .enable_mask = BIT(0),
2822 .hw.init = &(struct clk_init_data){
2823 .name = "gcc_ufs_card_unipro_core_clk",
2824 .parent_hws = (const struct clk_hw *[]){
2825 &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
2826 .num_parents = 1,
2827 .flags = CLK_SET_RATE_PARENT,
2828 .ops = &clk_branch2_ops,
2829 },
2830 },
2831 };
2832
2833 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2834 .halt_reg = 0x75058,
2835 .halt_check = BRANCH_HALT,
2836 .hwcg_reg = 0x75058,
2837 .hwcg_bit = 1,
2838 .clkr = {
2839 .enable_reg = 0x75058,
2840 .enable_mask = BIT(1),
2841 .hw.init = &(struct clk_init_data){
2842 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2843 .parent_hws = (const struct clk_hw *[]){
2844 &gcc_ufs_card_unipro_core_clk.clkr.hw },
2845 .num_parents = 1,
2846 .flags = CLK_SET_RATE_PARENT,
2847 .ops = &clk_branch_simple_ops,
2848 },
2849 },
2850 };
2851
2852 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2853 .halt_reg = 0x8c000,
2854 .halt_check = BRANCH_HALT,
2855 .clkr = {
2856 .enable_reg = 0x8c000,
2857 .enable_mask = BIT(0),
2858 .hw.init = &(struct clk_init_data){
2859 .name = "gcc_ufs_mem_clkref_clk",
2860 .ops = &clk_branch2_ops,
2861 },
2862 },
2863 };
2864
2865 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2866 .halt_reg = 0x77014,
2867 .halt_check = BRANCH_HALT,
2868 .hwcg_reg = 0x77014,
2869 .hwcg_bit = 1,
2870 .clkr = {
2871 .enable_reg = 0x77014,
2872 .enable_mask = BIT(0),
2873 .hw.init = &(struct clk_init_data){
2874 .name = "gcc_ufs_phy_ahb_clk",
2875 .ops = &clk_branch2_ops,
2876 },
2877 },
2878 };
2879
2880 static struct clk_branch gcc_ufs_phy_axi_clk = {
2881 .halt_reg = 0x77010,
2882 .halt_check = BRANCH_HALT,
2883 .hwcg_reg = 0x77010,
2884 .hwcg_bit = 1,
2885 .clkr = {
2886 .enable_reg = 0x77010,
2887 .enable_mask = BIT(0),
2888 .hw.init = &(struct clk_init_data){
2889 .name = "gcc_ufs_phy_axi_clk",
2890 .parent_hws = (const struct clk_hw *[]){
2891 &gcc_ufs_phy_axi_clk_src.clkr.hw },
2892 .num_parents = 1,
2893 .flags = CLK_SET_RATE_PARENT,
2894 .ops = &clk_branch2_ops,
2895 },
2896 },
2897 };
2898
2899 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2900 .halt_reg = 0x77010,
2901 .halt_check = BRANCH_HALT,
2902 .hwcg_reg = 0x77010,
2903 .hwcg_bit = 1,
2904 .clkr = {
2905 .enable_reg = 0x77010,
2906 .enable_mask = BIT(1),
2907 .hw.init = &(struct clk_init_data){
2908 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2909 .parent_hws = (const struct clk_hw *[]){
2910 &gcc_ufs_phy_axi_clk.clkr.hw },
2911 .num_parents = 1,
2912 .flags = CLK_SET_RATE_PARENT,
2913 .ops = &clk_branch_simple_ops,
2914 },
2915 },
2916 };
2917
2918 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2919 .halt_reg = 0x7705c,
2920 .halt_check = BRANCH_HALT,
2921 .hwcg_reg = 0x7705c,
2922 .hwcg_bit = 1,
2923 .clkr = {
2924 .enable_reg = 0x7705c,
2925 .enable_mask = BIT(0),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "gcc_ufs_phy_ice_core_clk",
2928 .parent_hws = (const struct clk_hw *[]){
2929 &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
2930 .num_parents = 1,
2931 .flags = CLK_SET_RATE_PARENT,
2932 .ops = &clk_branch2_ops,
2933 },
2934 },
2935 };
2936
2937 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2938 .halt_reg = 0x7705c,
2939 .halt_check = BRANCH_HALT,
2940 .hwcg_reg = 0x7705c,
2941 .hwcg_bit = 1,
2942 .clkr = {
2943 .enable_reg = 0x7705c,
2944 .enable_mask = BIT(1),
2945 .hw.init = &(struct clk_init_data){
2946 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2947 .parent_hws = (const struct clk_hw *[]){
2948 &gcc_ufs_phy_ice_core_clk.clkr.hw },
2949 .num_parents = 1,
2950 .flags = CLK_SET_RATE_PARENT,
2951 .ops = &clk_branch_simple_ops,
2952 },
2953 },
2954 };
2955
2956 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2957 .halt_reg = 0x77090,
2958 .halt_check = BRANCH_HALT,
2959 .hwcg_reg = 0x77090,
2960 .hwcg_bit = 1,
2961 .clkr = {
2962 .enable_reg = 0x77090,
2963 .enable_mask = BIT(0),
2964 .hw.init = &(struct clk_init_data){
2965 .name = "gcc_ufs_phy_phy_aux_clk",
2966 .parent_hws = (const struct clk_hw *[]){
2967 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
2968 .num_parents = 1,
2969 .flags = CLK_SET_RATE_PARENT,
2970 .ops = &clk_branch2_ops,
2971 },
2972 },
2973 };
2974
2975 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2976 .halt_reg = 0x77090,
2977 .halt_check = BRANCH_HALT,
2978 .hwcg_reg = 0x77090,
2979 .hwcg_bit = 1,
2980 .clkr = {
2981 .enable_reg = 0x77090,
2982 .enable_mask = BIT(1),
2983 .hw.init = &(struct clk_init_data){
2984 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2985 .parent_hws = (const struct clk_hw *[]){
2986 &gcc_ufs_phy_phy_aux_clk.clkr.hw },
2987 .num_parents = 1,
2988 .flags = CLK_SET_RATE_PARENT,
2989 .ops = &clk_branch_simple_ops,
2990 },
2991 },
2992 };
2993
2994 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2995 .halt_reg = 0x77058,
2996 .halt_check = BRANCH_HALT,
2997 .hwcg_reg = 0x77058,
2998 .hwcg_bit = 1,
2999 .clkr = {
3000 .enable_reg = 0x77058,
3001 .enable_mask = BIT(0),
3002 .hw.init = &(struct clk_init_data){
3003 .name = "gcc_ufs_phy_unipro_core_clk",
3004 .parent_hws = (const struct clk_hw *[]){
3005 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
3006 .num_parents = 1,
3007 .flags = CLK_SET_RATE_PARENT,
3008 .ops = &clk_branch2_ops,
3009 },
3010 },
3011 };
3012
3013 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3014 .halt_reg = 0x77058,
3015 .halt_check = BRANCH_HALT,
3016 .hwcg_reg = 0x77058,
3017 .hwcg_bit = 1,
3018 .clkr = {
3019 .enable_reg = 0x77058,
3020 .enable_mask = BIT(1),
3021 .hw.init = &(struct clk_init_data){
3022 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3023 .parent_hws = (const struct clk_hw *[]){
3024 &gcc_ufs_phy_unipro_core_clk.clkr.hw },
3025 .num_parents = 1,
3026 .flags = CLK_SET_RATE_PARENT,
3027 .ops = &clk_branch_simple_ops,
3028 },
3029 },
3030 };
3031
3032 static struct clk_branch gcc_usb30_prim_master_clk = {
3033 .halt_reg = 0xf010,
3034 .halt_check = BRANCH_HALT,
3035 .clkr = {
3036 .enable_reg = 0xf010,
3037 .enable_mask = BIT(0),
3038 .hw.init = &(struct clk_init_data){
3039 .name = "gcc_usb30_prim_master_clk",
3040 .parent_hws = (const struct clk_hw *[]){
3041 &gcc_usb30_prim_master_clk_src.clkr.hw },
3042 .num_parents = 1,
3043 .flags = CLK_SET_RATE_PARENT,
3044 .ops = &clk_branch2_ops,
3045 },
3046 },
3047 };
3048
3049 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3050 .halt_reg = 0xf018,
3051 .halt_check = BRANCH_HALT,
3052 .clkr = {
3053 .enable_reg = 0xf018,
3054 .enable_mask = BIT(0),
3055 .hw.init = &(struct clk_init_data){
3056 .name = "gcc_usb30_prim_mock_utmi_clk",
3057 .parent_hws = (const struct clk_hw *[]){
3058 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
3059 .num_parents = 1,
3060 .flags = CLK_SET_RATE_PARENT,
3061 .ops = &clk_branch2_ops,
3062 },
3063 },
3064 };
3065
3066 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3067 .halt_reg = 0xf014,
3068 .halt_check = BRANCH_HALT,
3069 .clkr = {
3070 .enable_reg = 0xf014,
3071 .enable_mask = BIT(0),
3072 .hw.init = &(struct clk_init_data){
3073 .name = "gcc_usb30_prim_sleep_clk",
3074 .ops = &clk_branch2_ops,
3075 },
3076 },
3077 };
3078
3079 static struct clk_branch gcc_usb30_sec_master_clk = {
3080 .halt_reg = 0x10010,
3081 .halt_check = BRANCH_HALT,
3082 .clkr = {
3083 .enable_reg = 0x10010,
3084 .enable_mask = BIT(0),
3085 .hw.init = &(struct clk_init_data){
3086 .name = "gcc_usb30_sec_master_clk",
3087 .parent_hws = (const struct clk_hw *[]){
3088 &gcc_usb30_sec_master_clk_src.clkr.hw },
3089 .num_parents = 1,
3090 .flags = CLK_SET_RATE_PARENT,
3091 .ops = &clk_branch2_ops,
3092 },
3093 },
3094 };
3095
3096 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3097 .halt_reg = 0x10018,
3098 .halt_check = BRANCH_HALT,
3099 .clkr = {
3100 .enable_reg = 0x10018,
3101 .enable_mask = BIT(0),
3102 .hw.init = &(struct clk_init_data){
3103 .name = "gcc_usb30_sec_mock_utmi_clk",
3104 .parent_hws = (const struct clk_hw *[]){
3105 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
3106 .num_parents = 1,
3107 .flags = CLK_SET_RATE_PARENT,
3108 .ops = &clk_branch2_ops,
3109 },
3110 },
3111 };
3112
3113 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3114 .halt_reg = 0x10014,
3115 .halt_check = BRANCH_HALT,
3116 .clkr = {
3117 .enable_reg = 0x10014,
3118 .enable_mask = BIT(0),
3119 .hw.init = &(struct clk_init_data){
3120 .name = "gcc_usb30_sec_sleep_clk",
3121 .ops = &clk_branch2_ops,
3122 },
3123 },
3124 };
3125
3126 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3127 .halt_reg = 0x8c008,
3128 .halt_check = BRANCH_HALT,
3129 .clkr = {
3130 .enable_reg = 0x8c008,
3131 .enable_mask = BIT(0),
3132 .hw.init = &(struct clk_init_data){
3133 .name = "gcc_usb3_prim_clkref_clk",
3134 .ops = &clk_branch2_ops,
3135 },
3136 },
3137 };
3138
3139 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3140 .halt_reg = 0xf050,
3141 .halt_check = BRANCH_HALT,
3142 .clkr = {
3143 .enable_reg = 0xf050,
3144 .enable_mask = BIT(0),
3145 .hw.init = &(struct clk_init_data){
3146 .name = "gcc_usb3_prim_phy_aux_clk",
3147 .parent_hws = (const struct clk_hw *[]){
3148 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3149 .num_parents = 1,
3150 .flags = CLK_SET_RATE_PARENT,
3151 .ops = &clk_branch2_ops,
3152 },
3153 },
3154 };
3155
3156 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3157 .halt_reg = 0xf054,
3158 .halt_check = BRANCH_HALT,
3159 .clkr = {
3160 .enable_reg = 0xf054,
3161 .enable_mask = BIT(0),
3162 .hw.init = &(struct clk_init_data){
3163 .name = "gcc_usb3_prim_phy_com_aux_clk",
3164 .parent_hws = (const struct clk_hw *[]){
3165 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3166 .num_parents = 1,
3167 .flags = CLK_SET_RATE_PARENT,
3168 .ops = &clk_branch2_ops,
3169 },
3170 },
3171 };
3172
3173 static struct clk_branch gcc_usb3_sec_clkref_clk = {
3174 .halt_reg = 0x8c028,
3175 .halt_check = BRANCH_HALT,
3176 .clkr = {
3177 .enable_reg = 0x8c028,
3178 .enable_mask = BIT(0),
3179 .hw.init = &(struct clk_init_data){
3180 .name = "gcc_usb3_sec_clkref_clk",
3181 .ops = &clk_branch2_ops,
3182 },
3183 },
3184 };
3185
3186 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3187 .halt_reg = 0x10050,
3188 .halt_check = BRANCH_HALT,
3189 .clkr = {
3190 .enable_reg = 0x10050,
3191 .enable_mask = BIT(0),
3192 .hw.init = &(struct clk_init_data){
3193 .name = "gcc_usb3_sec_phy_aux_clk",
3194 .parent_hws = (const struct clk_hw *[]){
3195 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3196 .num_parents = 1,
3197 .flags = CLK_SET_RATE_PARENT,
3198 .ops = &clk_branch2_ops,
3199 },
3200 },
3201 };
3202
3203 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3204 .halt_reg = 0x10054,
3205 .halt_check = BRANCH_HALT,
3206 .clkr = {
3207 .enable_reg = 0x10054,
3208 .enable_mask = BIT(0),
3209 .hw.init = &(struct clk_init_data){
3210 .name = "gcc_usb3_sec_phy_com_aux_clk",
3211 .parent_hws = (const struct clk_hw *[]){
3212 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3213 .num_parents = 1,
3214 .flags = CLK_SET_RATE_PARENT,
3215 .ops = &clk_branch2_ops,
3216 },
3217 },
3218 };
3219
3220
3221
3222
3223
3224 static struct clk_branch gcc_video_ahb_clk = {
3225 .halt_reg = 0xb004,
3226 .halt_check = BRANCH_HALT_DELAY,
3227 .hwcg_reg = 0xb004,
3228 .hwcg_bit = 1,
3229 .clkr = {
3230 .enable_reg = 0xb004,
3231 .enable_mask = BIT(0),
3232 .hw.init = &(struct clk_init_data){
3233 .name = "gcc_video_ahb_clk",
3234 .flags = CLK_IS_CRITICAL,
3235 .ops = &clk_branch2_ops,
3236 },
3237 },
3238 };
3239
3240 static struct clk_branch gcc_video_axi0_clk = {
3241 .halt_reg = 0xb024,
3242 .halt_check = BRANCH_HALT,
3243 .clkr = {
3244 .enable_reg = 0xb024,
3245 .enable_mask = BIT(0),
3246 .hw.init = &(struct clk_init_data){
3247 .name = "gcc_video_axi0_clk",
3248 .ops = &clk_branch2_ops,
3249 },
3250 },
3251 };
3252
3253 static struct clk_branch gcc_video_axi1_clk = {
3254 .halt_reg = 0xb028,
3255 .halt_check = BRANCH_HALT,
3256 .clkr = {
3257 .enable_reg = 0xb028,
3258 .enable_mask = BIT(0),
3259 .hw.init = &(struct clk_init_data){
3260 .name = "gcc_video_axi1_clk",
3261 .ops = &clk_branch2_ops,
3262 },
3263 },
3264 };
3265
3266 static struct clk_branch gcc_video_axic_clk = {
3267 .halt_reg = 0xb02c,
3268 .halt_check = BRANCH_HALT,
3269 .clkr = {
3270 .enable_reg = 0xb02c,
3271 .enable_mask = BIT(0),
3272 .hw.init = &(struct clk_init_data){
3273 .name = "gcc_video_axic_clk",
3274 .ops = &clk_branch2_ops,
3275 },
3276 },
3277 };
3278
3279
3280 static struct clk_branch gcc_video_xo_clk = {
3281 .halt_reg = 0xb040,
3282 .halt_check = BRANCH_HALT_DELAY,
3283 .clkr = {
3284 .enable_reg = 0xb040,
3285 .enable_mask = BIT(0),
3286 .hw.init = &(struct clk_init_data){
3287 .name = "gcc_video_xo_clk",
3288 .flags = CLK_IS_CRITICAL,
3289 .ops = &clk_branch2_ops,
3290 },
3291 },
3292 };
3293
3294 static struct clk_regmap *gcc_sm8150_clocks[] = {
3295 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3296 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3297 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
3298 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3299 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3300 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
3301 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3302 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3303 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3304 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3305 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3306 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3307 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3308 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3309 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3310 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3311 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3312 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3313 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3314 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3315 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3316 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3317 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3318 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3319 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3320 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3321 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
3322 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
3323 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
3324 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
3325 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
3326 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
3327 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3328 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3329 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3330 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3331 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3332 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3333 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3334 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3335 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3336 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3337 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
3338 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3339 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3340 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
3341 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3342 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3343 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3344 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3345 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3346 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3347 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3348 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3349 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3350 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3351 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3352 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3353 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3354 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3355 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3356 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3357 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3358 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3359 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3360 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3361 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3362 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3363 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3364 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3365 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3366 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3367 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3368 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3369 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3370 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3371 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3372 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3373 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3374 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3375 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3376 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3377 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3378 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3379 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3380 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3381 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3382 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3383 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3384 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3385 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3386 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3387 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3388 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3389 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3390 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3391 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3392 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3393 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3394 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3395 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3396 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3397 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3398 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3399 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3400 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3401 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3402 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3403 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3404 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3405 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3406 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3407 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3408 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3409 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3410 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3411 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3412 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3413 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3414 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3415 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3416 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3417 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3418 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3419 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3420 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3421 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3422 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3423 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3424 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3425 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3426 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3427 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3428 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3429 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3430 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3431 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3432 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3433 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3434 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3435 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3436 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3437 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3438 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
3439 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3440 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3441 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3442 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
3443 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3444 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3445 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3446 &gcc_ufs_card_unipro_core_clk_src.clkr,
3447 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
3448 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3449 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3450 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3451 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3452 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3453 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3454 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3455 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3456 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
3457 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3458 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3459 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3460 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3461 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3462 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3463 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3464 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
3465 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3466 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3467 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3468 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3469 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3470 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3471 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3472 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3473 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3474 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3475 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3476 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3477 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3478 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3479 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3480 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3481 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3482 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3483 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3484 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3485 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3486 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3487 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3488 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3489 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
3490 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3491 [GPLL0] = &gpll0.clkr,
3492 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3493 [GPLL7] = &gpll7.clkr,
3494 [GPLL9] = &gpll9.clkr,
3495 };
3496
3497 static const struct qcom_reset_map gcc_sm8150_resets[] = {
3498 [GCC_EMAC_BCR] = { 0x6000 },
3499 [GCC_GPU_BCR] = { 0x71000 },
3500 [GCC_MMSS_BCR] = { 0xb000 },
3501 [GCC_NPU_BCR] = { 0x4d000 },
3502 [GCC_PCIE_0_BCR] = { 0x6b000 },
3503 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3504 [GCC_PCIE_1_BCR] = { 0x8d000 },
3505 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3506 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3507 [GCC_PDM_BCR] = { 0x33000 },
3508 [GCC_PRNG_BCR] = { 0x34000 },
3509 [GCC_QSPI_BCR] = { 0x24008 },
3510 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3511 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3512 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3513 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3514 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3515 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3516 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3517 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3518 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3519 [GCC_SDCC2_BCR] = { 0x14000 },
3520 [GCC_SDCC4_BCR] = { 0x16000 },
3521 [GCC_TSIF_BCR] = { 0x36000 },
3522 [GCC_UFS_CARD_BCR] = { 0x75000 },
3523 [GCC_UFS_PHY_BCR] = { 0x77000 },
3524 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3525 [GCC_USB30_SEC_BCR] = { 0x10000 },
3526 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3527 };
3528
3529 static const struct regmap_config gcc_sm8150_regmap_config = {
3530 .reg_bits = 32,
3531 .reg_stride = 4,
3532 .val_bits = 32,
3533 .max_register = 0x9c040,
3534 .fast_io = true,
3535 };
3536
3537 static const struct qcom_cc_desc gcc_sm8150_desc = {
3538 .config = &gcc_sm8150_regmap_config,
3539 .clks = gcc_sm8150_clocks,
3540 .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
3541 .resets = gcc_sm8150_resets,
3542 .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
3543 };
3544
3545 static const struct of_device_id gcc_sm8150_match_table[] = {
3546 { .compatible = "qcom,gcc-sm8150" },
3547 { }
3548 };
3549 MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
3550
3551 static int gcc_sm8150_probe(struct platform_device *pdev)
3552 {
3553 struct regmap *regmap;
3554
3555 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
3556 if (IS_ERR(regmap))
3557 return PTR_ERR(regmap);
3558
3559
3560 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
3561 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3562
3563 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
3564 }
3565
3566 static struct platform_driver gcc_sm8150_driver = {
3567 .probe = gcc_sm8150_probe,
3568 .driver = {
3569 .name = "gcc-sm8150",
3570 .of_match_table = gcc_sm8150_match_table,
3571 },
3572 };
3573
3574 static int __init gcc_sm8150_init(void)
3575 {
3576 return platform_driver_register(&gcc_sm8150_driver);
3577 }
3578 subsys_initcall(gcc_sm8150_init);
3579
3580 static void __exit gcc_sm8150_exit(void)
3581 {
3582 platform_driver_unregister(&gcc_sm8150_driver);
3583 }
3584 module_exit(gcc_sm8150_exit);
3585
3586 MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
3587 MODULE_LICENSE("GPL v2");