This source file includes following definitions.
- mmcc_msm8974_probe
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6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
18 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
19
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 enum {
29 P_XO,
30 P_MMPLL0,
31 P_EDPLINK,
32 P_MMPLL1,
33 P_HDMIPLL,
34 P_GPLL0,
35 P_EDPVCO,
36 P_GPLL1,
37 P_DSI0PLL,
38 P_DSI0PLL_BYTE,
39 P_MMPLL2,
40 P_MMPLL3,
41 P_DSI1PLL,
42 P_DSI1PLL_BYTE,
43 };
44
45 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
46 { P_XO, 0 },
47 { P_MMPLL0, 1 },
48 { P_MMPLL1, 2 },
49 { P_GPLL0, 5 }
50 };
51
52 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
53 "xo",
54 "mmpll0_vote",
55 "mmpll1_vote",
56 "mmss_gpll0_vote",
57 };
58
59 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
60 { P_XO, 0 },
61 { P_MMPLL0, 1 },
62 { P_HDMIPLL, 4 },
63 { P_GPLL0, 5 },
64 { P_DSI0PLL, 2 },
65 { P_DSI1PLL, 3 }
66 };
67
68 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
69 "xo",
70 "mmpll0_vote",
71 "hdmipll",
72 "mmss_gpll0_vote",
73 "dsi0pll",
74 "dsi1pll",
75 };
76
77 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
78 { P_XO, 0 },
79 { P_MMPLL0, 1 },
80 { P_MMPLL1, 2 },
81 { P_GPLL0, 5 },
82 { P_MMPLL2, 3 }
83 };
84
85 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
86 "xo",
87 "mmpll0_vote",
88 "mmpll1_vote",
89 "mmss_gpll0_vote",
90 "mmpll2",
91 };
92
93 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
94 { P_XO, 0 },
95 { P_MMPLL0, 1 },
96 { P_MMPLL1, 2 },
97 { P_GPLL0, 5 },
98 { P_MMPLL3, 3 }
99 };
100
101 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
102 "xo",
103 "mmpll0_vote",
104 "mmpll1_vote",
105 "mmss_gpll0_vote",
106 "mmpll3",
107 };
108
109 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
110 { P_XO, 0 },
111 { P_MMPLL0, 1 },
112 { P_MMPLL1, 2 },
113 { P_GPLL0, 5 },
114 { P_GPLL1, 4 }
115 };
116
117 static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
118 "xo",
119 "mmpll0_vote",
120 "mmpll1_vote",
121 "mmss_gpll0_vote",
122 "gpll1_vote",
123 };
124
125 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
126 { P_XO, 0 },
127 { P_EDPLINK, 4 },
128 { P_HDMIPLL, 3 },
129 { P_EDPVCO, 5 },
130 { P_DSI0PLL, 1 },
131 { P_DSI1PLL, 2 }
132 };
133
134 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
135 "xo",
136 "edp_link_clk",
137 "hdmipll",
138 "edp_vco_div",
139 "dsi0pll",
140 "dsi1pll",
141 };
142
143 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
144 { P_XO, 0 },
145 { P_EDPLINK, 4 },
146 { P_HDMIPLL, 3 },
147 { P_GPLL0, 5 },
148 { P_DSI0PLL, 1 },
149 { P_DSI1PLL, 2 }
150 };
151
152 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
153 "xo",
154 "edp_link_clk",
155 "hdmipll",
156 "gpll0_vote",
157 "dsi0pll",
158 "dsi1pll",
159 };
160
161 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
162 { P_XO, 0 },
163 { P_EDPLINK, 4 },
164 { P_HDMIPLL, 3 },
165 { P_GPLL0, 5 },
166 { P_DSI0PLL_BYTE, 1 },
167 { P_DSI1PLL_BYTE, 2 }
168 };
169
170 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
171 "xo",
172 "edp_link_clk",
173 "hdmipll",
174 "gpll0_vote",
175 "dsi0pllbyte",
176 "dsi1pllbyte",
177 };
178
179 static struct clk_pll mmpll0 = {
180 .l_reg = 0x0004,
181 .m_reg = 0x0008,
182 .n_reg = 0x000c,
183 .config_reg = 0x0014,
184 .mode_reg = 0x0000,
185 .status_reg = 0x001c,
186 .status_bit = 17,
187 .clkr.hw.init = &(struct clk_init_data){
188 .name = "mmpll0",
189 .parent_names = (const char *[]){ "xo" },
190 .num_parents = 1,
191 .ops = &clk_pll_ops,
192 },
193 };
194
195 static struct clk_regmap mmpll0_vote = {
196 .enable_reg = 0x0100,
197 .enable_mask = BIT(0),
198 .hw.init = &(struct clk_init_data){
199 .name = "mmpll0_vote",
200 .parent_names = (const char *[]){ "mmpll0" },
201 .num_parents = 1,
202 .ops = &clk_pll_vote_ops,
203 },
204 };
205
206 static struct clk_pll mmpll1 = {
207 .l_reg = 0x0044,
208 .m_reg = 0x0048,
209 .n_reg = 0x004c,
210 .config_reg = 0x0050,
211 .mode_reg = 0x0040,
212 .status_reg = 0x005c,
213 .status_bit = 17,
214 .clkr.hw.init = &(struct clk_init_data){
215 .name = "mmpll1",
216 .parent_names = (const char *[]){ "xo" },
217 .num_parents = 1,
218 .ops = &clk_pll_ops,
219 },
220 };
221
222 static struct clk_regmap mmpll1_vote = {
223 .enable_reg = 0x0100,
224 .enable_mask = BIT(1),
225 .hw.init = &(struct clk_init_data){
226 .name = "mmpll1_vote",
227 .parent_names = (const char *[]){ "mmpll1" },
228 .num_parents = 1,
229 .ops = &clk_pll_vote_ops,
230 },
231 };
232
233 static struct clk_pll mmpll2 = {
234 .l_reg = 0x4104,
235 .m_reg = 0x4108,
236 .n_reg = 0x410c,
237 .config_reg = 0x4110,
238 .mode_reg = 0x4100,
239 .status_reg = 0x411c,
240 .clkr.hw.init = &(struct clk_init_data){
241 .name = "mmpll2",
242 .parent_names = (const char *[]){ "xo" },
243 .num_parents = 1,
244 .ops = &clk_pll_ops,
245 },
246 };
247
248 static struct clk_pll mmpll3 = {
249 .l_reg = 0x0084,
250 .m_reg = 0x0088,
251 .n_reg = 0x008c,
252 .config_reg = 0x0090,
253 .mode_reg = 0x0080,
254 .status_reg = 0x009c,
255 .status_bit = 17,
256 .clkr.hw.init = &(struct clk_init_data){
257 .name = "mmpll3",
258 .parent_names = (const char *[]){ "xo" },
259 .num_parents = 1,
260 .ops = &clk_pll_ops,
261 },
262 };
263
264 static struct clk_rcg2 mmss_ahb_clk_src = {
265 .cmd_rcgr = 0x5000,
266 .hid_width = 5,
267 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
268 .clkr.hw.init = &(struct clk_init_data){
269 .name = "mmss_ahb_clk_src",
270 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
271 .num_parents = 4,
272 .ops = &clk_rcg2_ops,
273 },
274 };
275
276 static struct freq_tbl ftbl_mmss_axi_clk[] = {
277 F( 19200000, P_XO, 1, 0, 0),
278 F( 37500000, P_GPLL0, 16, 0, 0),
279 F( 50000000, P_GPLL0, 12, 0, 0),
280 F( 75000000, P_GPLL0, 8, 0, 0),
281 F(100000000, P_GPLL0, 6, 0, 0),
282 F(150000000, P_GPLL0, 4, 0, 0),
283 F(291750000, P_MMPLL1, 4, 0, 0),
284 F(400000000, P_MMPLL0, 2, 0, 0),
285 F(466800000, P_MMPLL1, 2.5, 0, 0),
286 };
287
288 static struct clk_rcg2 mmss_axi_clk_src = {
289 .cmd_rcgr = 0x5040,
290 .hid_width = 5,
291 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
292 .freq_tbl = ftbl_mmss_axi_clk,
293 .clkr.hw.init = &(struct clk_init_data){
294 .name = "mmss_axi_clk_src",
295 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
296 .num_parents = 4,
297 .ops = &clk_rcg2_ops,
298 },
299 };
300
301 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
302 F( 19200000, P_XO, 1, 0, 0),
303 F( 37500000, P_GPLL0, 16, 0, 0),
304 F( 50000000, P_GPLL0, 12, 0, 0),
305 F( 75000000, P_GPLL0, 8, 0, 0),
306 F(100000000, P_GPLL0, 6, 0, 0),
307 F(150000000, P_GPLL0, 4, 0, 0),
308 F(291750000, P_MMPLL1, 4, 0, 0),
309 F(400000000, P_MMPLL0, 2, 0, 0),
310 };
311
312 static struct clk_rcg2 ocmemnoc_clk_src = {
313 .cmd_rcgr = 0x5090,
314 .hid_width = 5,
315 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
316 .freq_tbl = ftbl_ocmemnoc_clk,
317 .clkr.hw.init = &(struct clk_init_data){
318 .name = "ocmemnoc_clk_src",
319 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
320 .num_parents = 4,
321 .ops = &clk_rcg2_ops,
322 },
323 };
324
325 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
326 F(100000000, P_GPLL0, 6, 0, 0),
327 F(200000000, P_MMPLL0, 4, 0, 0),
328 { }
329 };
330
331 static struct clk_rcg2 csi0_clk_src = {
332 .cmd_rcgr = 0x3090,
333 .hid_width = 5,
334 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
335 .freq_tbl = ftbl_camss_csi0_3_clk,
336 .clkr.hw.init = &(struct clk_init_data){
337 .name = "csi0_clk_src",
338 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
339 .num_parents = 4,
340 .ops = &clk_rcg2_ops,
341 },
342 };
343
344 static struct clk_rcg2 csi1_clk_src = {
345 .cmd_rcgr = 0x3100,
346 .hid_width = 5,
347 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
348 .freq_tbl = ftbl_camss_csi0_3_clk,
349 .clkr.hw.init = &(struct clk_init_data){
350 .name = "csi1_clk_src",
351 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
352 .num_parents = 4,
353 .ops = &clk_rcg2_ops,
354 },
355 };
356
357 static struct clk_rcg2 csi2_clk_src = {
358 .cmd_rcgr = 0x3160,
359 .hid_width = 5,
360 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
361 .freq_tbl = ftbl_camss_csi0_3_clk,
362 .clkr.hw.init = &(struct clk_init_data){
363 .name = "csi2_clk_src",
364 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
365 .num_parents = 4,
366 .ops = &clk_rcg2_ops,
367 },
368 };
369
370 static struct clk_rcg2 csi3_clk_src = {
371 .cmd_rcgr = 0x31c0,
372 .hid_width = 5,
373 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
374 .freq_tbl = ftbl_camss_csi0_3_clk,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "csi3_clk_src",
377 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
378 .num_parents = 4,
379 .ops = &clk_rcg2_ops,
380 },
381 };
382
383 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
384 F(37500000, P_GPLL0, 16, 0, 0),
385 F(50000000, P_GPLL0, 12, 0, 0),
386 F(60000000, P_GPLL0, 10, 0, 0),
387 F(80000000, P_GPLL0, 7.5, 0, 0),
388 F(100000000, P_GPLL0, 6, 0, 0),
389 F(109090000, P_GPLL0, 5.5, 0, 0),
390 F(133330000, P_GPLL0, 4.5, 0, 0),
391 F(200000000, P_GPLL0, 3, 0, 0),
392 F(228570000, P_MMPLL0, 3.5, 0, 0),
393 F(266670000, P_MMPLL0, 3, 0, 0),
394 F(320000000, P_MMPLL0, 2.5, 0, 0),
395 F(400000000, P_MMPLL0, 2, 0, 0),
396 F(465000000, P_MMPLL3, 2, 0, 0),
397 { }
398 };
399
400 static struct clk_rcg2 vfe0_clk_src = {
401 .cmd_rcgr = 0x3600,
402 .hid_width = 5,
403 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
404 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
405 .clkr.hw.init = &(struct clk_init_data){
406 .name = "vfe0_clk_src",
407 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
408 .num_parents = 4,
409 .ops = &clk_rcg2_ops,
410 },
411 };
412
413 static struct clk_rcg2 vfe1_clk_src = {
414 .cmd_rcgr = 0x3620,
415 .hid_width = 5,
416 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
417 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
418 .clkr.hw.init = &(struct clk_init_data){
419 .name = "vfe1_clk_src",
420 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
421 .num_parents = 4,
422 .ops = &clk_rcg2_ops,
423 },
424 };
425
426 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
427 F(37500000, P_GPLL0, 16, 0, 0),
428 F(60000000, P_GPLL0, 10, 0, 0),
429 F(75000000, P_GPLL0, 8, 0, 0),
430 F(85710000, P_GPLL0, 7, 0, 0),
431 F(100000000, P_GPLL0, 6, 0, 0),
432 F(133330000, P_MMPLL0, 6, 0, 0),
433 F(160000000, P_MMPLL0, 5, 0, 0),
434 F(200000000, P_MMPLL0, 4, 0, 0),
435 F(228570000, P_MMPLL0, 3.5, 0, 0),
436 F(240000000, P_GPLL0, 2.5, 0, 0),
437 F(266670000, P_MMPLL0, 3, 0, 0),
438 F(320000000, P_MMPLL0, 2.5, 0, 0),
439 { }
440 };
441
442 static struct clk_rcg2 mdp_clk_src = {
443 .cmd_rcgr = 0x2040,
444 .hid_width = 5,
445 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
446 .freq_tbl = ftbl_mdss_mdp_clk,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "mdp_clk_src",
449 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
450 .num_parents = 6,
451 .ops = &clk_rcg2_ops,
452 },
453 };
454
455 static struct clk_rcg2 gfx3d_clk_src = {
456 .cmd_rcgr = 0x4000,
457 .hid_width = 5,
458 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
459 .clkr.hw.init = &(struct clk_init_data){
460 .name = "gfx3d_clk_src",
461 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
462 .num_parents = 5,
463 .ops = &clk_rcg2_ops,
464 },
465 };
466
467 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
468 F(75000000, P_GPLL0, 8, 0, 0),
469 F(133330000, P_GPLL0, 4.5, 0, 0),
470 F(200000000, P_GPLL0, 3, 0, 0),
471 F(228570000, P_MMPLL0, 3.5, 0, 0),
472 F(266670000, P_MMPLL0, 3, 0, 0),
473 F(320000000, P_MMPLL0, 2.5, 0, 0),
474 { }
475 };
476
477 static struct clk_rcg2 jpeg0_clk_src = {
478 .cmd_rcgr = 0x3500,
479 .hid_width = 5,
480 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
481 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
482 .clkr.hw.init = &(struct clk_init_data){
483 .name = "jpeg0_clk_src",
484 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
485 .num_parents = 4,
486 .ops = &clk_rcg2_ops,
487 },
488 };
489
490 static struct clk_rcg2 jpeg1_clk_src = {
491 .cmd_rcgr = 0x3520,
492 .hid_width = 5,
493 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
494 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
495 .clkr.hw.init = &(struct clk_init_data){
496 .name = "jpeg1_clk_src",
497 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
498 .num_parents = 4,
499 .ops = &clk_rcg2_ops,
500 },
501 };
502
503 static struct clk_rcg2 jpeg2_clk_src = {
504 .cmd_rcgr = 0x3540,
505 .hid_width = 5,
506 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
507 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
508 .clkr.hw.init = &(struct clk_init_data){
509 .name = "jpeg2_clk_src",
510 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
511 .num_parents = 4,
512 .ops = &clk_rcg2_ops,
513 },
514 };
515
516 static struct clk_rcg2 pclk0_clk_src = {
517 .cmd_rcgr = 0x2000,
518 .mnd_width = 8,
519 .hid_width = 5,
520 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
521 .clkr.hw.init = &(struct clk_init_data){
522 .name = "pclk0_clk_src",
523 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
524 .num_parents = 6,
525 .ops = &clk_pixel_ops,
526 .flags = CLK_SET_RATE_PARENT,
527 },
528 };
529
530 static struct clk_rcg2 pclk1_clk_src = {
531 .cmd_rcgr = 0x2020,
532 .mnd_width = 8,
533 .hid_width = 5,
534 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
535 .clkr.hw.init = &(struct clk_init_data){
536 .name = "pclk1_clk_src",
537 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
538 .num_parents = 6,
539 .ops = &clk_pixel_ops,
540 .flags = CLK_SET_RATE_PARENT,
541 },
542 };
543
544 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
545 F(50000000, P_GPLL0, 12, 0, 0),
546 F(100000000, P_GPLL0, 6, 0, 0),
547 F(133330000, P_MMPLL0, 6, 0, 0),
548 F(200000000, P_MMPLL0, 4, 0, 0),
549 F(266670000, P_MMPLL0, 3, 0, 0),
550 F(465000000, P_MMPLL3, 2, 0, 0),
551 { }
552 };
553
554 static struct clk_rcg2 vcodec0_clk_src = {
555 .cmd_rcgr = 0x1000,
556 .mnd_width = 8,
557 .hid_width = 5,
558 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
559 .freq_tbl = ftbl_venus0_vcodec0_clk,
560 .clkr.hw.init = &(struct clk_init_data){
561 .name = "vcodec0_clk_src",
562 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
563 .num_parents = 5,
564 .ops = &clk_rcg2_ops,
565 },
566 };
567
568 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
569 F(19200000, P_XO, 1, 0, 0),
570 { }
571 };
572
573 static struct clk_rcg2 cci_clk_src = {
574 .cmd_rcgr = 0x3300,
575 .hid_width = 5,
576 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
577 .freq_tbl = ftbl_camss_cci_cci_clk,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "cci_clk_src",
580 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
581 .num_parents = 4,
582 .ops = &clk_rcg2_ops,
583 },
584 };
585
586 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
587 F(10000, P_XO, 16, 1, 120),
588 F(24000, P_XO, 16, 1, 50),
589 F(6000000, P_GPLL0, 10, 1, 10),
590 F(12000000, P_GPLL0, 10, 1, 5),
591 F(13000000, P_GPLL0, 4, 13, 150),
592 F(24000000, P_GPLL0, 5, 1, 5),
593 { }
594 };
595
596 static struct clk_rcg2 camss_gp0_clk_src = {
597 .cmd_rcgr = 0x3420,
598 .mnd_width = 8,
599 .hid_width = 5,
600 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
601 .freq_tbl = ftbl_camss_gp0_1_clk,
602 .clkr.hw.init = &(struct clk_init_data){
603 .name = "camss_gp0_clk_src",
604 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
605 .num_parents = 5,
606 .ops = &clk_rcg2_ops,
607 },
608 };
609
610 static struct clk_rcg2 camss_gp1_clk_src = {
611 .cmd_rcgr = 0x3450,
612 .mnd_width = 8,
613 .hid_width = 5,
614 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
615 .freq_tbl = ftbl_camss_gp0_1_clk,
616 .clkr.hw.init = &(struct clk_init_data){
617 .name = "camss_gp1_clk_src",
618 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
619 .num_parents = 5,
620 .ops = &clk_rcg2_ops,
621 },
622 };
623
624 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
625 F(4800000, P_XO, 4, 0, 0),
626 F(6000000, P_GPLL0, 10, 1, 10),
627 F(8000000, P_GPLL0, 15, 1, 5),
628 F(9600000, P_XO, 2, 0, 0),
629 F(16000000, P_GPLL0, 12.5, 1, 3),
630 F(19200000, P_XO, 1, 0, 0),
631 F(24000000, P_GPLL0, 5, 1, 5),
632 F(32000000, P_MMPLL0, 5, 1, 5),
633 F(48000000, P_GPLL0, 12.5, 0, 0),
634 F(64000000, P_MMPLL0, 12.5, 0, 0),
635 F(66670000, P_GPLL0, 9, 0, 0),
636 { }
637 };
638
639 static struct clk_rcg2 mclk0_clk_src = {
640 .cmd_rcgr = 0x3360,
641 .hid_width = 5,
642 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
643 .freq_tbl = ftbl_camss_mclk0_3_clk,
644 .clkr.hw.init = &(struct clk_init_data){
645 .name = "mclk0_clk_src",
646 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
647 .num_parents = 4,
648 .ops = &clk_rcg2_ops,
649 },
650 };
651
652 static struct clk_rcg2 mclk1_clk_src = {
653 .cmd_rcgr = 0x3390,
654 .hid_width = 5,
655 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
656 .freq_tbl = ftbl_camss_mclk0_3_clk,
657 .clkr.hw.init = &(struct clk_init_data){
658 .name = "mclk1_clk_src",
659 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
660 .num_parents = 4,
661 .ops = &clk_rcg2_ops,
662 },
663 };
664
665 static struct clk_rcg2 mclk2_clk_src = {
666 .cmd_rcgr = 0x33c0,
667 .hid_width = 5,
668 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
669 .freq_tbl = ftbl_camss_mclk0_3_clk,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "mclk2_clk_src",
672 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
673 .num_parents = 4,
674 .ops = &clk_rcg2_ops,
675 },
676 };
677
678 static struct clk_rcg2 mclk3_clk_src = {
679 .cmd_rcgr = 0x33f0,
680 .hid_width = 5,
681 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
682 .freq_tbl = ftbl_camss_mclk0_3_clk,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "mclk3_clk_src",
685 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
686 .num_parents = 4,
687 .ops = &clk_rcg2_ops,
688 },
689 };
690
691 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
692 F(100000000, P_GPLL0, 6, 0, 0),
693 F(200000000, P_MMPLL0, 4, 0, 0),
694 { }
695 };
696
697 static struct clk_rcg2 csi0phytimer_clk_src = {
698 .cmd_rcgr = 0x3000,
699 .hid_width = 5,
700 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
701 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
702 .clkr.hw.init = &(struct clk_init_data){
703 .name = "csi0phytimer_clk_src",
704 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
705 .num_parents = 4,
706 .ops = &clk_rcg2_ops,
707 },
708 };
709
710 static struct clk_rcg2 csi1phytimer_clk_src = {
711 .cmd_rcgr = 0x3030,
712 .hid_width = 5,
713 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
714 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "csi1phytimer_clk_src",
717 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
718 .num_parents = 4,
719 .ops = &clk_rcg2_ops,
720 },
721 };
722
723 static struct clk_rcg2 csi2phytimer_clk_src = {
724 .cmd_rcgr = 0x3060,
725 .hid_width = 5,
726 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
727 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
728 .clkr.hw.init = &(struct clk_init_data){
729 .name = "csi2phytimer_clk_src",
730 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
731 .num_parents = 4,
732 .ops = &clk_rcg2_ops,
733 },
734 };
735
736 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
737 F(133330000, P_GPLL0, 4.5, 0, 0),
738 F(266670000, P_MMPLL0, 3, 0, 0),
739 F(320000000, P_MMPLL0, 2.5, 0, 0),
740 F(400000000, P_MMPLL0, 2, 0, 0),
741 F(465000000, P_MMPLL3, 2, 0, 0),
742 { }
743 };
744
745 static struct clk_rcg2 cpp_clk_src = {
746 .cmd_rcgr = 0x3640,
747 .hid_width = 5,
748 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
749 .freq_tbl = ftbl_camss_vfe_cpp_clk,
750 .clkr.hw.init = &(struct clk_init_data){
751 .name = "cpp_clk_src",
752 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
753 .num_parents = 4,
754 .ops = &clk_rcg2_ops,
755 },
756 };
757
758 static struct freq_tbl byte_freq_tbl[] = {
759 { .src = P_DSI0PLL_BYTE },
760 { }
761 };
762
763 static struct clk_rcg2 byte0_clk_src = {
764 .cmd_rcgr = 0x2120,
765 .hid_width = 5,
766 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
767 .freq_tbl = byte_freq_tbl,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "byte0_clk_src",
770 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
771 .num_parents = 6,
772 .ops = &clk_byte2_ops,
773 .flags = CLK_SET_RATE_PARENT,
774 },
775 };
776
777 static struct clk_rcg2 byte1_clk_src = {
778 .cmd_rcgr = 0x2140,
779 .hid_width = 5,
780 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
781 .freq_tbl = byte_freq_tbl,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "byte1_clk_src",
784 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
785 .num_parents = 6,
786 .ops = &clk_byte2_ops,
787 .flags = CLK_SET_RATE_PARENT,
788 },
789 };
790
791 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
792 F(19200000, P_XO, 1, 0, 0),
793 { }
794 };
795
796 static struct clk_rcg2 edpaux_clk_src = {
797 .cmd_rcgr = 0x20e0,
798 .hid_width = 5,
799 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
800 .freq_tbl = ftbl_mdss_edpaux_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "edpaux_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
804 .num_parents = 4,
805 .ops = &clk_rcg2_ops,
806 },
807 };
808
809 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
810 F(135000000, P_EDPLINK, 2, 0, 0),
811 F(270000000, P_EDPLINK, 11, 0, 0),
812 { }
813 };
814
815 static struct clk_rcg2 edplink_clk_src = {
816 .cmd_rcgr = 0x20c0,
817 .hid_width = 5,
818 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
819 .freq_tbl = ftbl_mdss_edplink_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "edplink_clk_src",
822 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
823 .num_parents = 6,
824 .ops = &clk_rcg2_ops,
825 .flags = CLK_SET_RATE_PARENT,
826 },
827 };
828
829 static struct freq_tbl edp_pixel_freq_tbl[] = {
830 { .src = P_EDPVCO },
831 { }
832 };
833
834 static struct clk_rcg2 edppixel_clk_src = {
835 .cmd_rcgr = 0x20a0,
836 .mnd_width = 8,
837 .hid_width = 5,
838 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
839 .freq_tbl = edp_pixel_freq_tbl,
840 .clkr.hw.init = &(struct clk_init_data){
841 .name = "edppixel_clk_src",
842 .parent_names = mmcc_xo_dsi_hdmi_edp,
843 .num_parents = 6,
844 .ops = &clk_edp_pixel_ops,
845 },
846 };
847
848 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
849 F(19200000, P_XO, 1, 0, 0),
850 { }
851 };
852
853 static struct clk_rcg2 esc0_clk_src = {
854 .cmd_rcgr = 0x2160,
855 .hid_width = 5,
856 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
857 .freq_tbl = ftbl_mdss_esc0_1_clk,
858 .clkr.hw.init = &(struct clk_init_data){
859 .name = "esc0_clk_src",
860 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
861 .num_parents = 6,
862 .ops = &clk_rcg2_ops,
863 },
864 };
865
866 static struct clk_rcg2 esc1_clk_src = {
867 .cmd_rcgr = 0x2180,
868 .hid_width = 5,
869 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
870 .freq_tbl = ftbl_mdss_esc0_1_clk,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "esc1_clk_src",
873 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
874 .num_parents = 6,
875 .ops = &clk_rcg2_ops,
876 },
877 };
878
879 static struct freq_tbl extpclk_freq_tbl[] = {
880 { .src = P_HDMIPLL },
881 { }
882 };
883
884 static struct clk_rcg2 extpclk_clk_src = {
885 .cmd_rcgr = 0x2060,
886 .hid_width = 5,
887 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
888 .freq_tbl = extpclk_freq_tbl,
889 .clkr.hw.init = &(struct clk_init_data){
890 .name = "extpclk_clk_src",
891 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
892 .num_parents = 6,
893 .ops = &clk_byte_ops,
894 .flags = CLK_SET_RATE_PARENT,
895 },
896 };
897
898 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
899 F(19200000, P_XO, 1, 0, 0),
900 { }
901 };
902
903 static struct clk_rcg2 hdmi_clk_src = {
904 .cmd_rcgr = 0x2100,
905 .hid_width = 5,
906 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
907 .freq_tbl = ftbl_mdss_hdmi_clk,
908 .clkr.hw.init = &(struct clk_init_data){
909 .name = "hdmi_clk_src",
910 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
911 .num_parents = 4,
912 .ops = &clk_rcg2_ops,
913 },
914 };
915
916 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
917 F(19200000, P_XO, 1, 0, 0),
918 { }
919 };
920
921 static struct clk_rcg2 vsync_clk_src = {
922 .cmd_rcgr = 0x2080,
923 .hid_width = 5,
924 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
925 .freq_tbl = ftbl_mdss_vsync_clk,
926 .clkr.hw.init = &(struct clk_init_data){
927 .name = "vsync_clk_src",
928 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
929 .num_parents = 4,
930 .ops = &clk_rcg2_ops,
931 },
932 };
933
934 static struct clk_branch camss_cci_cci_ahb_clk = {
935 .halt_reg = 0x3348,
936 .clkr = {
937 .enable_reg = 0x3348,
938 .enable_mask = BIT(0),
939 .hw.init = &(struct clk_init_data){
940 .name = "camss_cci_cci_ahb_clk",
941 .parent_names = (const char *[]){
942 "mmss_ahb_clk_src",
943 },
944 .num_parents = 1,
945 .ops = &clk_branch2_ops,
946 },
947 },
948 };
949
950 static struct clk_branch camss_cci_cci_clk = {
951 .halt_reg = 0x3344,
952 .clkr = {
953 .enable_reg = 0x3344,
954 .enable_mask = BIT(0),
955 .hw.init = &(struct clk_init_data){
956 .name = "camss_cci_cci_clk",
957 .parent_names = (const char *[]){
958 "cci_clk_src",
959 },
960 .num_parents = 1,
961 .flags = CLK_SET_RATE_PARENT,
962 .ops = &clk_branch2_ops,
963 },
964 },
965 };
966
967 static struct clk_branch camss_csi0_ahb_clk = {
968 .halt_reg = 0x30bc,
969 .clkr = {
970 .enable_reg = 0x30bc,
971 .enable_mask = BIT(0),
972 .hw.init = &(struct clk_init_data){
973 .name = "camss_csi0_ahb_clk",
974 .parent_names = (const char *[]){
975 "mmss_ahb_clk_src",
976 },
977 .num_parents = 1,
978 .ops = &clk_branch2_ops,
979 },
980 },
981 };
982
983 static struct clk_branch camss_csi0_clk = {
984 .halt_reg = 0x30b4,
985 .clkr = {
986 .enable_reg = 0x30b4,
987 .enable_mask = BIT(0),
988 .hw.init = &(struct clk_init_data){
989 .name = "camss_csi0_clk",
990 .parent_names = (const char *[]){
991 "csi0_clk_src",
992 },
993 .num_parents = 1,
994 .flags = CLK_SET_RATE_PARENT,
995 .ops = &clk_branch2_ops,
996 },
997 },
998 };
999
1000 static struct clk_branch camss_csi0phy_clk = {
1001 .halt_reg = 0x30c4,
1002 .clkr = {
1003 .enable_reg = 0x30c4,
1004 .enable_mask = BIT(0),
1005 .hw.init = &(struct clk_init_data){
1006 .name = "camss_csi0phy_clk",
1007 .parent_names = (const char *[]){
1008 "csi0_clk_src",
1009 },
1010 .num_parents = 1,
1011 .flags = CLK_SET_RATE_PARENT,
1012 .ops = &clk_branch2_ops,
1013 },
1014 },
1015 };
1016
1017 static struct clk_branch camss_csi0pix_clk = {
1018 .halt_reg = 0x30e4,
1019 .clkr = {
1020 .enable_reg = 0x30e4,
1021 .enable_mask = BIT(0),
1022 .hw.init = &(struct clk_init_data){
1023 .name = "camss_csi0pix_clk",
1024 .parent_names = (const char *[]){
1025 "csi0_clk_src",
1026 },
1027 .num_parents = 1,
1028 .flags = CLK_SET_RATE_PARENT,
1029 .ops = &clk_branch2_ops,
1030 },
1031 },
1032 };
1033
1034 static struct clk_branch camss_csi0rdi_clk = {
1035 .halt_reg = 0x30d4,
1036 .clkr = {
1037 .enable_reg = 0x30d4,
1038 .enable_mask = BIT(0),
1039 .hw.init = &(struct clk_init_data){
1040 .name = "camss_csi0rdi_clk",
1041 .parent_names = (const char *[]){
1042 "csi0_clk_src",
1043 },
1044 .num_parents = 1,
1045 .flags = CLK_SET_RATE_PARENT,
1046 .ops = &clk_branch2_ops,
1047 },
1048 },
1049 };
1050
1051 static struct clk_branch camss_csi1_ahb_clk = {
1052 .halt_reg = 0x3128,
1053 .clkr = {
1054 .enable_reg = 0x3128,
1055 .enable_mask = BIT(0),
1056 .hw.init = &(struct clk_init_data){
1057 .name = "camss_csi1_ahb_clk",
1058 .parent_names = (const char *[]){
1059 "mmss_ahb_clk_src",
1060 },
1061 .num_parents = 1,
1062 .ops = &clk_branch2_ops,
1063 },
1064 },
1065 };
1066
1067 static struct clk_branch camss_csi1_clk = {
1068 .halt_reg = 0x3124,
1069 .clkr = {
1070 .enable_reg = 0x3124,
1071 .enable_mask = BIT(0),
1072 .hw.init = &(struct clk_init_data){
1073 .name = "camss_csi1_clk",
1074 .parent_names = (const char *[]){
1075 "csi1_clk_src",
1076 },
1077 .num_parents = 1,
1078 .flags = CLK_SET_RATE_PARENT,
1079 .ops = &clk_branch2_ops,
1080 },
1081 },
1082 };
1083
1084 static struct clk_branch camss_csi1phy_clk = {
1085 .halt_reg = 0x3134,
1086 .clkr = {
1087 .enable_reg = 0x3134,
1088 .enable_mask = BIT(0),
1089 .hw.init = &(struct clk_init_data){
1090 .name = "camss_csi1phy_clk",
1091 .parent_names = (const char *[]){
1092 "csi1_clk_src",
1093 },
1094 .num_parents = 1,
1095 .flags = CLK_SET_RATE_PARENT,
1096 .ops = &clk_branch2_ops,
1097 },
1098 },
1099 };
1100
1101 static struct clk_branch camss_csi1pix_clk = {
1102 .halt_reg = 0x3154,
1103 .clkr = {
1104 .enable_reg = 0x3154,
1105 .enable_mask = BIT(0),
1106 .hw.init = &(struct clk_init_data){
1107 .name = "camss_csi1pix_clk",
1108 .parent_names = (const char *[]){
1109 "csi1_clk_src",
1110 },
1111 .num_parents = 1,
1112 .flags = CLK_SET_RATE_PARENT,
1113 .ops = &clk_branch2_ops,
1114 },
1115 },
1116 };
1117
1118 static struct clk_branch camss_csi1rdi_clk = {
1119 .halt_reg = 0x3144,
1120 .clkr = {
1121 .enable_reg = 0x3144,
1122 .enable_mask = BIT(0),
1123 .hw.init = &(struct clk_init_data){
1124 .name = "camss_csi1rdi_clk",
1125 .parent_names = (const char *[]){
1126 "csi1_clk_src",
1127 },
1128 .num_parents = 1,
1129 .flags = CLK_SET_RATE_PARENT,
1130 .ops = &clk_branch2_ops,
1131 },
1132 },
1133 };
1134
1135 static struct clk_branch camss_csi2_ahb_clk = {
1136 .halt_reg = 0x3188,
1137 .clkr = {
1138 .enable_reg = 0x3188,
1139 .enable_mask = BIT(0),
1140 .hw.init = &(struct clk_init_data){
1141 .name = "camss_csi2_ahb_clk",
1142 .parent_names = (const char *[]){
1143 "mmss_ahb_clk_src",
1144 },
1145 .num_parents = 1,
1146 .ops = &clk_branch2_ops,
1147 },
1148 },
1149 };
1150
1151 static struct clk_branch camss_csi2_clk = {
1152 .halt_reg = 0x3184,
1153 .clkr = {
1154 .enable_reg = 0x3184,
1155 .enable_mask = BIT(0),
1156 .hw.init = &(struct clk_init_data){
1157 .name = "camss_csi2_clk",
1158 .parent_names = (const char *[]){
1159 "csi2_clk_src",
1160 },
1161 .num_parents = 1,
1162 .flags = CLK_SET_RATE_PARENT,
1163 .ops = &clk_branch2_ops,
1164 },
1165 },
1166 };
1167
1168 static struct clk_branch camss_csi2phy_clk = {
1169 .halt_reg = 0x3194,
1170 .clkr = {
1171 .enable_reg = 0x3194,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data){
1174 .name = "camss_csi2phy_clk",
1175 .parent_names = (const char *[]){
1176 "csi2_clk_src",
1177 },
1178 .num_parents = 1,
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_branch2_ops,
1181 },
1182 },
1183 };
1184
1185 static struct clk_branch camss_csi2pix_clk = {
1186 .halt_reg = 0x31b4,
1187 .clkr = {
1188 .enable_reg = 0x31b4,
1189 .enable_mask = BIT(0),
1190 .hw.init = &(struct clk_init_data){
1191 .name = "camss_csi2pix_clk",
1192 .parent_names = (const char *[]){
1193 "csi2_clk_src",
1194 },
1195 .num_parents = 1,
1196 .flags = CLK_SET_RATE_PARENT,
1197 .ops = &clk_branch2_ops,
1198 },
1199 },
1200 };
1201
1202 static struct clk_branch camss_csi2rdi_clk = {
1203 .halt_reg = 0x31a4,
1204 .clkr = {
1205 .enable_reg = 0x31a4,
1206 .enable_mask = BIT(0),
1207 .hw.init = &(struct clk_init_data){
1208 .name = "camss_csi2rdi_clk",
1209 .parent_names = (const char *[]){
1210 "csi2_clk_src",
1211 },
1212 .num_parents = 1,
1213 .flags = CLK_SET_RATE_PARENT,
1214 .ops = &clk_branch2_ops,
1215 },
1216 },
1217 };
1218
1219 static struct clk_branch camss_csi3_ahb_clk = {
1220 .halt_reg = 0x31e8,
1221 .clkr = {
1222 .enable_reg = 0x31e8,
1223 .enable_mask = BIT(0),
1224 .hw.init = &(struct clk_init_data){
1225 .name = "camss_csi3_ahb_clk",
1226 .parent_names = (const char *[]){
1227 "mmss_ahb_clk_src",
1228 },
1229 .num_parents = 1,
1230 .ops = &clk_branch2_ops,
1231 },
1232 },
1233 };
1234
1235 static struct clk_branch camss_csi3_clk = {
1236 .halt_reg = 0x31e4,
1237 .clkr = {
1238 .enable_reg = 0x31e4,
1239 .enable_mask = BIT(0),
1240 .hw.init = &(struct clk_init_data){
1241 .name = "camss_csi3_clk",
1242 .parent_names = (const char *[]){
1243 "csi3_clk_src",
1244 },
1245 .num_parents = 1,
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1248 },
1249 },
1250 };
1251
1252 static struct clk_branch camss_csi3phy_clk = {
1253 .halt_reg = 0x31f4,
1254 .clkr = {
1255 .enable_reg = 0x31f4,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "camss_csi3phy_clk",
1259 .parent_names = (const char *[]){
1260 "csi3_clk_src",
1261 },
1262 .num_parents = 1,
1263 .flags = CLK_SET_RATE_PARENT,
1264 .ops = &clk_branch2_ops,
1265 },
1266 },
1267 };
1268
1269 static struct clk_branch camss_csi3pix_clk = {
1270 .halt_reg = 0x3214,
1271 .clkr = {
1272 .enable_reg = 0x3214,
1273 .enable_mask = BIT(0),
1274 .hw.init = &(struct clk_init_data){
1275 .name = "camss_csi3pix_clk",
1276 .parent_names = (const char *[]){
1277 "csi3_clk_src",
1278 },
1279 .num_parents = 1,
1280 .flags = CLK_SET_RATE_PARENT,
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch camss_csi3rdi_clk = {
1287 .halt_reg = 0x3204,
1288 .clkr = {
1289 .enable_reg = 0x3204,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "camss_csi3rdi_clk",
1293 .parent_names = (const char *[]){
1294 "csi3_clk_src",
1295 },
1296 .num_parents = 1,
1297 .flags = CLK_SET_RATE_PARENT,
1298 .ops = &clk_branch2_ops,
1299 },
1300 },
1301 };
1302
1303 static struct clk_branch camss_csi_vfe0_clk = {
1304 .halt_reg = 0x3704,
1305 .clkr = {
1306 .enable_reg = 0x3704,
1307 .enable_mask = BIT(0),
1308 .hw.init = &(struct clk_init_data){
1309 .name = "camss_csi_vfe0_clk",
1310 .parent_names = (const char *[]){
1311 "vfe0_clk_src",
1312 },
1313 .num_parents = 1,
1314 .flags = CLK_SET_RATE_PARENT,
1315 .ops = &clk_branch2_ops,
1316 },
1317 },
1318 };
1319
1320 static struct clk_branch camss_csi_vfe1_clk = {
1321 .halt_reg = 0x3714,
1322 .clkr = {
1323 .enable_reg = 0x3714,
1324 .enable_mask = BIT(0),
1325 .hw.init = &(struct clk_init_data){
1326 .name = "camss_csi_vfe1_clk",
1327 .parent_names = (const char *[]){
1328 "vfe1_clk_src",
1329 },
1330 .num_parents = 1,
1331 .flags = CLK_SET_RATE_PARENT,
1332 .ops = &clk_branch2_ops,
1333 },
1334 },
1335 };
1336
1337 static struct clk_branch camss_gp0_clk = {
1338 .halt_reg = 0x3444,
1339 .clkr = {
1340 .enable_reg = 0x3444,
1341 .enable_mask = BIT(0),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "camss_gp0_clk",
1344 .parent_names = (const char *[]){
1345 "camss_gp0_clk_src",
1346 },
1347 .num_parents = 1,
1348 .flags = CLK_SET_RATE_PARENT,
1349 .ops = &clk_branch2_ops,
1350 },
1351 },
1352 };
1353
1354 static struct clk_branch camss_gp1_clk = {
1355 .halt_reg = 0x3474,
1356 .clkr = {
1357 .enable_reg = 0x3474,
1358 .enable_mask = BIT(0),
1359 .hw.init = &(struct clk_init_data){
1360 .name = "camss_gp1_clk",
1361 .parent_names = (const char *[]){
1362 "camss_gp1_clk_src",
1363 },
1364 .num_parents = 1,
1365 .flags = CLK_SET_RATE_PARENT,
1366 .ops = &clk_branch2_ops,
1367 },
1368 },
1369 };
1370
1371 static struct clk_branch camss_ispif_ahb_clk = {
1372 .halt_reg = 0x3224,
1373 .clkr = {
1374 .enable_reg = 0x3224,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data){
1377 .name = "camss_ispif_ahb_clk",
1378 .parent_names = (const char *[]){
1379 "mmss_ahb_clk_src",
1380 },
1381 .num_parents = 1,
1382 .ops = &clk_branch2_ops,
1383 },
1384 },
1385 };
1386
1387 static struct clk_branch camss_jpeg_jpeg0_clk = {
1388 .halt_reg = 0x35a8,
1389 .clkr = {
1390 .enable_reg = 0x35a8,
1391 .enable_mask = BIT(0),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "camss_jpeg_jpeg0_clk",
1394 .parent_names = (const char *[]){
1395 "jpeg0_clk_src",
1396 },
1397 .num_parents = 1,
1398 .flags = CLK_SET_RATE_PARENT,
1399 .ops = &clk_branch2_ops,
1400 },
1401 },
1402 };
1403
1404 static struct clk_branch camss_jpeg_jpeg1_clk = {
1405 .halt_reg = 0x35ac,
1406 .clkr = {
1407 .enable_reg = 0x35ac,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "camss_jpeg_jpeg1_clk",
1411 .parent_names = (const char *[]){
1412 "jpeg1_clk_src",
1413 },
1414 .num_parents = 1,
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419 };
1420
1421 static struct clk_branch camss_jpeg_jpeg2_clk = {
1422 .halt_reg = 0x35b0,
1423 .clkr = {
1424 .enable_reg = 0x35b0,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "camss_jpeg_jpeg2_clk",
1428 .parent_names = (const char *[]){
1429 "jpeg2_clk_src",
1430 },
1431 .num_parents = 1,
1432 .flags = CLK_SET_RATE_PARENT,
1433 .ops = &clk_branch2_ops,
1434 },
1435 },
1436 };
1437
1438 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1439 .halt_reg = 0x35b4,
1440 .clkr = {
1441 .enable_reg = 0x35b4,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "camss_jpeg_jpeg_ahb_clk",
1445 .parent_names = (const char *[]){
1446 "mmss_ahb_clk_src",
1447 },
1448 .num_parents = 1,
1449 .ops = &clk_branch2_ops,
1450 },
1451 },
1452 };
1453
1454 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1455 .halt_reg = 0x35b8,
1456 .clkr = {
1457 .enable_reg = 0x35b8,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "camss_jpeg_jpeg_axi_clk",
1461 .parent_names = (const char *[]){
1462 "mmss_axi_clk_src",
1463 },
1464 .num_parents = 1,
1465 .ops = &clk_branch2_ops,
1466 },
1467 },
1468 };
1469
1470 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1471 .halt_reg = 0x35bc,
1472 .clkr = {
1473 .enable_reg = 0x35bc,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1477 .parent_names = (const char *[]){
1478 "ocmemnoc_clk_src",
1479 },
1480 .num_parents = 1,
1481 .flags = CLK_SET_RATE_PARENT,
1482 .ops = &clk_branch2_ops,
1483 },
1484 },
1485 };
1486
1487 static struct clk_branch camss_mclk0_clk = {
1488 .halt_reg = 0x3384,
1489 .clkr = {
1490 .enable_reg = 0x3384,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(struct clk_init_data){
1493 .name = "camss_mclk0_clk",
1494 .parent_names = (const char *[]){
1495 "mclk0_clk_src",
1496 },
1497 .num_parents = 1,
1498 .flags = CLK_SET_RATE_PARENT,
1499 .ops = &clk_branch2_ops,
1500 },
1501 },
1502 };
1503
1504 static struct clk_branch camss_mclk1_clk = {
1505 .halt_reg = 0x33b4,
1506 .clkr = {
1507 .enable_reg = 0x33b4,
1508 .enable_mask = BIT(0),
1509 .hw.init = &(struct clk_init_data){
1510 .name = "camss_mclk1_clk",
1511 .parent_names = (const char *[]){
1512 "mclk1_clk_src",
1513 },
1514 .num_parents = 1,
1515 .flags = CLK_SET_RATE_PARENT,
1516 .ops = &clk_branch2_ops,
1517 },
1518 },
1519 };
1520
1521 static struct clk_branch camss_mclk2_clk = {
1522 .halt_reg = 0x33e4,
1523 .clkr = {
1524 .enable_reg = 0x33e4,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "camss_mclk2_clk",
1528 .parent_names = (const char *[]){
1529 "mclk2_clk_src",
1530 },
1531 .num_parents = 1,
1532 .flags = CLK_SET_RATE_PARENT,
1533 .ops = &clk_branch2_ops,
1534 },
1535 },
1536 };
1537
1538 static struct clk_branch camss_mclk3_clk = {
1539 .halt_reg = 0x3414,
1540 .clkr = {
1541 .enable_reg = 0x3414,
1542 .enable_mask = BIT(0),
1543 .hw.init = &(struct clk_init_data){
1544 .name = "camss_mclk3_clk",
1545 .parent_names = (const char *[]){
1546 "mclk3_clk_src",
1547 },
1548 .num_parents = 1,
1549 .flags = CLK_SET_RATE_PARENT,
1550 .ops = &clk_branch2_ops,
1551 },
1552 },
1553 };
1554
1555 static struct clk_branch camss_micro_ahb_clk = {
1556 .halt_reg = 0x3494,
1557 .clkr = {
1558 .enable_reg = 0x3494,
1559 .enable_mask = BIT(0),
1560 .hw.init = &(struct clk_init_data){
1561 .name = "camss_micro_ahb_clk",
1562 .parent_names = (const char *[]){
1563 "mmss_ahb_clk_src",
1564 },
1565 .num_parents = 1,
1566 .ops = &clk_branch2_ops,
1567 },
1568 },
1569 };
1570
1571 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1572 .halt_reg = 0x3024,
1573 .clkr = {
1574 .enable_reg = 0x3024,
1575 .enable_mask = BIT(0),
1576 .hw.init = &(struct clk_init_data){
1577 .name = "camss_phy0_csi0phytimer_clk",
1578 .parent_names = (const char *[]){
1579 "csi0phytimer_clk_src",
1580 },
1581 .num_parents = 1,
1582 .flags = CLK_SET_RATE_PARENT,
1583 .ops = &clk_branch2_ops,
1584 },
1585 },
1586 };
1587
1588 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1589 .halt_reg = 0x3054,
1590 .clkr = {
1591 .enable_reg = 0x3054,
1592 .enable_mask = BIT(0),
1593 .hw.init = &(struct clk_init_data){
1594 .name = "camss_phy1_csi1phytimer_clk",
1595 .parent_names = (const char *[]){
1596 "csi1phytimer_clk_src",
1597 },
1598 .num_parents = 1,
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1601 },
1602 },
1603 };
1604
1605 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1606 .halt_reg = 0x3084,
1607 .clkr = {
1608 .enable_reg = 0x3084,
1609 .enable_mask = BIT(0),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "camss_phy2_csi2phytimer_clk",
1612 .parent_names = (const char *[]){
1613 "csi2phytimer_clk_src",
1614 },
1615 .num_parents = 1,
1616 .flags = CLK_SET_RATE_PARENT,
1617 .ops = &clk_branch2_ops,
1618 },
1619 },
1620 };
1621
1622 static struct clk_branch camss_top_ahb_clk = {
1623 .halt_reg = 0x3484,
1624 .clkr = {
1625 .enable_reg = 0x3484,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "camss_top_ahb_clk",
1629 .parent_names = (const char *[]){
1630 "mmss_ahb_clk_src",
1631 },
1632 .num_parents = 1,
1633 .ops = &clk_branch2_ops,
1634 },
1635 },
1636 };
1637
1638 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1639 .halt_reg = 0x36b4,
1640 .clkr = {
1641 .enable_reg = 0x36b4,
1642 .enable_mask = BIT(0),
1643 .hw.init = &(struct clk_init_data){
1644 .name = "camss_vfe_cpp_ahb_clk",
1645 .parent_names = (const char *[]){
1646 "mmss_ahb_clk_src",
1647 },
1648 .num_parents = 1,
1649 .ops = &clk_branch2_ops,
1650 },
1651 },
1652 };
1653
1654 static struct clk_branch camss_vfe_cpp_clk = {
1655 .halt_reg = 0x36b0,
1656 .clkr = {
1657 .enable_reg = 0x36b0,
1658 .enable_mask = BIT(0),
1659 .hw.init = &(struct clk_init_data){
1660 .name = "camss_vfe_cpp_clk",
1661 .parent_names = (const char *[]){
1662 "cpp_clk_src",
1663 },
1664 .num_parents = 1,
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669 };
1670
1671 static struct clk_branch camss_vfe_vfe0_clk = {
1672 .halt_reg = 0x36a8,
1673 .clkr = {
1674 .enable_reg = 0x36a8,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "camss_vfe_vfe0_clk",
1678 .parent_names = (const char *[]){
1679 "vfe0_clk_src",
1680 },
1681 .num_parents = 1,
1682 .flags = CLK_SET_RATE_PARENT,
1683 .ops = &clk_branch2_ops,
1684 },
1685 },
1686 };
1687
1688 static struct clk_branch camss_vfe_vfe1_clk = {
1689 .halt_reg = 0x36ac,
1690 .clkr = {
1691 .enable_reg = 0x36ac,
1692 .enable_mask = BIT(0),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "camss_vfe_vfe1_clk",
1695 .parent_names = (const char *[]){
1696 "vfe1_clk_src",
1697 },
1698 .num_parents = 1,
1699 .flags = CLK_SET_RATE_PARENT,
1700 .ops = &clk_branch2_ops,
1701 },
1702 },
1703 };
1704
1705 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1706 .halt_reg = 0x36b8,
1707 .clkr = {
1708 .enable_reg = 0x36b8,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "camss_vfe_vfe_ahb_clk",
1712 .parent_names = (const char *[]){
1713 "mmss_ahb_clk_src",
1714 },
1715 .num_parents = 1,
1716 .ops = &clk_branch2_ops,
1717 },
1718 },
1719 };
1720
1721 static struct clk_branch camss_vfe_vfe_axi_clk = {
1722 .halt_reg = 0x36bc,
1723 .clkr = {
1724 .enable_reg = 0x36bc,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "camss_vfe_vfe_axi_clk",
1728 .parent_names = (const char *[]){
1729 "mmss_axi_clk_src",
1730 },
1731 .num_parents = 1,
1732 .ops = &clk_branch2_ops,
1733 },
1734 },
1735 };
1736
1737 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1738 .halt_reg = 0x36c0,
1739 .clkr = {
1740 .enable_reg = 0x36c0,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "camss_vfe_vfe_ocmemnoc_clk",
1744 .parent_names = (const char *[]){
1745 "ocmemnoc_clk_src",
1746 },
1747 .num_parents = 1,
1748 .flags = CLK_SET_RATE_PARENT,
1749 .ops = &clk_branch2_ops,
1750 },
1751 },
1752 };
1753
1754 static struct clk_branch mdss_ahb_clk = {
1755 .halt_reg = 0x2308,
1756 .clkr = {
1757 .enable_reg = 0x2308,
1758 .enable_mask = BIT(0),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "mdss_ahb_clk",
1761 .parent_names = (const char *[]){
1762 "mmss_ahb_clk_src",
1763 },
1764 .num_parents = 1,
1765 .ops = &clk_branch2_ops,
1766 },
1767 },
1768 };
1769
1770 static struct clk_branch mdss_axi_clk = {
1771 .halt_reg = 0x2310,
1772 .clkr = {
1773 .enable_reg = 0x2310,
1774 .enable_mask = BIT(0),
1775 .hw.init = &(struct clk_init_data){
1776 .name = "mdss_axi_clk",
1777 .parent_names = (const char *[]){
1778 "mmss_axi_clk_src",
1779 },
1780 .num_parents = 1,
1781 .flags = CLK_SET_RATE_PARENT,
1782 .ops = &clk_branch2_ops,
1783 },
1784 },
1785 };
1786
1787 static struct clk_branch mdss_byte0_clk = {
1788 .halt_reg = 0x233c,
1789 .clkr = {
1790 .enable_reg = 0x233c,
1791 .enable_mask = BIT(0),
1792 .hw.init = &(struct clk_init_data){
1793 .name = "mdss_byte0_clk",
1794 .parent_names = (const char *[]){
1795 "byte0_clk_src",
1796 },
1797 .num_parents = 1,
1798 .flags = CLK_SET_RATE_PARENT,
1799 .ops = &clk_branch2_ops,
1800 },
1801 },
1802 };
1803
1804 static struct clk_branch mdss_byte1_clk = {
1805 .halt_reg = 0x2340,
1806 .clkr = {
1807 .enable_reg = 0x2340,
1808 .enable_mask = BIT(0),
1809 .hw.init = &(struct clk_init_data){
1810 .name = "mdss_byte1_clk",
1811 .parent_names = (const char *[]){
1812 "byte1_clk_src",
1813 },
1814 .num_parents = 1,
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1817 },
1818 },
1819 };
1820
1821 static struct clk_branch mdss_edpaux_clk = {
1822 .halt_reg = 0x2334,
1823 .clkr = {
1824 .enable_reg = 0x2334,
1825 .enable_mask = BIT(0),
1826 .hw.init = &(struct clk_init_data){
1827 .name = "mdss_edpaux_clk",
1828 .parent_names = (const char *[]){
1829 "edpaux_clk_src",
1830 },
1831 .num_parents = 1,
1832 .flags = CLK_SET_RATE_PARENT,
1833 .ops = &clk_branch2_ops,
1834 },
1835 },
1836 };
1837
1838 static struct clk_branch mdss_edplink_clk = {
1839 .halt_reg = 0x2330,
1840 .clkr = {
1841 .enable_reg = 0x2330,
1842 .enable_mask = BIT(0),
1843 .hw.init = &(struct clk_init_data){
1844 .name = "mdss_edplink_clk",
1845 .parent_names = (const char *[]){
1846 "edplink_clk_src",
1847 },
1848 .num_parents = 1,
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1851 },
1852 },
1853 };
1854
1855 static struct clk_branch mdss_edppixel_clk = {
1856 .halt_reg = 0x232c,
1857 .clkr = {
1858 .enable_reg = 0x232c,
1859 .enable_mask = BIT(0),
1860 .hw.init = &(struct clk_init_data){
1861 .name = "mdss_edppixel_clk",
1862 .parent_names = (const char *[]){
1863 "edppixel_clk_src",
1864 },
1865 .num_parents = 1,
1866 .flags = CLK_SET_RATE_PARENT,
1867 .ops = &clk_branch2_ops,
1868 },
1869 },
1870 };
1871
1872 static struct clk_branch mdss_esc0_clk = {
1873 .halt_reg = 0x2344,
1874 .clkr = {
1875 .enable_reg = 0x2344,
1876 .enable_mask = BIT(0),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "mdss_esc0_clk",
1879 .parent_names = (const char *[]){
1880 "esc0_clk_src",
1881 },
1882 .num_parents = 1,
1883 .flags = CLK_SET_RATE_PARENT,
1884 .ops = &clk_branch2_ops,
1885 },
1886 },
1887 };
1888
1889 static struct clk_branch mdss_esc1_clk = {
1890 .halt_reg = 0x2348,
1891 .clkr = {
1892 .enable_reg = 0x2348,
1893 .enable_mask = BIT(0),
1894 .hw.init = &(struct clk_init_data){
1895 .name = "mdss_esc1_clk",
1896 .parent_names = (const char *[]){
1897 "esc1_clk_src",
1898 },
1899 .num_parents = 1,
1900 .flags = CLK_SET_RATE_PARENT,
1901 .ops = &clk_branch2_ops,
1902 },
1903 },
1904 };
1905
1906 static struct clk_branch mdss_extpclk_clk = {
1907 .halt_reg = 0x2324,
1908 .clkr = {
1909 .enable_reg = 0x2324,
1910 .enable_mask = BIT(0),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "mdss_extpclk_clk",
1913 .parent_names = (const char *[]){
1914 "extpclk_clk_src",
1915 },
1916 .num_parents = 1,
1917 .flags = CLK_SET_RATE_PARENT,
1918 .ops = &clk_branch2_ops,
1919 },
1920 },
1921 };
1922
1923 static struct clk_branch mdss_hdmi_ahb_clk = {
1924 .halt_reg = 0x230c,
1925 .clkr = {
1926 .enable_reg = 0x230c,
1927 .enable_mask = BIT(0),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "mdss_hdmi_ahb_clk",
1930 .parent_names = (const char *[]){
1931 "mmss_ahb_clk_src",
1932 },
1933 .num_parents = 1,
1934 .ops = &clk_branch2_ops,
1935 },
1936 },
1937 };
1938
1939 static struct clk_branch mdss_hdmi_clk = {
1940 .halt_reg = 0x2338,
1941 .clkr = {
1942 .enable_reg = 0x2338,
1943 .enable_mask = BIT(0),
1944 .hw.init = &(struct clk_init_data){
1945 .name = "mdss_hdmi_clk",
1946 .parent_names = (const char *[]){
1947 "hdmi_clk_src",
1948 },
1949 .num_parents = 1,
1950 .flags = CLK_SET_RATE_PARENT,
1951 .ops = &clk_branch2_ops,
1952 },
1953 },
1954 };
1955
1956 static struct clk_branch mdss_mdp_clk = {
1957 .halt_reg = 0x231c,
1958 .clkr = {
1959 .enable_reg = 0x231c,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "mdss_mdp_clk",
1963 .parent_names = (const char *[]){
1964 "mdp_clk_src",
1965 },
1966 .num_parents = 1,
1967 .flags = CLK_SET_RATE_PARENT,
1968 .ops = &clk_branch2_ops,
1969 },
1970 },
1971 };
1972
1973 static struct clk_branch mdss_mdp_lut_clk = {
1974 .halt_reg = 0x2320,
1975 .clkr = {
1976 .enable_reg = 0x2320,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "mdss_mdp_lut_clk",
1980 .parent_names = (const char *[]){
1981 "mdp_clk_src",
1982 },
1983 .num_parents = 1,
1984 .flags = CLK_SET_RATE_PARENT,
1985 .ops = &clk_branch2_ops,
1986 },
1987 },
1988 };
1989
1990 static struct clk_branch mdss_pclk0_clk = {
1991 .halt_reg = 0x2314,
1992 .clkr = {
1993 .enable_reg = 0x2314,
1994 .enable_mask = BIT(0),
1995 .hw.init = &(struct clk_init_data){
1996 .name = "mdss_pclk0_clk",
1997 .parent_names = (const char *[]){
1998 "pclk0_clk_src",
1999 },
2000 .num_parents = 1,
2001 .flags = CLK_SET_RATE_PARENT,
2002 .ops = &clk_branch2_ops,
2003 },
2004 },
2005 };
2006
2007 static struct clk_branch mdss_pclk1_clk = {
2008 .halt_reg = 0x2318,
2009 .clkr = {
2010 .enable_reg = 0x2318,
2011 .enable_mask = BIT(0),
2012 .hw.init = &(struct clk_init_data){
2013 .name = "mdss_pclk1_clk",
2014 .parent_names = (const char *[]){
2015 "pclk1_clk_src",
2016 },
2017 .num_parents = 1,
2018 .flags = CLK_SET_RATE_PARENT,
2019 .ops = &clk_branch2_ops,
2020 },
2021 },
2022 };
2023
2024 static struct clk_branch mdss_vsync_clk = {
2025 .halt_reg = 0x2328,
2026 .clkr = {
2027 .enable_reg = 0x2328,
2028 .enable_mask = BIT(0),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "mdss_vsync_clk",
2031 .parent_names = (const char *[]){
2032 "vsync_clk_src",
2033 },
2034 .num_parents = 1,
2035 .flags = CLK_SET_RATE_PARENT,
2036 .ops = &clk_branch2_ops,
2037 },
2038 },
2039 };
2040
2041 static struct clk_branch mmss_misc_ahb_clk = {
2042 .halt_reg = 0x502c,
2043 .clkr = {
2044 .enable_reg = 0x502c,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "mmss_misc_ahb_clk",
2048 .parent_names = (const char *[]){
2049 "mmss_ahb_clk_src",
2050 },
2051 .num_parents = 1,
2052 .ops = &clk_branch2_ops,
2053 },
2054 },
2055 };
2056
2057 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2058 .halt_reg = 0x5024,
2059 .clkr = {
2060 .enable_reg = 0x5024,
2061 .enable_mask = BIT(0),
2062 .hw.init = &(struct clk_init_data){
2063 .name = "mmss_mmssnoc_ahb_clk",
2064 .parent_names = (const char *[]){
2065 "mmss_ahb_clk_src",
2066 },
2067 .num_parents = 1,
2068 .ops = &clk_branch2_ops,
2069 .flags = CLK_IGNORE_UNUSED,
2070 },
2071 },
2072 };
2073
2074 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2075 .halt_reg = 0x5028,
2076 .clkr = {
2077 .enable_reg = 0x5028,
2078 .enable_mask = BIT(0),
2079 .hw.init = &(struct clk_init_data){
2080 .name = "mmss_mmssnoc_bto_ahb_clk",
2081 .parent_names = (const char *[]){
2082 "mmss_ahb_clk_src",
2083 },
2084 .num_parents = 1,
2085 .ops = &clk_branch2_ops,
2086 .flags = CLK_IGNORE_UNUSED,
2087 },
2088 },
2089 };
2090
2091 static struct clk_branch mmss_mmssnoc_axi_clk = {
2092 .halt_reg = 0x506c,
2093 .clkr = {
2094 .enable_reg = 0x506c,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "mmss_mmssnoc_axi_clk",
2098 .parent_names = (const char *[]){
2099 "mmss_axi_clk_src",
2100 },
2101 .num_parents = 1,
2102 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2103 .ops = &clk_branch2_ops,
2104 },
2105 },
2106 };
2107
2108 static struct clk_branch mmss_s0_axi_clk = {
2109 .halt_reg = 0x5064,
2110 .clkr = {
2111 .enable_reg = 0x5064,
2112 .enable_mask = BIT(0),
2113 .hw.init = &(struct clk_init_data){
2114 .name = "mmss_s0_axi_clk",
2115 .parent_names = (const char *[]){
2116 "mmss_axi_clk_src",
2117 },
2118 .num_parents = 1,
2119 .ops = &clk_branch2_ops,
2120 .flags = CLK_IGNORE_UNUSED,
2121 },
2122 },
2123 };
2124
2125 static struct clk_branch ocmemcx_ahb_clk = {
2126 .halt_reg = 0x405c,
2127 .clkr = {
2128 .enable_reg = 0x405c,
2129 .enable_mask = BIT(0),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "ocmemcx_ahb_clk",
2132 .parent_names = (const char *[]){
2133 "mmss_ahb_clk_src",
2134 },
2135 .num_parents = 1,
2136 .ops = &clk_branch2_ops,
2137 },
2138 },
2139 };
2140
2141 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2142 .halt_reg = 0x4058,
2143 .clkr = {
2144 .enable_reg = 0x4058,
2145 .enable_mask = BIT(0),
2146 .hw.init = &(struct clk_init_data){
2147 .name = "ocmemcx_ocmemnoc_clk",
2148 .parent_names = (const char *[]){
2149 "ocmemnoc_clk_src",
2150 },
2151 .num_parents = 1,
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2154 },
2155 },
2156 };
2157
2158 static struct clk_branch oxili_ocmemgx_clk = {
2159 .halt_reg = 0x402c,
2160 .clkr = {
2161 .enable_reg = 0x402c,
2162 .enable_mask = BIT(0),
2163 .hw.init = &(struct clk_init_data){
2164 .name = "oxili_ocmemgx_clk",
2165 .parent_names = (const char *[]){
2166 "gfx3d_clk_src",
2167 },
2168 .num_parents = 1,
2169 .flags = CLK_SET_RATE_PARENT,
2170 .ops = &clk_branch2_ops,
2171 },
2172 },
2173 };
2174
2175 static struct clk_branch ocmemnoc_clk = {
2176 .halt_reg = 0x50b4,
2177 .clkr = {
2178 .enable_reg = 0x50b4,
2179 .enable_mask = BIT(0),
2180 .hw.init = &(struct clk_init_data){
2181 .name = "ocmemnoc_clk",
2182 .parent_names = (const char *[]){
2183 "ocmemnoc_clk_src",
2184 },
2185 .num_parents = 1,
2186 .flags = CLK_SET_RATE_PARENT,
2187 .ops = &clk_branch2_ops,
2188 },
2189 },
2190 };
2191
2192 static struct clk_branch oxili_gfx3d_clk = {
2193 .halt_reg = 0x4028,
2194 .clkr = {
2195 .enable_reg = 0x4028,
2196 .enable_mask = BIT(0),
2197 .hw.init = &(struct clk_init_data){
2198 .name = "oxili_gfx3d_clk",
2199 .parent_names = (const char *[]){
2200 "gfx3d_clk_src",
2201 },
2202 .num_parents = 1,
2203 .flags = CLK_SET_RATE_PARENT,
2204 .ops = &clk_branch2_ops,
2205 },
2206 },
2207 };
2208
2209 static struct clk_branch oxilicx_ahb_clk = {
2210 .halt_reg = 0x403c,
2211 .clkr = {
2212 .enable_reg = 0x403c,
2213 .enable_mask = BIT(0),
2214 .hw.init = &(struct clk_init_data){
2215 .name = "oxilicx_ahb_clk",
2216 .parent_names = (const char *[]){
2217 "mmss_ahb_clk_src",
2218 },
2219 .num_parents = 1,
2220 .ops = &clk_branch2_ops,
2221 },
2222 },
2223 };
2224
2225 static struct clk_branch oxilicx_axi_clk = {
2226 .halt_reg = 0x4038,
2227 .clkr = {
2228 .enable_reg = 0x4038,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "oxilicx_axi_clk",
2232 .parent_names = (const char *[]){
2233 "mmss_axi_clk_src",
2234 },
2235 .num_parents = 1,
2236 .ops = &clk_branch2_ops,
2237 },
2238 },
2239 };
2240
2241 static struct clk_branch venus0_ahb_clk = {
2242 .halt_reg = 0x1030,
2243 .clkr = {
2244 .enable_reg = 0x1030,
2245 .enable_mask = BIT(0),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "venus0_ahb_clk",
2248 .parent_names = (const char *[]){
2249 "mmss_ahb_clk_src",
2250 },
2251 .num_parents = 1,
2252 .ops = &clk_branch2_ops,
2253 },
2254 },
2255 };
2256
2257 static struct clk_branch venus0_axi_clk = {
2258 .halt_reg = 0x1034,
2259 .clkr = {
2260 .enable_reg = 0x1034,
2261 .enable_mask = BIT(0),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "venus0_axi_clk",
2264 .parent_names = (const char *[]){
2265 "mmss_axi_clk_src",
2266 },
2267 .num_parents = 1,
2268 .ops = &clk_branch2_ops,
2269 },
2270 },
2271 };
2272
2273 static struct clk_branch venus0_ocmemnoc_clk = {
2274 .halt_reg = 0x1038,
2275 .clkr = {
2276 .enable_reg = 0x1038,
2277 .enable_mask = BIT(0),
2278 .hw.init = &(struct clk_init_data){
2279 .name = "venus0_ocmemnoc_clk",
2280 .parent_names = (const char *[]){
2281 "ocmemnoc_clk_src",
2282 },
2283 .num_parents = 1,
2284 .flags = CLK_SET_RATE_PARENT,
2285 .ops = &clk_branch2_ops,
2286 },
2287 },
2288 };
2289
2290 static struct clk_branch venus0_vcodec0_clk = {
2291 .halt_reg = 0x1028,
2292 .clkr = {
2293 .enable_reg = 0x1028,
2294 .enable_mask = BIT(0),
2295 .hw.init = &(struct clk_init_data){
2296 .name = "venus0_vcodec0_clk",
2297 .parent_names = (const char *[]){
2298 "vcodec0_clk_src",
2299 },
2300 .num_parents = 1,
2301 .flags = CLK_SET_RATE_PARENT,
2302 .ops = &clk_branch2_ops,
2303 },
2304 },
2305 };
2306
2307 static const struct pll_config mmpll1_config = {
2308 .l = 60,
2309 .m = 25,
2310 .n = 32,
2311 .vco_val = 0x0,
2312 .vco_mask = 0x3 << 20,
2313 .pre_div_val = 0x0,
2314 .pre_div_mask = 0x7 << 12,
2315 .post_div_val = 0x0,
2316 .post_div_mask = 0x3 << 8,
2317 .mn_ena_mask = BIT(24),
2318 .main_output_mask = BIT(0),
2319 };
2320
2321 static struct pll_config mmpll3_config = {
2322 .l = 48,
2323 .m = 7,
2324 .n = 16,
2325 .vco_val = 0x0,
2326 .vco_mask = 0x3 << 20,
2327 .pre_div_val = 0x0,
2328 .pre_div_mask = 0x7 << 12,
2329 .post_div_val = 0x0,
2330 .post_div_mask = 0x3 << 8,
2331 .mn_ena_mask = BIT(24),
2332 .main_output_mask = BIT(0),
2333 .aux_output_mask = BIT(1),
2334 };
2335
2336 static struct gdsc venus0_gdsc = {
2337 .gdscr = 0x1024,
2338 .cxcs = (unsigned int []){ 0x1028 },
2339 .cxc_count = 1,
2340 .resets = (unsigned int []){ VENUS0_RESET },
2341 .reset_count = 1,
2342 .pd = {
2343 .name = "venus0",
2344 },
2345 .pwrsts = PWRSTS_ON,
2346 };
2347
2348 static struct gdsc mdss_gdsc = {
2349 .gdscr = 0x2304,
2350 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2351 .cxc_count = 2,
2352 .pd = {
2353 .name = "mdss",
2354 },
2355 .pwrsts = PWRSTS_RET_ON,
2356 };
2357
2358 static struct gdsc camss_jpeg_gdsc = {
2359 .gdscr = 0x35a4,
2360 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2361 .cxc_count = 3,
2362 .pd = {
2363 .name = "camss_jpeg",
2364 },
2365 .pwrsts = PWRSTS_OFF_ON,
2366 };
2367
2368 static struct gdsc camss_vfe_gdsc = {
2369 .gdscr = 0x36a4,
2370 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2371 .cxc_count = 5,
2372 .pd = {
2373 .name = "camss_vfe",
2374 },
2375 .pwrsts = PWRSTS_OFF_ON,
2376 };
2377
2378 static struct gdsc oxili_gdsc = {
2379 .gdscr = 0x4024,
2380 .cxcs = (unsigned int []){ 0x4028 },
2381 .cxc_count = 1,
2382 .pd = {
2383 .name = "oxili",
2384 },
2385 .pwrsts = PWRSTS_OFF_ON,
2386 };
2387
2388 static struct gdsc oxilicx_gdsc = {
2389 .gdscr = 0x4034,
2390 .pd = {
2391 .name = "oxilicx",
2392 },
2393 .parent = &oxili_gdsc.pd,
2394 .pwrsts = PWRSTS_OFF_ON,
2395 };
2396
2397 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2398 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2399 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2400 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2401 [MMPLL0] = &mmpll0.clkr,
2402 [MMPLL0_VOTE] = &mmpll0_vote,
2403 [MMPLL1] = &mmpll1.clkr,
2404 [MMPLL1_VOTE] = &mmpll1_vote,
2405 [MMPLL2] = &mmpll2.clkr,
2406 [MMPLL3] = &mmpll3.clkr,
2407 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2408 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2409 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2410 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2411 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2412 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2413 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2414 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2415 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2416 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2417 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2418 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2419 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2420 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2421 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2422 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2423 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2424 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2425 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2426 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2427 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2428 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2429 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2430 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2431 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2432 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2433 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2434 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2435 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2436 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2437 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2438 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2439 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2440 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2441 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2442 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2443 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2444 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2445 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2446 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2447 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2448 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2449 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2450 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2451 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2452 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2453 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2454 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2455 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2456 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2457 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2458 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2459 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2460 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2461 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2462 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2463 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2464 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2465 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2466 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2467 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2468 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2469 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2470 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2471 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2472 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2473 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2474 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2475 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2476 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2477 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2478 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2479 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2480 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2481 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2482 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2483 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2484 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2485 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2486 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2487 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2488 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2489 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2490 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2491 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2492 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2493 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2494 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2495 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2496 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2497 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2498 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2499 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2500 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2501 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2502 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2503 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2504 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2505 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2506 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2507 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2508 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2509 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2510 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2511 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2512 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2513 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2514 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2515 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2516 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2517 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2518 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2519 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2520 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2521 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2522 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2523 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2524 };
2525
2526 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2527 [SPDM_RESET] = { 0x0200 },
2528 [SPDM_RM_RESET] = { 0x0300 },
2529 [VENUS0_RESET] = { 0x1020 },
2530 [MDSS_RESET] = { 0x2300 },
2531 [CAMSS_PHY0_RESET] = { 0x3020 },
2532 [CAMSS_PHY1_RESET] = { 0x3050 },
2533 [CAMSS_PHY2_RESET] = { 0x3080 },
2534 [CAMSS_CSI0_RESET] = { 0x30b0 },
2535 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2536 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2537 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2538 [CAMSS_CSI1_RESET] = { 0x3120 },
2539 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2540 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2541 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2542 [CAMSS_CSI2_RESET] = { 0x3180 },
2543 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2544 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2545 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2546 [CAMSS_CSI3_RESET] = { 0x31e0 },
2547 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2548 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2549 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2550 [CAMSS_ISPIF_RESET] = { 0x3220 },
2551 [CAMSS_CCI_RESET] = { 0x3340 },
2552 [CAMSS_MCLK0_RESET] = { 0x3380 },
2553 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2554 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2555 [CAMSS_MCLK3_RESET] = { 0x3410 },
2556 [CAMSS_GP0_RESET] = { 0x3440 },
2557 [CAMSS_GP1_RESET] = { 0x3470 },
2558 [CAMSS_TOP_RESET] = { 0x3480 },
2559 [CAMSS_MICRO_RESET] = { 0x3490 },
2560 [CAMSS_JPEG_RESET] = { 0x35a0 },
2561 [CAMSS_VFE_RESET] = { 0x36a0 },
2562 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2563 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2564 [OXILI_RESET] = { 0x4020 },
2565 [OXILICX_RESET] = { 0x4030 },
2566 [OCMEMCX_RESET] = { 0x4050 },
2567 [MMSS_RBCRP_RESET] = { 0x4080 },
2568 [MMSSNOCAHB_RESET] = { 0x5020 },
2569 [MMSSNOCAXI_RESET] = { 0x5060 },
2570 [OCMEMNOC_RESET] = { 0x50b0 },
2571 };
2572
2573 static struct gdsc *mmcc_msm8974_gdscs[] = {
2574 [VENUS0_GDSC] = &venus0_gdsc,
2575 [MDSS_GDSC] = &mdss_gdsc,
2576 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2577 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2578 [OXILI_GDSC] = &oxili_gdsc,
2579 [OXILICX_GDSC] = &oxilicx_gdsc,
2580 };
2581
2582 static const struct regmap_config mmcc_msm8974_regmap_config = {
2583 .reg_bits = 32,
2584 .reg_stride = 4,
2585 .val_bits = 32,
2586 .max_register = 0x5104,
2587 .fast_io = true,
2588 };
2589
2590 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2591 .config = &mmcc_msm8974_regmap_config,
2592 .clks = mmcc_msm8974_clocks,
2593 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2594 .resets = mmcc_msm8974_resets,
2595 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2596 .gdscs = mmcc_msm8974_gdscs,
2597 .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2598 };
2599
2600 static const struct of_device_id mmcc_msm8974_match_table[] = {
2601 { .compatible = "qcom,mmcc-msm8974" },
2602 { }
2603 };
2604 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2605
2606 static int mmcc_msm8974_probe(struct platform_device *pdev)
2607 {
2608 struct regmap *regmap;
2609
2610 regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2611 if (IS_ERR(regmap))
2612 return PTR_ERR(regmap);
2613
2614 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2615 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2616
2617 return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2618 }
2619
2620 static struct platform_driver mmcc_msm8974_driver = {
2621 .probe = mmcc_msm8974_probe,
2622 .driver = {
2623 .name = "mmcc-msm8974",
2624 .of_match_table = mmcc_msm8974_match_table,
2625 },
2626 };
2627 module_platform_driver(mmcc_msm8974_driver);
2628
2629 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2630 MODULE_LICENSE("GPL v2");
2631 MODULE_ALIAS("platform:mmcc-msm8974");