root/drivers/clk/qcom/lpasscc-sdm845.c

DEFINITIONS

1. lpass_cc_sdm845_probe
2. lpass_cc_sdm845_init
3. lpass_cc_sdm845_exit

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5 
   6 #include <linux/platform_device.h>
   7 #include <linux/module.h>
   8 #include <linux/of_address.h>
   9 #include <linux/regmap.h>
  10 
  11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  12 
  13 #include "clk-regmap.h"
  14 #include "clk-branch.h"
  15 #include "common.h"
  16 
  17 static struct clk_branch lpass_q6ss_ahbm_aon_clk = {
  18         .halt_reg = 0x12000,
  19         .halt_check = BRANCH_VOTED,
  20         .clkr = {
  21                 .enable_reg = 0x12000,
  22                 .enable_mask = BIT(0),
  23                 .hw.init = &(struct clk_init_data){
  24                         .name = "lpass_q6ss_ahbm_aon_clk",
  25                         .ops = &clk_branch2_ops,
  26                 },
  27         },
  28 };
  29 
  30 static struct clk_branch lpass_q6ss_ahbs_aon_clk = {
  31         .halt_reg = 0x1f000,
  32         .halt_check = BRANCH_VOTED,
  33         .clkr = {
  34                 .enable_reg = 0x1f000,
  35                 .enable_mask = BIT(0),
  36                 .hw.init = &(struct clk_init_data){
  37                         .name = "lpass_q6ss_ahbs_aon_clk",
  38                         .ops = &clk_branch2_ops,
  39                 },
  40         },
  41 };
  42 
  43 static struct clk_branch lpass_qdsp6ss_core_clk = {
  44         .halt_reg = 0x20,
  45         /* CLK_OFF would not toggle until LPASS is out of reset */
  46         .halt_check = BRANCH_HALT_SKIP,
  47         .clkr = {
  48                 .enable_reg = 0x20,
  49                 .enable_mask = BIT(0),
  50                 .hw.init = &(struct clk_init_data){
  51                         .name = "lpass_qdsp6ss_core_clk",
  52                         .ops = &clk_branch2_ops,
  53                 },
  54         },
  55 };
  56 
  57 static struct clk_branch lpass_qdsp6ss_xo_clk = {
  58         .halt_reg = 0x38,
  59         /* CLK_OFF would not toggle until LPASS is out of reset */
  60         .halt_check = BRANCH_HALT_SKIP,
  61         .clkr = {
  62                 .enable_reg = 0x38,
  63                 .enable_mask = BIT(0),
  64                 .hw.init = &(struct clk_init_data){
  65                         .name = "lpass_qdsp6ss_xo_clk",
  66                         .ops = &clk_branch2_ops,
  67                 },
  68         },
  69 };
  70 
  71 static struct clk_branch lpass_qdsp6ss_sleep_clk = {
  72         .halt_reg = 0x3c,
  73         /* CLK_OFF would not toggle until LPASS is out of reset */
  74         .halt_check = BRANCH_HALT_SKIP,
  75         .clkr = {
  76                 .enable_reg = 0x3c,
  77                 .enable_mask = BIT(0),
  78                 .hw.init = &(struct clk_init_data){
  79                         .name = "lpass_qdsp6ss_sleep_clk",
  80                         .ops = &clk_branch2_ops,
  81                 },
  82         },
  83 };
  84 
  85 static struct regmap_config lpass_regmap_config = {
  86         .reg_bits       = 32,
  87         .reg_stride     = 4,
  88         .val_bits       = 32,
  89         .fast_io        = true,
  90 };
  91 
  92 static struct clk_regmap *lpass_cc_sdm845_clocks[] = {
  93         [LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr,
  94         [LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr,
  95 };
  96 
  97 static const struct qcom_cc_desc lpass_cc_sdm845_desc = {
  98         .config = &lpass_regmap_config,
  99         .clks = lpass_cc_sdm845_clocks,
 100         .num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks),
 101 };
 102 
 103 static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = {
 104         [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
 105         [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
 106         [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
 107 };
 108 
 109 static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
 110         .config = &lpass_regmap_config,
 111         .clks = lpass_qdsp6ss_sdm845_clocks,
 112         .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
 113 };
 114 
 115 static int lpass_cc_sdm845_probe(struct platform_device *pdev)
 116 {
 117         const struct qcom_cc_desc *desc;
 118         int ret;
 119 
 120         lpass_regmap_config.name = "cc";
 121         desc = &lpass_cc_sdm845_desc;
 122 
 123         ret = qcom_cc_probe_by_index(pdev, 0, desc);
 124         if (ret)
 125                 return ret;
 126 
 127         lpass_regmap_config.name = "qdsp6ss";
 128         desc = &lpass_qdsp6ss_sdm845_desc;
 129 
 130         return qcom_cc_probe_by_index(pdev, 1, desc);
 131 }
 132 
 133 static const struct of_device_id lpass_cc_sdm845_match_table[] = {
 134         { .compatible = "qcom,sdm845-lpasscc" },
 135         { }
 136 };
 137 MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table);
 138 
 139 static struct platform_driver lpass_cc_sdm845_driver = {
 140         .probe          = lpass_cc_sdm845_probe,
 141         .driver         = {
 142                 .name   = "sdm845-lpasscc",
 143                 .of_match_table = lpass_cc_sdm845_match_table,
 144         },
 145 };
 146 
 147 static int __init lpass_cc_sdm845_init(void)
 148 {
 149         return platform_driver_register(&lpass_cc_sdm845_driver);
 150 }
 151 subsys_initcall(lpass_cc_sdm845_init);
 152 
 153 static void __exit lpass_cc_sdm845_exit(void)
 154 {
 155         platform_driver_unregister(&lpass_cc_sdm845_driver);
 156 }
 157 module_exit(lpass_cc_sdm845_exit);
 158 
 159 MODULE_DESCRIPTION("QTI LPASS_CC SDM845 Driver");
 160 MODULE_LICENSE("GPL v2");