This source file includes following definitions.
- gcc_msm8960_probe
- gcc_msm8960_remove
- gcc_msm8960_init
- gcc_msm8960_exit
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5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
19
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "clk-hfpll.h"
26 #include "reset.h"
27
28 static struct clk_pll pll3 = {
29 .l_reg = 0x3164,
30 .m_reg = 0x3168,
31 .n_reg = 0x316c,
32 .config_reg = 0x3174,
33 .mode_reg = 0x3160,
34 .status_reg = 0x3178,
35 .status_bit = 16,
36 .clkr.hw.init = &(struct clk_init_data){
37 .name = "pll3",
38 .parent_names = (const char *[]){ "pxo" },
39 .num_parents = 1,
40 .ops = &clk_pll_ops,
41 },
42 };
43
44 static struct clk_regmap pll4_vote = {
45 .enable_reg = 0x34c0,
46 .enable_mask = BIT(4),
47 .hw.init = &(struct clk_init_data){
48 .name = "pll4_vote",
49 .parent_names = (const char *[]){ "pll4" },
50 .num_parents = 1,
51 .ops = &clk_pll_vote_ops,
52 },
53 };
54
55 static struct clk_pll pll8 = {
56 .l_reg = 0x3144,
57 .m_reg = 0x3148,
58 .n_reg = 0x314c,
59 .config_reg = 0x3154,
60 .mode_reg = 0x3140,
61 .status_reg = 0x3158,
62 .status_bit = 16,
63 .clkr.hw.init = &(struct clk_init_data){
64 .name = "pll8",
65 .parent_names = (const char *[]){ "pxo" },
66 .num_parents = 1,
67 .ops = &clk_pll_ops,
68 },
69 };
70
71 static struct clk_regmap pll8_vote = {
72 .enable_reg = 0x34c0,
73 .enable_mask = BIT(8),
74 .hw.init = &(struct clk_init_data){
75 .name = "pll8_vote",
76 .parent_names = (const char *[]){ "pll8" },
77 .num_parents = 1,
78 .ops = &clk_pll_vote_ops,
79 },
80 };
81
82 static struct hfpll_data hfpll0_data = {
83 .mode_reg = 0x3200,
84 .l_reg = 0x3208,
85 .m_reg = 0x320c,
86 .n_reg = 0x3210,
87 .config_reg = 0x3204,
88 .status_reg = 0x321c,
89 .config_val = 0x7845c665,
90 .droop_reg = 0x3214,
91 .droop_val = 0x0108c000,
92 .min_rate = 600000000UL,
93 .max_rate = 1800000000UL,
94 };
95
96 static struct clk_hfpll hfpll0 = {
97 .d = &hfpll0_data,
98 .clkr.hw.init = &(struct clk_init_data){
99 .parent_names = (const char *[]){ "pxo" },
100 .num_parents = 1,
101 .name = "hfpll0",
102 .ops = &clk_ops_hfpll,
103 .flags = CLK_IGNORE_UNUSED,
104 },
105 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
106 };
107
108 static struct hfpll_data hfpll1_8064_data = {
109 .mode_reg = 0x3240,
110 .l_reg = 0x3248,
111 .m_reg = 0x324c,
112 .n_reg = 0x3250,
113 .config_reg = 0x3244,
114 .status_reg = 0x325c,
115 .config_val = 0x7845c665,
116 .droop_reg = 0x3254,
117 .droop_val = 0x0108c000,
118 .min_rate = 600000000UL,
119 .max_rate = 1800000000UL,
120 };
121
122 static struct hfpll_data hfpll1_data = {
123 .mode_reg = 0x3300,
124 .l_reg = 0x3308,
125 .m_reg = 0x330c,
126 .n_reg = 0x3310,
127 .config_reg = 0x3304,
128 .status_reg = 0x331c,
129 .config_val = 0x7845c665,
130 .droop_reg = 0x3314,
131 .droop_val = 0x0108c000,
132 .min_rate = 600000000UL,
133 .max_rate = 1800000000UL,
134 };
135
136 static struct clk_hfpll hfpll1 = {
137 .d = &hfpll1_data,
138 .clkr.hw.init = &(struct clk_init_data){
139 .parent_names = (const char *[]){ "pxo" },
140 .num_parents = 1,
141 .name = "hfpll1",
142 .ops = &clk_ops_hfpll,
143 .flags = CLK_IGNORE_UNUSED,
144 },
145 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
146 };
147
148 static struct hfpll_data hfpll2_data = {
149 .mode_reg = 0x3280,
150 .l_reg = 0x3288,
151 .m_reg = 0x328c,
152 .n_reg = 0x3290,
153 .config_reg = 0x3284,
154 .status_reg = 0x329c,
155 .config_val = 0x7845c665,
156 .droop_reg = 0x3294,
157 .droop_val = 0x0108c000,
158 .min_rate = 600000000UL,
159 .max_rate = 1800000000UL,
160 };
161
162 static struct clk_hfpll hfpll2 = {
163 .d = &hfpll2_data,
164 .clkr.hw.init = &(struct clk_init_data){
165 .parent_names = (const char *[]){ "pxo" },
166 .num_parents = 1,
167 .name = "hfpll2",
168 .ops = &clk_ops_hfpll,
169 .flags = CLK_IGNORE_UNUSED,
170 },
171 .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
172 };
173
174 static struct hfpll_data hfpll3_data = {
175 .mode_reg = 0x32c0,
176 .l_reg = 0x32c8,
177 .m_reg = 0x32cc,
178 .n_reg = 0x32d0,
179 .config_reg = 0x32c4,
180 .status_reg = 0x32dc,
181 .config_val = 0x7845c665,
182 .droop_reg = 0x32d4,
183 .droop_val = 0x0108c000,
184 .min_rate = 600000000UL,
185 .max_rate = 1800000000UL,
186 };
187
188 static struct clk_hfpll hfpll3 = {
189 .d = &hfpll3_data,
190 .clkr.hw.init = &(struct clk_init_data){
191 .parent_names = (const char *[]){ "pxo" },
192 .num_parents = 1,
193 .name = "hfpll3",
194 .ops = &clk_ops_hfpll,
195 .flags = CLK_IGNORE_UNUSED,
196 },
197 .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
198 };
199
200 static struct hfpll_data hfpll_l2_8064_data = {
201 .mode_reg = 0x3300,
202 .l_reg = 0x3308,
203 .m_reg = 0x330c,
204 .n_reg = 0x3310,
205 .config_reg = 0x3304,
206 .status_reg = 0x331c,
207 .config_val = 0x7845c665,
208 .droop_reg = 0x3314,
209 .droop_val = 0x0108c000,
210 .min_rate = 600000000UL,
211 .max_rate = 1800000000UL,
212 };
213
214 static struct hfpll_data hfpll_l2_data = {
215 .mode_reg = 0x3400,
216 .l_reg = 0x3408,
217 .m_reg = 0x340c,
218 .n_reg = 0x3410,
219 .config_reg = 0x3404,
220 .status_reg = 0x341c,
221 .config_val = 0x7845c665,
222 .droop_reg = 0x3414,
223 .droop_val = 0x0108c000,
224 .min_rate = 600000000UL,
225 .max_rate = 1800000000UL,
226 };
227
228 static struct clk_hfpll hfpll_l2 = {
229 .d = &hfpll_l2_data,
230 .clkr.hw.init = &(struct clk_init_data){
231 .parent_names = (const char *[]){ "pxo" },
232 .num_parents = 1,
233 .name = "hfpll_l2",
234 .ops = &clk_ops_hfpll,
235 .flags = CLK_IGNORE_UNUSED,
236 },
237 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
238 };
239
240 static struct clk_pll pll14 = {
241 .l_reg = 0x31c4,
242 .m_reg = 0x31c8,
243 .n_reg = 0x31cc,
244 .config_reg = 0x31d4,
245 .mode_reg = 0x31c0,
246 .status_reg = 0x31d8,
247 .status_bit = 16,
248 .clkr.hw.init = &(struct clk_init_data){
249 .name = "pll14",
250 .parent_names = (const char *[]){ "pxo" },
251 .num_parents = 1,
252 .ops = &clk_pll_ops,
253 },
254 };
255
256 static struct clk_regmap pll14_vote = {
257 .enable_reg = 0x34c0,
258 .enable_mask = BIT(14),
259 .hw.init = &(struct clk_init_data){
260 .name = "pll14_vote",
261 .parent_names = (const char *[]){ "pll14" },
262 .num_parents = 1,
263 .ops = &clk_pll_vote_ops,
264 },
265 };
266
267 enum {
268 P_PXO,
269 P_PLL8,
270 P_PLL3,
271 P_CXO,
272 };
273
274 static const struct parent_map gcc_pxo_pll8_map[] = {
275 { P_PXO, 0 },
276 { P_PLL8, 3 }
277 };
278
279 static const char * const gcc_pxo_pll8[] = {
280 "pxo",
281 "pll8_vote",
282 };
283
284 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
285 { P_PXO, 0 },
286 { P_PLL8, 3 },
287 { P_CXO, 5 }
288 };
289
290 static const char * const gcc_pxo_pll8_cxo[] = {
291 "pxo",
292 "pll8_vote",
293 "cxo",
294 };
295
296 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
297 { P_PXO, 0 },
298 { P_PLL8, 3 },
299 { P_PLL3, 6 }
300 };
301
302 static const char * const gcc_pxo_pll8_pll3[] = {
303 "pxo",
304 "pll8_vote",
305 "pll3",
306 };
307
308 static struct freq_tbl clk_tbl_gsbi_uart[] = {
309 { 1843200, P_PLL8, 2, 6, 625 },
310 { 3686400, P_PLL8, 2, 12, 625 },
311 { 7372800, P_PLL8, 2, 24, 625 },
312 { 14745600, P_PLL8, 2, 48, 625 },
313 { 16000000, P_PLL8, 4, 1, 6 },
314 { 24000000, P_PLL8, 4, 1, 4 },
315 { 32000000, P_PLL8, 4, 1, 3 },
316 { 40000000, P_PLL8, 1, 5, 48 },
317 { 46400000, P_PLL8, 1, 29, 240 },
318 { 48000000, P_PLL8, 4, 1, 2 },
319 { 51200000, P_PLL8, 1, 2, 15 },
320 { 56000000, P_PLL8, 1, 7, 48 },
321 { 58982400, P_PLL8, 1, 96, 625 },
322 { 64000000, P_PLL8, 2, 1, 3 },
323 { }
324 };
325
326 static struct clk_rcg gsbi1_uart_src = {
327 .ns_reg = 0x29d4,
328 .md_reg = 0x29d0,
329 .mn = {
330 .mnctr_en_bit = 8,
331 .mnctr_reset_bit = 7,
332 .mnctr_mode_shift = 5,
333 .n_val_shift = 16,
334 .m_val_shift = 16,
335 .width = 16,
336 },
337 .p = {
338 .pre_div_shift = 3,
339 .pre_div_width = 2,
340 },
341 .s = {
342 .src_sel_shift = 0,
343 .parent_map = gcc_pxo_pll8_map,
344 },
345 .freq_tbl = clk_tbl_gsbi_uart,
346 .clkr = {
347 .enable_reg = 0x29d4,
348 .enable_mask = BIT(11),
349 .hw.init = &(struct clk_init_data){
350 .name = "gsbi1_uart_src",
351 .parent_names = gcc_pxo_pll8,
352 .num_parents = 2,
353 .ops = &clk_rcg_ops,
354 .flags = CLK_SET_PARENT_GATE,
355 },
356 },
357 };
358
359 static struct clk_branch gsbi1_uart_clk = {
360 .halt_reg = 0x2fcc,
361 .halt_bit = 10,
362 .clkr = {
363 .enable_reg = 0x29d4,
364 .enable_mask = BIT(9),
365 .hw.init = &(struct clk_init_data){
366 .name = "gsbi1_uart_clk",
367 .parent_names = (const char *[]){
368 "gsbi1_uart_src",
369 },
370 .num_parents = 1,
371 .ops = &clk_branch_ops,
372 .flags = CLK_SET_RATE_PARENT,
373 },
374 },
375 };
376
377 static struct clk_rcg gsbi2_uart_src = {
378 .ns_reg = 0x29f4,
379 .md_reg = 0x29f0,
380 .mn = {
381 .mnctr_en_bit = 8,
382 .mnctr_reset_bit = 7,
383 .mnctr_mode_shift = 5,
384 .n_val_shift = 16,
385 .m_val_shift = 16,
386 .width = 16,
387 },
388 .p = {
389 .pre_div_shift = 3,
390 .pre_div_width = 2,
391 },
392 .s = {
393 .src_sel_shift = 0,
394 .parent_map = gcc_pxo_pll8_map,
395 },
396 .freq_tbl = clk_tbl_gsbi_uart,
397 .clkr = {
398 .enable_reg = 0x29f4,
399 .enable_mask = BIT(11),
400 .hw.init = &(struct clk_init_data){
401 .name = "gsbi2_uart_src",
402 .parent_names = gcc_pxo_pll8,
403 .num_parents = 2,
404 .ops = &clk_rcg_ops,
405 .flags = CLK_SET_PARENT_GATE,
406 },
407 },
408 };
409
410 static struct clk_branch gsbi2_uart_clk = {
411 .halt_reg = 0x2fcc,
412 .halt_bit = 6,
413 .clkr = {
414 .enable_reg = 0x29f4,
415 .enable_mask = BIT(9),
416 .hw.init = &(struct clk_init_data){
417 .name = "gsbi2_uart_clk",
418 .parent_names = (const char *[]){
419 "gsbi2_uart_src",
420 },
421 .num_parents = 1,
422 .ops = &clk_branch_ops,
423 .flags = CLK_SET_RATE_PARENT,
424 },
425 },
426 };
427
428 static struct clk_rcg gsbi3_uart_src = {
429 .ns_reg = 0x2a14,
430 .md_reg = 0x2a10,
431 .mn = {
432 .mnctr_en_bit = 8,
433 .mnctr_reset_bit = 7,
434 .mnctr_mode_shift = 5,
435 .n_val_shift = 16,
436 .m_val_shift = 16,
437 .width = 16,
438 },
439 .p = {
440 .pre_div_shift = 3,
441 .pre_div_width = 2,
442 },
443 .s = {
444 .src_sel_shift = 0,
445 .parent_map = gcc_pxo_pll8_map,
446 },
447 .freq_tbl = clk_tbl_gsbi_uart,
448 .clkr = {
449 .enable_reg = 0x2a14,
450 .enable_mask = BIT(11),
451 .hw.init = &(struct clk_init_data){
452 .name = "gsbi3_uart_src",
453 .parent_names = gcc_pxo_pll8,
454 .num_parents = 2,
455 .ops = &clk_rcg_ops,
456 .flags = CLK_SET_PARENT_GATE,
457 },
458 },
459 };
460
461 static struct clk_branch gsbi3_uart_clk = {
462 .halt_reg = 0x2fcc,
463 .halt_bit = 2,
464 .clkr = {
465 .enable_reg = 0x2a14,
466 .enable_mask = BIT(9),
467 .hw.init = &(struct clk_init_data){
468 .name = "gsbi3_uart_clk",
469 .parent_names = (const char *[]){
470 "gsbi3_uart_src",
471 },
472 .num_parents = 1,
473 .ops = &clk_branch_ops,
474 .flags = CLK_SET_RATE_PARENT,
475 },
476 },
477 };
478
479 static struct clk_rcg gsbi4_uart_src = {
480 .ns_reg = 0x2a34,
481 .md_reg = 0x2a30,
482 .mn = {
483 .mnctr_en_bit = 8,
484 .mnctr_reset_bit = 7,
485 .mnctr_mode_shift = 5,
486 .n_val_shift = 16,
487 .m_val_shift = 16,
488 .width = 16,
489 },
490 .p = {
491 .pre_div_shift = 3,
492 .pre_div_width = 2,
493 },
494 .s = {
495 .src_sel_shift = 0,
496 .parent_map = gcc_pxo_pll8_map,
497 },
498 .freq_tbl = clk_tbl_gsbi_uart,
499 .clkr = {
500 .enable_reg = 0x2a34,
501 .enable_mask = BIT(11),
502 .hw.init = &(struct clk_init_data){
503 .name = "gsbi4_uart_src",
504 .parent_names = gcc_pxo_pll8,
505 .num_parents = 2,
506 .ops = &clk_rcg_ops,
507 .flags = CLK_SET_PARENT_GATE,
508 },
509 },
510 };
511
512 static struct clk_branch gsbi4_uart_clk = {
513 .halt_reg = 0x2fd0,
514 .halt_bit = 26,
515 .clkr = {
516 .enable_reg = 0x2a34,
517 .enable_mask = BIT(9),
518 .hw.init = &(struct clk_init_data){
519 .name = "gsbi4_uart_clk",
520 .parent_names = (const char *[]){
521 "gsbi4_uart_src",
522 },
523 .num_parents = 1,
524 .ops = &clk_branch_ops,
525 .flags = CLK_SET_RATE_PARENT,
526 },
527 },
528 };
529
530 static struct clk_rcg gsbi5_uart_src = {
531 .ns_reg = 0x2a54,
532 .md_reg = 0x2a50,
533 .mn = {
534 .mnctr_en_bit = 8,
535 .mnctr_reset_bit = 7,
536 .mnctr_mode_shift = 5,
537 .n_val_shift = 16,
538 .m_val_shift = 16,
539 .width = 16,
540 },
541 .p = {
542 .pre_div_shift = 3,
543 .pre_div_width = 2,
544 },
545 .s = {
546 .src_sel_shift = 0,
547 .parent_map = gcc_pxo_pll8_map,
548 },
549 .freq_tbl = clk_tbl_gsbi_uart,
550 .clkr = {
551 .enable_reg = 0x2a54,
552 .enable_mask = BIT(11),
553 .hw.init = &(struct clk_init_data){
554 .name = "gsbi5_uart_src",
555 .parent_names = gcc_pxo_pll8,
556 .num_parents = 2,
557 .ops = &clk_rcg_ops,
558 .flags = CLK_SET_PARENT_GATE,
559 },
560 },
561 };
562
563 static struct clk_branch gsbi5_uart_clk = {
564 .halt_reg = 0x2fd0,
565 .halt_bit = 22,
566 .clkr = {
567 .enable_reg = 0x2a54,
568 .enable_mask = BIT(9),
569 .hw.init = &(struct clk_init_data){
570 .name = "gsbi5_uart_clk",
571 .parent_names = (const char *[]){
572 "gsbi5_uart_src",
573 },
574 .num_parents = 1,
575 .ops = &clk_branch_ops,
576 .flags = CLK_SET_RATE_PARENT,
577 },
578 },
579 };
580
581 static struct clk_rcg gsbi6_uart_src = {
582 .ns_reg = 0x2a74,
583 .md_reg = 0x2a70,
584 .mn = {
585 .mnctr_en_bit = 8,
586 .mnctr_reset_bit = 7,
587 .mnctr_mode_shift = 5,
588 .n_val_shift = 16,
589 .m_val_shift = 16,
590 .width = 16,
591 },
592 .p = {
593 .pre_div_shift = 3,
594 .pre_div_width = 2,
595 },
596 .s = {
597 .src_sel_shift = 0,
598 .parent_map = gcc_pxo_pll8_map,
599 },
600 .freq_tbl = clk_tbl_gsbi_uart,
601 .clkr = {
602 .enable_reg = 0x2a74,
603 .enable_mask = BIT(11),
604 .hw.init = &(struct clk_init_data){
605 .name = "gsbi6_uart_src",
606 .parent_names = gcc_pxo_pll8,
607 .num_parents = 2,
608 .ops = &clk_rcg_ops,
609 .flags = CLK_SET_PARENT_GATE,
610 },
611 },
612 };
613
614 static struct clk_branch gsbi6_uart_clk = {
615 .halt_reg = 0x2fd0,
616 .halt_bit = 18,
617 .clkr = {
618 .enable_reg = 0x2a74,
619 .enable_mask = BIT(9),
620 .hw.init = &(struct clk_init_data){
621 .name = "gsbi6_uart_clk",
622 .parent_names = (const char *[]){
623 "gsbi6_uart_src",
624 },
625 .num_parents = 1,
626 .ops = &clk_branch_ops,
627 .flags = CLK_SET_RATE_PARENT,
628 },
629 },
630 };
631
632 static struct clk_rcg gsbi7_uart_src = {
633 .ns_reg = 0x2a94,
634 .md_reg = 0x2a90,
635 .mn = {
636 .mnctr_en_bit = 8,
637 .mnctr_reset_bit = 7,
638 .mnctr_mode_shift = 5,
639 .n_val_shift = 16,
640 .m_val_shift = 16,
641 .width = 16,
642 },
643 .p = {
644 .pre_div_shift = 3,
645 .pre_div_width = 2,
646 },
647 .s = {
648 .src_sel_shift = 0,
649 .parent_map = gcc_pxo_pll8_map,
650 },
651 .freq_tbl = clk_tbl_gsbi_uart,
652 .clkr = {
653 .enable_reg = 0x2a94,
654 .enable_mask = BIT(11),
655 .hw.init = &(struct clk_init_data){
656 .name = "gsbi7_uart_src",
657 .parent_names = gcc_pxo_pll8,
658 .num_parents = 2,
659 .ops = &clk_rcg_ops,
660 .flags = CLK_SET_PARENT_GATE,
661 },
662 },
663 };
664
665 static struct clk_branch gsbi7_uart_clk = {
666 .halt_reg = 0x2fd0,
667 .halt_bit = 14,
668 .clkr = {
669 .enable_reg = 0x2a94,
670 .enable_mask = BIT(9),
671 .hw.init = &(struct clk_init_data){
672 .name = "gsbi7_uart_clk",
673 .parent_names = (const char *[]){
674 "gsbi7_uart_src",
675 },
676 .num_parents = 1,
677 .ops = &clk_branch_ops,
678 .flags = CLK_SET_RATE_PARENT,
679 },
680 },
681 };
682
683 static struct clk_rcg gsbi8_uart_src = {
684 .ns_reg = 0x2ab4,
685 .md_reg = 0x2ab0,
686 .mn = {
687 .mnctr_en_bit = 8,
688 .mnctr_reset_bit = 7,
689 .mnctr_mode_shift = 5,
690 .n_val_shift = 16,
691 .m_val_shift = 16,
692 .width = 16,
693 },
694 .p = {
695 .pre_div_shift = 3,
696 .pre_div_width = 2,
697 },
698 .s = {
699 .src_sel_shift = 0,
700 .parent_map = gcc_pxo_pll8_map,
701 },
702 .freq_tbl = clk_tbl_gsbi_uart,
703 .clkr = {
704 .enable_reg = 0x2ab4,
705 .enable_mask = BIT(11),
706 .hw.init = &(struct clk_init_data){
707 .name = "gsbi8_uart_src",
708 .parent_names = gcc_pxo_pll8,
709 .num_parents = 2,
710 .ops = &clk_rcg_ops,
711 .flags = CLK_SET_PARENT_GATE,
712 },
713 },
714 };
715
716 static struct clk_branch gsbi8_uart_clk = {
717 .halt_reg = 0x2fd0,
718 .halt_bit = 10,
719 .clkr = {
720 .enable_reg = 0x2ab4,
721 .enable_mask = BIT(9),
722 .hw.init = &(struct clk_init_data){
723 .name = "gsbi8_uart_clk",
724 .parent_names = (const char *[]){ "gsbi8_uart_src" },
725 .num_parents = 1,
726 .ops = &clk_branch_ops,
727 .flags = CLK_SET_RATE_PARENT,
728 },
729 },
730 };
731
732 static struct clk_rcg gsbi9_uart_src = {
733 .ns_reg = 0x2ad4,
734 .md_reg = 0x2ad0,
735 .mn = {
736 .mnctr_en_bit = 8,
737 .mnctr_reset_bit = 7,
738 .mnctr_mode_shift = 5,
739 .n_val_shift = 16,
740 .m_val_shift = 16,
741 .width = 16,
742 },
743 .p = {
744 .pre_div_shift = 3,
745 .pre_div_width = 2,
746 },
747 .s = {
748 .src_sel_shift = 0,
749 .parent_map = gcc_pxo_pll8_map,
750 },
751 .freq_tbl = clk_tbl_gsbi_uart,
752 .clkr = {
753 .enable_reg = 0x2ad4,
754 .enable_mask = BIT(11),
755 .hw.init = &(struct clk_init_data){
756 .name = "gsbi9_uart_src",
757 .parent_names = gcc_pxo_pll8,
758 .num_parents = 2,
759 .ops = &clk_rcg_ops,
760 .flags = CLK_SET_PARENT_GATE,
761 },
762 },
763 };
764
765 static struct clk_branch gsbi9_uart_clk = {
766 .halt_reg = 0x2fd0,
767 .halt_bit = 6,
768 .clkr = {
769 .enable_reg = 0x2ad4,
770 .enable_mask = BIT(9),
771 .hw.init = &(struct clk_init_data){
772 .name = "gsbi9_uart_clk",
773 .parent_names = (const char *[]){ "gsbi9_uart_src" },
774 .num_parents = 1,
775 .ops = &clk_branch_ops,
776 .flags = CLK_SET_RATE_PARENT,
777 },
778 },
779 };
780
781 static struct clk_rcg gsbi10_uart_src = {
782 .ns_reg = 0x2af4,
783 .md_reg = 0x2af0,
784 .mn = {
785 .mnctr_en_bit = 8,
786 .mnctr_reset_bit = 7,
787 .mnctr_mode_shift = 5,
788 .n_val_shift = 16,
789 .m_val_shift = 16,
790 .width = 16,
791 },
792 .p = {
793 .pre_div_shift = 3,
794 .pre_div_width = 2,
795 },
796 .s = {
797 .src_sel_shift = 0,
798 .parent_map = gcc_pxo_pll8_map,
799 },
800 .freq_tbl = clk_tbl_gsbi_uart,
801 .clkr = {
802 .enable_reg = 0x2af4,
803 .enable_mask = BIT(11),
804 .hw.init = &(struct clk_init_data){
805 .name = "gsbi10_uart_src",
806 .parent_names = gcc_pxo_pll8,
807 .num_parents = 2,
808 .ops = &clk_rcg_ops,
809 .flags = CLK_SET_PARENT_GATE,
810 },
811 },
812 };
813
814 static struct clk_branch gsbi10_uart_clk = {
815 .halt_reg = 0x2fd0,
816 .halt_bit = 2,
817 .clkr = {
818 .enable_reg = 0x2af4,
819 .enable_mask = BIT(9),
820 .hw.init = &(struct clk_init_data){
821 .name = "gsbi10_uart_clk",
822 .parent_names = (const char *[]){ "gsbi10_uart_src" },
823 .num_parents = 1,
824 .ops = &clk_branch_ops,
825 .flags = CLK_SET_RATE_PARENT,
826 },
827 },
828 };
829
830 static struct clk_rcg gsbi11_uart_src = {
831 .ns_reg = 0x2b14,
832 .md_reg = 0x2b10,
833 .mn = {
834 .mnctr_en_bit = 8,
835 .mnctr_reset_bit = 7,
836 .mnctr_mode_shift = 5,
837 .n_val_shift = 16,
838 .m_val_shift = 16,
839 .width = 16,
840 },
841 .p = {
842 .pre_div_shift = 3,
843 .pre_div_width = 2,
844 },
845 .s = {
846 .src_sel_shift = 0,
847 .parent_map = gcc_pxo_pll8_map,
848 },
849 .freq_tbl = clk_tbl_gsbi_uart,
850 .clkr = {
851 .enable_reg = 0x2b14,
852 .enable_mask = BIT(11),
853 .hw.init = &(struct clk_init_data){
854 .name = "gsbi11_uart_src",
855 .parent_names = gcc_pxo_pll8,
856 .num_parents = 2,
857 .ops = &clk_rcg_ops,
858 .flags = CLK_SET_PARENT_GATE,
859 },
860 },
861 };
862
863 static struct clk_branch gsbi11_uart_clk = {
864 .halt_reg = 0x2fd4,
865 .halt_bit = 17,
866 .clkr = {
867 .enable_reg = 0x2b14,
868 .enable_mask = BIT(9),
869 .hw.init = &(struct clk_init_data){
870 .name = "gsbi11_uart_clk",
871 .parent_names = (const char *[]){ "gsbi11_uart_src" },
872 .num_parents = 1,
873 .ops = &clk_branch_ops,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876 },
877 };
878
879 static struct clk_rcg gsbi12_uart_src = {
880 .ns_reg = 0x2b34,
881 .md_reg = 0x2b30,
882 .mn = {
883 .mnctr_en_bit = 8,
884 .mnctr_reset_bit = 7,
885 .mnctr_mode_shift = 5,
886 .n_val_shift = 16,
887 .m_val_shift = 16,
888 .width = 16,
889 },
890 .p = {
891 .pre_div_shift = 3,
892 .pre_div_width = 2,
893 },
894 .s = {
895 .src_sel_shift = 0,
896 .parent_map = gcc_pxo_pll8_map,
897 },
898 .freq_tbl = clk_tbl_gsbi_uart,
899 .clkr = {
900 .enable_reg = 0x2b34,
901 .enable_mask = BIT(11),
902 .hw.init = &(struct clk_init_data){
903 .name = "gsbi12_uart_src",
904 .parent_names = gcc_pxo_pll8,
905 .num_parents = 2,
906 .ops = &clk_rcg_ops,
907 .flags = CLK_SET_PARENT_GATE,
908 },
909 },
910 };
911
912 static struct clk_branch gsbi12_uart_clk = {
913 .halt_reg = 0x2fd4,
914 .halt_bit = 13,
915 .clkr = {
916 .enable_reg = 0x2b34,
917 .enable_mask = BIT(9),
918 .hw.init = &(struct clk_init_data){
919 .name = "gsbi12_uart_clk",
920 .parent_names = (const char *[]){ "gsbi12_uart_src" },
921 .num_parents = 1,
922 .ops = &clk_branch_ops,
923 .flags = CLK_SET_RATE_PARENT,
924 },
925 },
926 };
927
928 static struct freq_tbl clk_tbl_gsbi_qup[] = {
929 { 1100000, P_PXO, 1, 2, 49 },
930 { 5400000, P_PXO, 1, 1, 5 },
931 { 10800000, P_PXO, 1, 2, 5 },
932 { 15060000, P_PLL8, 1, 2, 51 },
933 { 24000000, P_PLL8, 4, 1, 4 },
934 { 25600000, P_PLL8, 1, 1, 15 },
935 { 27000000, P_PXO, 1, 0, 0 },
936 { 48000000, P_PLL8, 4, 1, 2 },
937 { 51200000, P_PLL8, 1, 2, 15 },
938 { }
939 };
940
941 static struct clk_rcg gsbi1_qup_src = {
942 .ns_reg = 0x29cc,
943 .md_reg = 0x29c8,
944 .mn = {
945 .mnctr_en_bit = 8,
946 .mnctr_reset_bit = 7,
947 .mnctr_mode_shift = 5,
948 .n_val_shift = 16,
949 .m_val_shift = 16,
950 .width = 8,
951 },
952 .p = {
953 .pre_div_shift = 3,
954 .pre_div_width = 2,
955 },
956 .s = {
957 .src_sel_shift = 0,
958 .parent_map = gcc_pxo_pll8_map,
959 },
960 .freq_tbl = clk_tbl_gsbi_qup,
961 .clkr = {
962 .enable_reg = 0x29cc,
963 .enable_mask = BIT(11),
964 .hw.init = &(struct clk_init_data){
965 .name = "gsbi1_qup_src",
966 .parent_names = gcc_pxo_pll8,
967 .num_parents = 2,
968 .ops = &clk_rcg_ops,
969 .flags = CLK_SET_PARENT_GATE,
970 },
971 },
972 };
973
974 static struct clk_branch gsbi1_qup_clk = {
975 .halt_reg = 0x2fcc,
976 .halt_bit = 9,
977 .clkr = {
978 .enable_reg = 0x29cc,
979 .enable_mask = BIT(9),
980 .hw.init = &(struct clk_init_data){
981 .name = "gsbi1_qup_clk",
982 .parent_names = (const char *[]){ "gsbi1_qup_src" },
983 .num_parents = 1,
984 .ops = &clk_branch_ops,
985 .flags = CLK_SET_RATE_PARENT,
986 },
987 },
988 };
989
990 static struct clk_rcg gsbi2_qup_src = {
991 .ns_reg = 0x29ec,
992 .md_reg = 0x29e8,
993 .mn = {
994 .mnctr_en_bit = 8,
995 .mnctr_reset_bit = 7,
996 .mnctr_mode_shift = 5,
997 .n_val_shift = 16,
998 .m_val_shift = 16,
999 .width = 8,
1000 },
1001 .p = {
1002 .pre_div_shift = 3,
1003 .pre_div_width = 2,
1004 },
1005 .s = {
1006 .src_sel_shift = 0,
1007 .parent_map = gcc_pxo_pll8_map,
1008 },
1009 .freq_tbl = clk_tbl_gsbi_qup,
1010 .clkr = {
1011 .enable_reg = 0x29ec,
1012 .enable_mask = BIT(11),
1013 .hw.init = &(struct clk_init_data){
1014 .name = "gsbi2_qup_src",
1015 .parent_names = gcc_pxo_pll8,
1016 .num_parents = 2,
1017 .ops = &clk_rcg_ops,
1018 .flags = CLK_SET_PARENT_GATE,
1019 },
1020 },
1021 };
1022
1023 static struct clk_branch gsbi2_qup_clk = {
1024 .halt_reg = 0x2fcc,
1025 .halt_bit = 4,
1026 .clkr = {
1027 .enable_reg = 0x29ec,
1028 .enable_mask = BIT(9),
1029 .hw.init = &(struct clk_init_data){
1030 .name = "gsbi2_qup_clk",
1031 .parent_names = (const char *[]){ "gsbi2_qup_src" },
1032 .num_parents = 1,
1033 .ops = &clk_branch_ops,
1034 .flags = CLK_SET_RATE_PARENT,
1035 },
1036 },
1037 };
1038
1039 static struct clk_rcg gsbi3_qup_src = {
1040 .ns_reg = 0x2a0c,
1041 .md_reg = 0x2a08,
1042 .mn = {
1043 .mnctr_en_bit = 8,
1044 .mnctr_reset_bit = 7,
1045 .mnctr_mode_shift = 5,
1046 .n_val_shift = 16,
1047 .m_val_shift = 16,
1048 .width = 8,
1049 },
1050 .p = {
1051 .pre_div_shift = 3,
1052 .pre_div_width = 2,
1053 },
1054 .s = {
1055 .src_sel_shift = 0,
1056 .parent_map = gcc_pxo_pll8_map,
1057 },
1058 .freq_tbl = clk_tbl_gsbi_qup,
1059 .clkr = {
1060 .enable_reg = 0x2a0c,
1061 .enable_mask = BIT(11),
1062 .hw.init = &(struct clk_init_data){
1063 .name = "gsbi3_qup_src",
1064 .parent_names = gcc_pxo_pll8,
1065 .num_parents = 2,
1066 .ops = &clk_rcg_ops,
1067 .flags = CLK_SET_PARENT_GATE,
1068 },
1069 },
1070 };
1071
1072 static struct clk_branch gsbi3_qup_clk = {
1073 .halt_reg = 0x2fcc,
1074 .halt_bit = 0,
1075 .clkr = {
1076 .enable_reg = 0x2a0c,
1077 .enable_mask = BIT(9),
1078 .hw.init = &(struct clk_init_data){
1079 .name = "gsbi3_qup_clk",
1080 .parent_names = (const char *[]){ "gsbi3_qup_src" },
1081 .num_parents = 1,
1082 .ops = &clk_branch_ops,
1083 .flags = CLK_SET_RATE_PARENT,
1084 },
1085 },
1086 };
1087
1088 static struct clk_rcg gsbi4_qup_src = {
1089 .ns_reg = 0x2a2c,
1090 .md_reg = 0x2a28,
1091 .mn = {
1092 .mnctr_en_bit = 8,
1093 .mnctr_reset_bit = 7,
1094 .mnctr_mode_shift = 5,
1095 .n_val_shift = 16,
1096 .m_val_shift = 16,
1097 .width = 8,
1098 },
1099 .p = {
1100 .pre_div_shift = 3,
1101 .pre_div_width = 2,
1102 },
1103 .s = {
1104 .src_sel_shift = 0,
1105 .parent_map = gcc_pxo_pll8_map,
1106 },
1107 .freq_tbl = clk_tbl_gsbi_qup,
1108 .clkr = {
1109 .enable_reg = 0x2a2c,
1110 .enable_mask = BIT(11),
1111 .hw.init = &(struct clk_init_data){
1112 .name = "gsbi4_qup_src",
1113 .parent_names = gcc_pxo_pll8,
1114 .num_parents = 2,
1115 .ops = &clk_rcg_ops,
1116 .flags = CLK_SET_PARENT_GATE,
1117 },
1118 },
1119 };
1120
1121 static struct clk_branch gsbi4_qup_clk = {
1122 .halt_reg = 0x2fd0,
1123 .halt_bit = 24,
1124 .clkr = {
1125 .enable_reg = 0x2a2c,
1126 .enable_mask = BIT(9),
1127 .hw.init = &(struct clk_init_data){
1128 .name = "gsbi4_qup_clk",
1129 .parent_names = (const char *[]){ "gsbi4_qup_src" },
1130 .num_parents = 1,
1131 .ops = &clk_branch_ops,
1132 .flags = CLK_SET_RATE_PARENT,
1133 },
1134 },
1135 };
1136
1137 static struct clk_rcg gsbi5_qup_src = {
1138 .ns_reg = 0x2a4c,
1139 .md_reg = 0x2a48,
1140 .mn = {
1141 .mnctr_en_bit = 8,
1142 .mnctr_reset_bit = 7,
1143 .mnctr_mode_shift = 5,
1144 .n_val_shift = 16,
1145 .m_val_shift = 16,
1146 .width = 8,
1147 },
1148 .p = {
1149 .pre_div_shift = 3,
1150 .pre_div_width = 2,
1151 },
1152 .s = {
1153 .src_sel_shift = 0,
1154 .parent_map = gcc_pxo_pll8_map,
1155 },
1156 .freq_tbl = clk_tbl_gsbi_qup,
1157 .clkr = {
1158 .enable_reg = 0x2a4c,
1159 .enable_mask = BIT(11),
1160 .hw.init = &(struct clk_init_data){
1161 .name = "gsbi5_qup_src",
1162 .parent_names = gcc_pxo_pll8,
1163 .num_parents = 2,
1164 .ops = &clk_rcg_ops,
1165 .flags = CLK_SET_PARENT_GATE,
1166 },
1167 },
1168 };
1169
1170 static struct clk_branch gsbi5_qup_clk = {
1171 .halt_reg = 0x2fd0,
1172 .halt_bit = 20,
1173 .clkr = {
1174 .enable_reg = 0x2a4c,
1175 .enable_mask = BIT(9),
1176 .hw.init = &(struct clk_init_data){
1177 .name = "gsbi5_qup_clk",
1178 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1179 .num_parents = 1,
1180 .ops = &clk_branch_ops,
1181 .flags = CLK_SET_RATE_PARENT,
1182 },
1183 },
1184 };
1185
1186 static struct clk_rcg gsbi6_qup_src = {
1187 .ns_reg = 0x2a6c,
1188 .md_reg = 0x2a68,
1189 .mn = {
1190 .mnctr_en_bit = 8,
1191 .mnctr_reset_bit = 7,
1192 .mnctr_mode_shift = 5,
1193 .n_val_shift = 16,
1194 .m_val_shift = 16,
1195 .width = 8,
1196 },
1197 .p = {
1198 .pre_div_shift = 3,
1199 .pre_div_width = 2,
1200 },
1201 .s = {
1202 .src_sel_shift = 0,
1203 .parent_map = gcc_pxo_pll8_map,
1204 },
1205 .freq_tbl = clk_tbl_gsbi_qup,
1206 .clkr = {
1207 .enable_reg = 0x2a6c,
1208 .enable_mask = BIT(11),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "gsbi6_qup_src",
1211 .parent_names = gcc_pxo_pll8,
1212 .num_parents = 2,
1213 .ops = &clk_rcg_ops,
1214 .flags = CLK_SET_PARENT_GATE,
1215 },
1216 },
1217 };
1218
1219 static struct clk_branch gsbi6_qup_clk = {
1220 .halt_reg = 0x2fd0,
1221 .halt_bit = 16,
1222 .clkr = {
1223 .enable_reg = 0x2a6c,
1224 .enable_mask = BIT(9),
1225 .hw.init = &(struct clk_init_data){
1226 .name = "gsbi6_qup_clk",
1227 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1228 .num_parents = 1,
1229 .ops = &clk_branch_ops,
1230 .flags = CLK_SET_RATE_PARENT,
1231 },
1232 },
1233 };
1234
1235 static struct clk_rcg gsbi7_qup_src = {
1236 .ns_reg = 0x2a8c,
1237 .md_reg = 0x2a88,
1238 .mn = {
1239 .mnctr_en_bit = 8,
1240 .mnctr_reset_bit = 7,
1241 .mnctr_mode_shift = 5,
1242 .n_val_shift = 16,
1243 .m_val_shift = 16,
1244 .width = 8,
1245 },
1246 .p = {
1247 .pre_div_shift = 3,
1248 .pre_div_width = 2,
1249 },
1250 .s = {
1251 .src_sel_shift = 0,
1252 .parent_map = gcc_pxo_pll8_map,
1253 },
1254 .freq_tbl = clk_tbl_gsbi_qup,
1255 .clkr = {
1256 .enable_reg = 0x2a8c,
1257 .enable_mask = BIT(11),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "gsbi7_qup_src",
1260 .parent_names = gcc_pxo_pll8,
1261 .num_parents = 2,
1262 .ops = &clk_rcg_ops,
1263 .flags = CLK_SET_PARENT_GATE,
1264 },
1265 },
1266 };
1267
1268 static struct clk_branch gsbi7_qup_clk = {
1269 .halt_reg = 0x2fd0,
1270 .halt_bit = 12,
1271 .clkr = {
1272 .enable_reg = 0x2a8c,
1273 .enable_mask = BIT(9),
1274 .hw.init = &(struct clk_init_data){
1275 .name = "gsbi7_qup_clk",
1276 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1277 .num_parents = 1,
1278 .ops = &clk_branch_ops,
1279 .flags = CLK_SET_RATE_PARENT,
1280 },
1281 },
1282 };
1283
1284 static struct clk_rcg gsbi8_qup_src = {
1285 .ns_reg = 0x2aac,
1286 .md_reg = 0x2aa8,
1287 .mn = {
1288 .mnctr_en_bit = 8,
1289 .mnctr_reset_bit = 7,
1290 .mnctr_mode_shift = 5,
1291 .n_val_shift = 16,
1292 .m_val_shift = 16,
1293 .width = 8,
1294 },
1295 .p = {
1296 .pre_div_shift = 3,
1297 .pre_div_width = 2,
1298 },
1299 .s = {
1300 .src_sel_shift = 0,
1301 .parent_map = gcc_pxo_pll8_map,
1302 },
1303 .freq_tbl = clk_tbl_gsbi_qup,
1304 .clkr = {
1305 .enable_reg = 0x2aac,
1306 .enable_mask = BIT(11),
1307 .hw.init = &(struct clk_init_data){
1308 .name = "gsbi8_qup_src",
1309 .parent_names = gcc_pxo_pll8,
1310 .num_parents = 2,
1311 .ops = &clk_rcg_ops,
1312 .flags = CLK_SET_PARENT_GATE,
1313 },
1314 },
1315 };
1316
1317 static struct clk_branch gsbi8_qup_clk = {
1318 .halt_reg = 0x2fd0,
1319 .halt_bit = 8,
1320 .clkr = {
1321 .enable_reg = 0x2aac,
1322 .enable_mask = BIT(9),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "gsbi8_qup_clk",
1325 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1326 .num_parents = 1,
1327 .ops = &clk_branch_ops,
1328 .flags = CLK_SET_RATE_PARENT,
1329 },
1330 },
1331 };
1332
1333 static struct clk_rcg gsbi9_qup_src = {
1334 .ns_reg = 0x2acc,
1335 .md_reg = 0x2ac8,
1336 .mn = {
1337 .mnctr_en_bit = 8,
1338 .mnctr_reset_bit = 7,
1339 .mnctr_mode_shift = 5,
1340 .n_val_shift = 16,
1341 .m_val_shift = 16,
1342 .width = 8,
1343 },
1344 .p = {
1345 .pre_div_shift = 3,
1346 .pre_div_width = 2,
1347 },
1348 .s = {
1349 .src_sel_shift = 0,
1350 .parent_map = gcc_pxo_pll8_map,
1351 },
1352 .freq_tbl = clk_tbl_gsbi_qup,
1353 .clkr = {
1354 .enable_reg = 0x2acc,
1355 .enable_mask = BIT(11),
1356 .hw.init = &(struct clk_init_data){
1357 .name = "gsbi9_qup_src",
1358 .parent_names = gcc_pxo_pll8,
1359 .num_parents = 2,
1360 .ops = &clk_rcg_ops,
1361 .flags = CLK_SET_PARENT_GATE,
1362 },
1363 },
1364 };
1365
1366 static struct clk_branch gsbi9_qup_clk = {
1367 .halt_reg = 0x2fd0,
1368 .halt_bit = 4,
1369 .clkr = {
1370 .enable_reg = 0x2acc,
1371 .enable_mask = BIT(9),
1372 .hw.init = &(struct clk_init_data){
1373 .name = "gsbi9_qup_clk",
1374 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1375 .num_parents = 1,
1376 .ops = &clk_branch_ops,
1377 .flags = CLK_SET_RATE_PARENT,
1378 },
1379 },
1380 };
1381
1382 static struct clk_rcg gsbi10_qup_src = {
1383 .ns_reg = 0x2aec,
1384 .md_reg = 0x2ae8,
1385 .mn = {
1386 .mnctr_en_bit = 8,
1387 .mnctr_reset_bit = 7,
1388 .mnctr_mode_shift = 5,
1389 .n_val_shift = 16,
1390 .m_val_shift = 16,
1391 .width = 8,
1392 },
1393 .p = {
1394 .pre_div_shift = 3,
1395 .pre_div_width = 2,
1396 },
1397 .s = {
1398 .src_sel_shift = 0,
1399 .parent_map = gcc_pxo_pll8_map,
1400 },
1401 .freq_tbl = clk_tbl_gsbi_qup,
1402 .clkr = {
1403 .enable_reg = 0x2aec,
1404 .enable_mask = BIT(11),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "gsbi10_qup_src",
1407 .parent_names = gcc_pxo_pll8,
1408 .num_parents = 2,
1409 .ops = &clk_rcg_ops,
1410 .flags = CLK_SET_PARENT_GATE,
1411 },
1412 },
1413 };
1414
1415 static struct clk_branch gsbi10_qup_clk = {
1416 .halt_reg = 0x2fd0,
1417 .halt_bit = 0,
1418 .clkr = {
1419 .enable_reg = 0x2aec,
1420 .enable_mask = BIT(9),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gsbi10_qup_clk",
1423 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1424 .num_parents = 1,
1425 .ops = &clk_branch_ops,
1426 .flags = CLK_SET_RATE_PARENT,
1427 },
1428 },
1429 };
1430
1431 static struct clk_rcg gsbi11_qup_src = {
1432 .ns_reg = 0x2b0c,
1433 .md_reg = 0x2b08,
1434 .mn = {
1435 .mnctr_en_bit = 8,
1436 .mnctr_reset_bit = 7,
1437 .mnctr_mode_shift = 5,
1438 .n_val_shift = 16,
1439 .m_val_shift = 16,
1440 .width = 8,
1441 },
1442 .p = {
1443 .pre_div_shift = 3,
1444 .pre_div_width = 2,
1445 },
1446 .s = {
1447 .src_sel_shift = 0,
1448 .parent_map = gcc_pxo_pll8_map,
1449 },
1450 .freq_tbl = clk_tbl_gsbi_qup,
1451 .clkr = {
1452 .enable_reg = 0x2b0c,
1453 .enable_mask = BIT(11),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gsbi11_qup_src",
1456 .parent_names = gcc_pxo_pll8,
1457 .num_parents = 2,
1458 .ops = &clk_rcg_ops,
1459 .flags = CLK_SET_PARENT_GATE,
1460 },
1461 },
1462 };
1463
1464 static struct clk_branch gsbi11_qup_clk = {
1465 .halt_reg = 0x2fd4,
1466 .halt_bit = 15,
1467 .clkr = {
1468 .enable_reg = 0x2b0c,
1469 .enable_mask = BIT(9),
1470 .hw.init = &(struct clk_init_data){
1471 .name = "gsbi11_qup_clk",
1472 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1473 .num_parents = 1,
1474 .ops = &clk_branch_ops,
1475 .flags = CLK_SET_RATE_PARENT,
1476 },
1477 },
1478 };
1479
1480 static struct clk_rcg gsbi12_qup_src = {
1481 .ns_reg = 0x2b2c,
1482 .md_reg = 0x2b28,
1483 .mn = {
1484 .mnctr_en_bit = 8,
1485 .mnctr_reset_bit = 7,
1486 .mnctr_mode_shift = 5,
1487 .n_val_shift = 16,
1488 .m_val_shift = 16,
1489 .width = 8,
1490 },
1491 .p = {
1492 .pre_div_shift = 3,
1493 .pre_div_width = 2,
1494 },
1495 .s = {
1496 .src_sel_shift = 0,
1497 .parent_map = gcc_pxo_pll8_map,
1498 },
1499 .freq_tbl = clk_tbl_gsbi_qup,
1500 .clkr = {
1501 .enable_reg = 0x2b2c,
1502 .enable_mask = BIT(11),
1503 .hw.init = &(struct clk_init_data){
1504 .name = "gsbi12_qup_src",
1505 .parent_names = gcc_pxo_pll8,
1506 .num_parents = 2,
1507 .ops = &clk_rcg_ops,
1508 .flags = CLK_SET_PARENT_GATE,
1509 },
1510 },
1511 };
1512
1513 static struct clk_branch gsbi12_qup_clk = {
1514 .halt_reg = 0x2fd4,
1515 .halt_bit = 11,
1516 .clkr = {
1517 .enable_reg = 0x2b2c,
1518 .enable_mask = BIT(9),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "gsbi12_qup_clk",
1521 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1522 .num_parents = 1,
1523 .ops = &clk_branch_ops,
1524 .flags = CLK_SET_RATE_PARENT,
1525 },
1526 },
1527 };
1528
1529 static const struct freq_tbl clk_tbl_gp[] = {
1530 { 9600000, P_CXO, 2, 0, 0 },
1531 { 13500000, P_PXO, 2, 0, 0 },
1532 { 19200000, P_CXO, 1, 0, 0 },
1533 { 27000000, P_PXO, 1, 0, 0 },
1534 { 64000000, P_PLL8, 2, 1, 3 },
1535 { 76800000, P_PLL8, 1, 1, 5 },
1536 { 96000000, P_PLL8, 4, 0, 0 },
1537 { 128000000, P_PLL8, 3, 0, 0 },
1538 { 192000000, P_PLL8, 2, 0, 0 },
1539 { }
1540 };
1541
1542 static struct clk_rcg gp0_src = {
1543 .ns_reg = 0x2d24,
1544 .md_reg = 0x2d00,
1545 .mn = {
1546 .mnctr_en_bit = 8,
1547 .mnctr_reset_bit = 7,
1548 .mnctr_mode_shift = 5,
1549 .n_val_shift = 16,
1550 .m_val_shift = 16,
1551 .width = 8,
1552 },
1553 .p = {
1554 .pre_div_shift = 3,
1555 .pre_div_width = 2,
1556 },
1557 .s = {
1558 .src_sel_shift = 0,
1559 .parent_map = gcc_pxo_pll8_cxo_map,
1560 },
1561 .freq_tbl = clk_tbl_gp,
1562 .clkr = {
1563 .enable_reg = 0x2d24,
1564 .enable_mask = BIT(11),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "gp0_src",
1567 .parent_names = gcc_pxo_pll8_cxo,
1568 .num_parents = 3,
1569 .ops = &clk_rcg_ops,
1570 .flags = CLK_SET_PARENT_GATE,
1571 },
1572 }
1573 };
1574
1575 static struct clk_branch gp0_clk = {
1576 .halt_reg = 0x2fd8,
1577 .halt_bit = 7,
1578 .clkr = {
1579 .enable_reg = 0x2d24,
1580 .enable_mask = BIT(9),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "gp0_clk",
1583 .parent_names = (const char *[]){ "gp0_src" },
1584 .num_parents = 1,
1585 .ops = &clk_branch_ops,
1586 .flags = CLK_SET_RATE_PARENT,
1587 },
1588 },
1589 };
1590
1591 static struct clk_rcg gp1_src = {
1592 .ns_reg = 0x2d44,
1593 .md_reg = 0x2d40,
1594 .mn = {
1595 .mnctr_en_bit = 8,
1596 .mnctr_reset_bit = 7,
1597 .mnctr_mode_shift = 5,
1598 .n_val_shift = 16,
1599 .m_val_shift = 16,
1600 .width = 8,
1601 },
1602 .p = {
1603 .pre_div_shift = 3,
1604 .pre_div_width = 2,
1605 },
1606 .s = {
1607 .src_sel_shift = 0,
1608 .parent_map = gcc_pxo_pll8_cxo_map,
1609 },
1610 .freq_tbl = clk_tbl_gp,
1611 .clkr = {
1612 .enable_reg = 0x2d44,
1613 .enable_mask = BIT(11),
1614 .hw.init = &(struct clk_init_data){
1615 .name = "gp1_src",
1616 .parent_names = gcc_pxo_pll8_cxo,
1617 .num_parents = 3,
1618 .ops = &clk_rcg_ops,
1619 .flags = CLK_SET_RATE_GATE,
1620 },
1621 }
1622 };
1623
1624 static struct clk_branch gp1_clk = {
1625 .halt_reg = 0x2fd8,
1626 .halt_bit = 6,
1627 .clkr = {
1628 .enable_reg = 0x2d44,
1629 .enable_mask = BIT(9),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "gp1_clk",
1632 .parent_names = (const char *[]){ "gp1_src" },
1633 .num_parents = 1,
1634 .ops = &clk_branch_ops,
1635 .flags = CLK_SET_RATE_PARENT,
1636 },
1637 },
1638 };
1639
1640 static struct clk_rcg gp2_src = {
1641 .ns_reg = 0x2d64,
1642 .md_reg = 0x2d60,
1643 .mn = {
1644 .mnctr_en_bit = 8,
1645 .mnctr_reset_bit = 7,
1646 .mnctr_mode_shift = 5,
1647 .n_val_shift = 16,
1648 .m_val_shift = 16,
1649 .width = 8,
1650 },
1651 .p = {
1652 .pre_div_shift = 3,
1653 .pre_div_width = 2,
1654 },
1655 .s = {
1656 .src_sel_shift = 0,
1657 .parent_map = gcc_pxo_pll8_cxo_map,
1658 },
1659 .freq_tbl = clk_tbl_gp,
1660 .clkr = {
1661 .enable_reg = 0x2d64,
1662 .enable_mask = BIT(11),
1663 .hw.init = &(struct clk_init_data){
1664 .name = "gp2_src",
1665 .parent_names = gcc_pxo_pll8_cxo,
1666 .num_parents = 3,
1667 .ops = &clk_rcg_ops,
1668 .flags = CLK_SET_RATE_GATE,
1669 },
1670 }
1671 };
1672
1673 static struct clk_branch gp2_clk = {
1674 .halt_reg = 0x2fd8,
1675 .halt_bit = 5,
1676 .clkr = {
1677 .enable_reg = 0x2d64,
1678 .enable_mask = BIT(9),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "gp2_clk",
1681 .parent_names = (const char *[]){ "gp2_src" },
1682 .num_parents = 1,
1683 .ops = &clk_branch_ops,
1684 .flags = CLK_SET_RATE_PARENT,
1685 },
1686 },
1687 };
1688
1689 static struct clk_branch pmem_clk = {
1690 .hwcg_reg = 0x25a0,
1691 .hwcg_bit = 6,
1692 .halt_reg = 0x2fc8,
1693 .halt_bit = 20,
1694 .clkr = {
1695 .enable_reg = 0x25a0,
1696 .enable_mask = BIT(4),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "pmem_clk",
1699 .ops = &clk_branch_ops,
1700 },
1701 },
1702 };
1703
1704 static struct clk_rcg prng_src = {
1705 .ns_reg = 0x2e80,
1706 .p = {
1707 .pre_div_shift = 3,
1708 .pre_div_width = 4,
1709 },
1710 .s = {
1711 .src_sel_shift = 0,
1712 .parent_map = gcc_pxo_pll8_map,
1713 },
1714 .clkr = {
1715 .hw.init = &(struct clk_init_data){
1716 .name = "prng_src",
1717 .parent_names = gcc_pxo_pll8,
1718 .num_parents = 2,
1719 .ops = &clk_rcg_ops,
1720 },
1721 },
1722 };
1723
1724 static struct clk_branch prng_clk = {
1725 .halt_reg = 0x2fd8,
1726 .halt_check = BRANCH_HALT_VOTED,
1727 .halt_bit = 10,
1728 .clkr = {
1729 .enable_reg = 0x3080,
1730 .enable_mask = BIT(10),
1731 .hw.init = &(struct clk_init_data){
1732 .name = "prng_clk",
1733 .parent_names = (const char *[]){ "prng_src" },
1734 .num_parents = 1,
1735 .ops = &clk_branch_ops,
1736 },
1737 },
1738 };
1739
1740 static const struct freq_tbl clk_tbl_sdc[] = {
1741 { 144000, P_PXO, 3, 2, 125 },
1742 { 400000, P_PLL8, 4, 1, 240 },
1743 { 16000000, P_PLL8, 4, 1, 6 },
1744 { 17070000, P_PLL8, 1, 2, 45 },
1745 { 20210000, P_PLL8, 1, 1, 19 },
1746 { 24000000, P_PLL8, 4, 1, 4 },
1747 { 48000000, P_PLL8, 4, 1, 2 },
1748 { 64000000, P_PLL8, 3, 1, 2 },
1749 { 96000000, P_PLL8, 4, 0, 0 },
1750 { 192000000, P_PLL8, 2, 0, 0 },
1751 { }
1752 };
1753
1754 static struct clk_rcg sdc1_src = {
1755 .ns_reg = 0x282c,
1756 .md_reg = 0x2828,
1757 .mn = {
1758 .mnctr_en_bit = 8,
1759 .mnctr_reset_bit = 7,
1760 .mnctr_mode_shift = 5,
1761 .n_val_shift = 16,
1762 .m_val_shift = 16,
1763 .width = 8,
1764 },
1765 .p = {
1766 .pre_div_shift = 3,
1767 .pre_div_width = 2,
1768 },
1769 .s = {
1770 .src_sel_shift = 0,
1771 .parent_map = gcc_pxo_pll8_map,
1772 },
1773 .freq_tbl = clk_tbl_sdc,
1774 .clkr = {
1775 .enable_reg = 0x282c,
1776 .enable_mask = BIT(11),
1777 .hw.init = &(struct clk_init_data){
1778 .name = "sdc1_src",
1779 .parent_names = gcc_pxo_pll8,
1780 .num_parents = 2,
1781 .ops = &clk_rcg_ops,
1782 },
1783 }
1784 };
1785
1786 static struct clk_branch sdc1_clk = {
1787 .halt_reg = 0x2fc8,
1788 .halt_bit = 6,
1789 .clkr = {
1790 .enable_reg = 0x282c,
1791 .enable_mask = BIT(9),
1792 .hw.init = &(struct clk_init_data){
1793 .name = "sdc1_clk",
1794 .parent_names = (const char *[]){ "sdc1_src" },
1795 .num_parents = 1,
1796 .ops = &clk_branch_ops,
1797 .flags = CLK_SET_RATE_PARENT,
1798 },
1799 },
1800 };
1801
1802 static struct clk_rcg sdc2_src = {
1803 .ns_reg = 0x284c,
1804 .md_reg = 0x2848,
1805 .mn = {
1806 .mnctr_en_bit = 8,
1807 .mnctr_reset_bit = 7,
1808 .mnctr_mode_shift = 5,
1809 .n_val_shift = 16,
1810 .m_val_shift = 16,
1811 .width = 8,
1812 },
1813 .p = {
1814 .pre_div_shift = 3,
1815 .pre_div_width = 2,
1816 },
1817 .s = {
1818 .src_sel_shift = 0,
1819 .parent_map = gcc_pxo_pll8_map,
1820 },
1821 .freq_tbl = clk_tbl_sdc,
1822 .clkr = {
1823 .enable_reg = 0x284c,
1824 .enable_mask = BIT(11),
1825 .hw.init = &(struct clk_init_data){
1826 .name = "sdc2_src",
1827 .parent_names = gcc_pxo_pll8,
1828 .num_parents = 2,
1829 .ops = &clk_rcg_ops,
1830 },
1831 }
1832 };
1833
1834 static struct clk_branch sdc2_clk = {
1835 .halt_reg = 0x2fc8,
1836 .halt_bit = 5,
1837 .clkr = {
1838 .enable_reg = 0x284c,
1839 .enable_mask = BIT(9),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "sdc2_clk",
1842 .parent_names = (const char *[]){ "sdc2_src" },
1843 .num_parents = 1,
1844 .ops = &clk_branch_ops,
1845 .flags = CLK_SET_RATE_PARENT,
1846 },
1847 },
1848 };
1849
1850 static struct clk_rcg sdc3_src = {
1851 .ns_reg = 0x286c,
1852 .md_reg = 0x2868,
1853 .mn = {
1854 .mnctr_en_bit = 8,
1855 .mnctr_reset_bit = 7,
1856 .mnctr_mode_shift = 5,
1857 .n_val_shift = 16,
1858 .m_val_shift = 16,
1859 .width = 8,
1860 },
1861 .p = {
1862 .pre_div_shift = 3,
1863 .pre_div_width = 2,
1864 },
1865 .s = {
1866 .src_sel_shift = 0,
1867 .parent_map = gcc_pxo_pll8_map,
1868 },
1869 .freq_tbl = clk_tbl_sdc,
1870 .clkr = {
1871 .enable_reg = 0x286c,
1872 .enable_mask = BIT(11),
1873 .hw.init = &(struct clk_init_data){
1874 .name = "sdc3_src",
1875 .parent_names = gcc_pxo_pll8,
1876 .num_parents = 2,
1877 .ops = &clk_rcg_ops,
1878 },
1879 }
1880 };
1881
1882 static struct clk_branch sdc3_clk = {
1883 .halt_reg = 0x2fc8,
1884 .halt_bit = 4,
1885 .clkr = {
1886 .enable_reg = 0x286c,
1887 .enable_mask = BIT(9),
1888 .hw.init = &(struct clk_init_data){
1889 .name = "sdc3_clk",
1890 .parent_names = (const char *[]){ "sdc3_src" },
1891 .num_parents = 1,
1892 .ops = &clk_branch_ops,
1893 .flags = CLK_SET_RATE_PARENT,
1894 },
1895 },
1896 };
1897
1898 static struct clk_rcg sdc4_src = {
1899 .ns_reg = 0x288c,
1900 .md_reg = 0x2888,
1901 .mn = {
1902 .mnctr_en_bit = 8,
1903 .mnctr_reset_bit = 7,
1904 .mnctr_mode_shift = 5,
1905 .n_val_shift = 16,
1906 .m_val_shift = 16,
1907 .width = 8,
1908 },
1909 .p = {
1910 .pre_div_shift = 3,
1911 .pre_div_width = 2,
1912 },
1913 .s = {
1914 .src_sel_shift = 0,
1915 .parent_map = gcc_pxo_pll8_map,
1916 },
1917 .freq_tbl = clk_tbl_sdc,
1918 .clkr = {
1919 .enable_reg = 0x288c,
1920 .enable_mask = BIT(11),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "sdc4_src",
1923 .parent_names = gcc_pxo_pll8,
1924 .num_parents = 2,
1925 .ops = &clk_rcg_ops,
1926 },
1927 }
1928 };
1929
1930 static struct clk_branch sdc4_clk = {
1931 .halt_reg = 0x2fc8,
1932 .halt_bit = 3,
1933 .clkr = {
1934 .enable_reg = 0x288c,
1935 .enable_mask = BIT(9),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "sdc4_clk",
1938 .parent_names = (const char *[]){ "sdc4_src" },
1939 .num_parents = 1,
1940 .ops = &clk_branch_ops,
1941 .flags = CLK_SET_RATE_PARENT,
1942 },
1943 },
1944 };
1945
1946 static struct clk_rcg sdc5_src = {
1947 .ns_reg = 0x28ac,
1948 .md_reg = 0x28a8,
1949 .mn = {
1950 .mnctr_en_bit = 8,
1951 .mnctr_reset_bit = 7,
1952 .mnctr_mode_shift = 5,
1953 .n_val_shift = 16,
1954 .m_val_shift = 16,
1955 .width = 8,
1956 },
1957 .p = {
1958 .pre_div_shift = 3,
1959 .pre_div_width = 2,
1960 },
1961 .s = {
1962 .src_sel_shift = 0,
1963 .parent_map = gcc_pxo_pll8_map,
1964 },
1965 .freq_tbl = clk_tbl_sdc,
1966 .clkr = {
1967 .enable_reg = 0x28ac,
1968 .enable_mask = BIT(11),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "sdc5_src",
1971 .parent_names = gcc_pxo_pll8,
1972 .num_parents = 2,
1973 .ops = &clk_rcg_ops,
1974 },
1975 }
1976 };
1977
1978 static struct clk_branch sdc5_clk = {
1979 .halt_reg = 0x2fc8,
1980 .halt_bit = 2,
1981 .clkr = {
1982 .enable_reg = 0x28ac,
1983 .enable_mask = BIT(9),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "sdc5_clk",
1986 .parent_names = (const char *[]){ "sdc5_src" },
1987 .num_parents = 1,
1988 .ops = &clk_branch_ops,
1989 .flags = CLK_SET_RATE_PARENT,
1990 },
1991 },
1992 };
1993
1994 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1995 { 105000, P_PXO, 1, 1, 256 },
1996 { }
1997 };
1998
1999 static struct clk_rcg tsif_ref_src = {
2000 .ns_reg = 0x2710,
2001 .md_reg = 0x270c,
2002 .mn = {
2003 .mnctr_en_bit = 8,
2004 .mnctr_reset_bit = 7,
2005 .mnctr_mode_shift = 5,
2006 .n_val_shift = 16,
2007 .m_val_shift = 16,
2008 .width = 16,
2009 },
2010 .p = {
2011 .pre_div_shift = 3,
2012 .pre_div_width = 2,
2013 },
2014 .s = {
2015 .src_sel_shift = 0,
2016 .parent_map = gcc_pxo_pll8_map,
2017 },
2018 .freq_tbl = clk_tbl_tsif_ref,
2019 .clkr = {
2020 .enable_reg = 0x2710,
2021 .enable_mask = BIT(11),
2022 .hw.init = &(struct clk_init_data){
2023 .name = "tsif_ref_src",
2024 .parent_names = gcc_pxo_pll8,
2025 .num_parents = 2,
2026 .ops = &clk_rcg_ops,
2027 .flags = CLK_SET_RATE_GATE,
2028 },
2029 }
2030 };
2031
2032 static struct clk_branch tsif_ref_clk = {
2033 .halt_reg = 0x2fd4,
2034 .halt_bit = 5,
2035 .clkr = {
2036 .enable_reg = 0x2710,
2037 .enable_mask = BIT(9),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "tsif_ref_clk",
2040 .parent_names = (const char *[]){ "tsif_ref_src" },
2041 .num_parents = 1,
2042 .ops = &clk_branch_ops,
2043 .flags = CLK_SET_RATE_PARENT,
2044 },
2045 },
2046 };
2047
2048 static const struct freq_tbl clk_tbl_usb[] = {
2049 { 60000000, P_PLL8, 1, 5, 32 },
2050 { }
2051 };
2052
2053 static struct clk_rcg usb_hs1_xcvr_src = {
2054 .ns_reg = 0x290c,
2055 .md_reg = 0x2908,
2056 .mn = {
2057 .mnctr_en_bit = 8,
2058 .mnctr_reset_bit = 7,
2059 .mnctr_mode_shift = 5,
2060 .n_val_shift = 16,
2061 .m_val_shift = 16,
2062 .width = 8,
2063 },
2064 .p = {
2065 .pre_div_shift = 3,
2066 .pre_div_width = 2,
2067 },
2068 .s = {
2069 .src_sel_shift = 0,
2070 .parent_map = gcc_pxo_pll8_map,
2071 },
2072 .freq_tbl = clk_tbl_usb,
2073 .clkr = {
2074 .enable_reg = 0x290c,
2075 .enable_mask = BIT(11),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "usb_hs1_xcvr_src",
2078 .parent_names = gcc_pxo_pll8,
2079 .num_parents = 2,
2080 .ops = &clk_rcg_ops,
2081 .flags = CLK_SET_RATE_GATE,
2082 },
2083 }
2084 };
2085
2086 static struct clk_branch usb_hs1_xcvr_clk = {
2087 .halt_reg = 0x2fc8,
2088 .halt_bit = 0,
2089 .clkr = {
2090 .enable_reg = 0x290c,
2091 .enable_mask = BIT(9),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "usb_hs1_xcvr_clk",
2094 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2095 .num_parents = 1,
2096 .ops = &clk_branch_ops,
2097 .flags = CLK_SET_RATE_PARENT,
2098 },
2099 },
2100 };
2101
2102 static struct clk_rcg usb_hs3_xcvr_src = {
2103 .ns_reg = 0x370c,
2104 .md_reg = 0x3708,
2105 .mn = {
2106 .mnctr_en_bit = 8,
2107 .mnctr_reset_bit = 7,
2108 .mnctr_mode_shift = 5,
2109 .n_val_shift = 16,
2110 .m_val_shift = 16,
2111 .width = 8,
2112 },
2113 .p = {
2114 .pre_div_shift = 3,
2115 .pre_div_width = 2,
2116 },
2117 .s = {
2118 .src_sel_shift = 0,
2119 .parent_map = gcc_pxo_pll8_map,
2120 },
2121 .freq_tbl = clk_tbl_usb,
2122 .clkr = {
2123 .enable_reg = 0x370c,
2124 .enable_mask = BIT(11),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "usb_hs3_xcvr_src",
2127 .parent_names = gcc_pxo_pll8,
2128 .num_parents = 2,
2129 .ops = &clk_rcg_ops,
2130 .flags = CLK_SET_RATE_GATE,
2131 },
2132 }
2133 };
2134
2135 static struct clk_branch usb_hs3_xcvr_clk = {
2136 .halt_reg = 0x2fc8,
2137 .halt_bit = 30,
2138 .clkr = {
2139 .enable_reg = 0x370c,
2140 .enable_mask = BIT(9),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "usb_hs3_xcvr_clk",
2143 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
2144 .num_parents = 1,
2145 .ops = &clk_branch_ops,
2146 .flags = CLK_SET_RATE_PARENT,
2147 },
2148 },
2149 };
2150
2151 static struct clk_rcg usb_hs4_xcvr_src = {
2152 .ns_reg = 0x372c,
2153 .md_reg = 0x3728,
2154 .mn = {
2155 .mnctr_en_bit = 8,
2156 .mnctr_reset_bit = 7,
2157 .mnctr_mode_shift = 5,
2158 .n_val_shift = 16,
2159 .m_val_shift = 16,
2160 .width = 8,
2161 },
2162 .p = {
2163 .pre_div_shift = 3,
2164 .pre_div_width = 2,
2165 },
2166 .s = {
2167 .src_sel_shift = 0,
2168 .parent_map = gcc_pxo_pll8_map,
2169 },
2170 .freq_tbl = clk_tbl_usb,
2171 .clkr = {
2172 .enable_reg = 0x372c,
2173 .enable_mask = BIT(11),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "usb_hs4_xcvr_src",
2176 .parent_names = gcc_pxo_pll8,
2177 .num_parents = 2,
2178 .ops = &clk_rcg_ops,
2179 .flags = CLK_SET_RATE_GATE,
2180 },
2181 }
2182 };
2183
2184 static struct clk_branch usb_hs4_xcvr_clk = {
2185 .halt_reg = 0x2fc8,
2186 .halt_bit = 2,
2187 .clkr = {
2188 .enable_reg = 0x372c,
2189 .enable_mask = BIT(9),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "usb_hs4_xcvr_clk",
2192 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2193 .num_parents = 1,
2194 .ops = &clk_branch_ops,
2195 .flags = CLK_SET_RATE_PARENT,
2196 },
2197 },
2198 };
2199
2200 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2201 .ns_reg = 0x2928,
2202 .md_reg = 0x2924,
2203 .mn = {
2204 .mnctr_en_bit = 8,
2205 .mnctr_reset_bit = 7,
2206 .mnctr_mode_shift = 5,
2207 .n_val_shift = 16,
2208 .m_val_shift = 16,
2209 .width = 8,
2210 },
2211 .p = {
2212 .pre_div_shift = 3,
2213 .pre_div_width = 2,
2214 },
2215 .s = {
2216 .src_sel_shift = 0,
2217 .parent_map = gcc_pxo_pll8_map,
2218 },
2219 .freq_tbl = clk_tbl_usb,
2220 .clkr = {
2221 .enable_reg = 0x2928,
2222 .enable_mask = BIT(11),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "usb_hsic_xcvr_fs_src",
2225 .parent_names = gcc_pxo_pll8,
2226 .num_parents = 2,
2227 .ops = &clk_rcg_ops,
2228 .flags = CLK_SET_RATE_GATE,
2229 },
2230 }
2231 };
2232
2233 static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2234
2235 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2236 .halt_reg = 0x2fc8,
2237 .halt_bit = 2,
2238 .clkr = {
2239 .enable_reg = 0x2928,
2240 .enable_mask = BIT(9),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "usb_hsic_xcvr_fs_clk",
2243 .parent_names = usb_hsic_xcvr_fs_src_p,
2244 .num_parents = 1,
2245 .ops = &clk_branch_ops,
2246 .flags = CLK_SET_RATE_PARENT,
2247 },
2248 },
2249 };
2250
2251 static struct clk_branch usb_hsic_system_clk = {
2252 .halt_reg = 0x2fcc,
2253 .halt_bit = 24,
2254 .clkr = {
2255 .enable_reg = 0x292c,
2256 .enable_mask = BIT(4),
2257 .hw.init = &(struct clk_init_data){
2258 .parent_names = usb_hsic_xcvr_fs_src_p,
2259 .num_parents = 1,
2260 .name = "usb_hsic_system_clk",
2261 .ops = &clk_branch_ops,
2262 .flags = CLK_SET_RATE_PARENT,
2263 },
2264 },
2265 };
2266
2267 static struct clk_branch usb_hsic_hsic_clk = {
2268 .halt_reg = 0x2fcc,
2269 .halt_bit = 19,
2270 .clkr = {
2271 .enable_reg = 0x2b44,
2272 .enable_mask = BIT(0),
2273 .hw.init = &(struct clk_init_data){
2274 .parent_names = (const char *[]){ "pll14_vote" },
2275 .num_parents = 1,
2276 .name = "usb_hsic_hsic_clk",
2277 .ops = &clk_branch_ops,
2278 },
2279 },
2280 };
2281
2282 static struct clk_branch usb_hsic_hsio_cal_clk = {
2283 .halt_reg = 0x2fcc,
2284 .halt_bit = 23,
2285 .clkr = {
2286 .enable_reg = 0x2b48,
2287 .enable_mask = BIT(0),
2288 .hw.init = &(struct clk_init_data){
2289 .name = "usb_hsic_hsio_cal_clk",
2290 .ops = &clk_branch_ops,
2291 },
2292 },
2293 };
2294
2295 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2296 .ns_reg = 0x2968,
2297 .md_reg = 0x2964,
2298 .mn = {
2299 .mnctr_en_bit = 8,
2300 .mnctr_reset_bit = 7,
2301 .mnctr_mode_shift = 5,
2302 .n_val_shift = 16,
2303 .m_val_shift = 16,
2304 .width = 8,
2305 },
2306 .p = {
2307 .pre_div_shift = 3,
2308 .pre_div_width = 2,
2309 },
2310 .s = {
2311 .src_sel_shift = 0,
2312 .parent_map = gcc_pxo_pll8_map,
2313 },
2314 .freq_tbl = clk_tbl_usb,
2315 .clkr = {
2316 .enable_reg = 0x2968,
2317 .enable_mask = BIT(11),
2318 .hw.init = &(struct clk_init_data){
2319 .name = "usb_fs1_xcvr_fs_src",
2320 .parent_names = gcc_pxo_pll8,
2321 .num_parents = 2,
2322 .ops = &clk_rcg_ops,
2323 .flags = CLK_SET_RATE_GATE,
2324 },
2325 }
2326 };
2327
2328 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2329
2330 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2331 .halt_reg = 0x2fcc,
2332 .halt_bit = 15,
2333 .clkr = {
2334 .enable_reg = 0x2968,
2335 .enable_mask = BIT(9),
2336 .hw.init = &(struct clk_init_data){
2337 .name = "usb_fs1_xcvr_fs_clk",
2338 .parent_names = usb_fs1_xcvr_fs_src_p,
2339 .num_parents = 1,
2340 .ops = &clk_branch_ops,
2341 .flags = CLK_SET_RATE_PARENT,
2342 },
2343 },
2344 };
2345
2346 static struct clk_branch usb_fs1_system_clk = {
2347 .halt_reg = 0x2fcc,
2348 .halt_bit = 16,
2349 .clkr = {
2350 .enable_reg = 0x296c,
2351 .enable_mask = BIT(4),
2352 .hw.init = &(struct clk_init_data){
2353 .parent_names = usb_fs1_xcvr_fs_src_p,
2354 .num_parents = 1,
2355 .name = "usb_fs1_system_clk",
2356 .ops = &clk_branch_ops,
2357 .flags = CLK_SET_RATE_PARENT,
2358 },
2359 },
2360 };
2361
2362 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2363 .ns_reg = 0x2988,
2364 .md_reg = 0x2984,
2365 .mn = {
2366 .mnctr_en_bit = 8,
2367 .mnctr_reset_bit = 7,
2368 .mnctr_mode_shift = 5,
2369 .n_val_shift = 16,
2370 .m_val_shift = 16,
2371 .width = 8,
2372 },
2373 .p = {
2374 .pre_div_shift = 3,
2375 .pre_div_width = 2,
2376 },
2377 .s = {
2378 .src_sel_shift = 0,
2379 .parent_map = gcc_pxo_pll8_map,
2380 },
2381 .freq_tbl = clk_tbl_usb,
2382 .clkr = {
2383 .enable_reg = 0x2988,
2384 .enable_mask = BIT(11),
2385 .hw.init = &(struct clk_init_data){
2386 .name = "usb_fs2_xcvr_fs_src",
2387 .parent_names = gcc_pxo_pll8,
2388 .num_parents = 2,
2389 .ops = &clk_rcg_ops,
2390 .flags = CLK_SET_RATE_GATE,
2391 },
2392 }
2393 };
2394
2395 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2396
2397 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2398 .halt_reg = 0x2fcc,
2399 .halt_bit = 12,
2400 .clkr = {
2401 .enable_reg = 0x2988,
2402 .enable_mask = BIT(9),
2403 .hw.init = &(struct clk_init_data){
2404 .name = "usb_fs2_xcvr_fs_clk",
2405 .parent_names = usb_fs2_xcvr_fs_src_p,
2406 .num_parents = 1,
2407 .ops = &clk_branch_ops,
2408 .flags = CLK_SET_RATE_PARENT,
2409 },
2410 },
2411 };
2412
2413 static struct clk_branch usb_fs2_system_clk = {
2414 .halt_reg = 0x2fcc,
2415 .halt_bit = 13,
2416 .clkr = {
2417 .enable_reg = 0x298c,
2418 .enable_mask = BIT(4),
2419 .hw.init = &(struct clk_init_data){
2420 .name = "usb_fs2_system_clk",
2421 .parent_names = usb_fs2_xcvr_fs_src_p,
2422 .num_parents = 1,
2423 .ops = &clk_branch_ops,
2424 .flags = CLK_SET_RATE_PARENT,
2425 },
2426 },
2427 };
2428
2429 static struct clk_branch ce1_core_clk = {
2430 .hwcg_reg = 0x2724,
2431 .hwcg_bit = 6,
2432 .halt_reg = 0x2fd4,
2433 .halt_bit = 27,
2434 .clkr = {
2435 .enable_reg = 0x2724,
2436 .enable_mask = BIT(4),
2437 .hw.init = &(struct clk_init_data){
2438 .name = "ce1_core_clk",
2439 .ops = &clk_branch_ops,
2440 },
2441 },
2442 };
2443
2444 static struct clk_branch ce1_h_clk = {
2445 .halt_reg = 0x2fd4,
2446 .halt_bit = 1,
2447 .clkr = {
2448 .enable_reg = 0x2720,
2449 .enable_mask = BIT(4),
2450 .hw.init = &(struct clk_init_data){
2451 .name = "ce1_h_clk",
2452 .ops = &clk_branch_ops,
2453 },
2454 },
2455 };
2456
2457 static struct clk_branch dma_bam_h_clk = {
2458 .hwcg_reg = 0x25c0,
2459 .hwcg_bit = 6,
2460 .halt_reg = 0x2fc8,
2461 .halt_bit = 12,
2462 .clkr = {
2463 .enable_reg = 0x25c0,
2464 .enable_mask = BIT(4),
2465 .hw.init = &(struct clk_init_data){
2466 .name = "dma_bam_h_clk",
2467 .ops = &clk_branch_ops,
2468 },
2469 },
2470 };
2471
2472 static struct clk_branch gsbi1_h_clk = {
2473 .hwcg_reg = 0x29c0,
2474 .hwcg_bit = 6,
2475 .halt_reg = 0x2fcc,
2476 .halt_bit = 11,
2477 .clkr = {
2478 .enable_reg = 0x29c0,
2479 .enable_mask = BIT(4),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "gsbi1_h_clk",
2482 .ops = &clk_branch_ops,
2483 },
2484 },
2485 };
2486
2487 static struct clk_branch gsbi2_h_clk = {
2488 .hwcg_reg = 0x29e0,
2489 .hwcg_bit = 6,
2490 .halt_reg = 0x2fcc,
2491 .halt_bit = 7,
2492 .clkr = {
2493 .enable_reg = 0x29e0,
2494 .enable_mask = BIT(4),
2495 .hw.init = &(struct clk_init_data){
2496 .name = "gsbi2_h_clk",
2497 .ops = &clk_branch_ops,
2498 },
2499 },
2500 };
2501
2502 static struct clk_branch gsbi3_h_clk = {
2503 .hwcg_reg = 0x2a00,
2504 .hwcg_bit = 6,
2505 .halt_reg = 0x2fcc,
2506 .halt_bit = 3,
2507 .clkr = {
2508 .enable_reg = 0x2a00,
2509 .enable_mask = BIT(4),
2510 .hw.init = &(struct clk_init_data){
2511 .name = "gsbi3_h_clk",
2512 .ops = &clk_branch_ops,
2513 },
2514 },
2515 };
2516
2517 static struct clk_branch gsbi4_h_clk = {
2518 .hwcg_reg = 0x2a20,
2519 .hwcg_bit = 6,
2520 .halt_reg = 0x2fd0,
2521 .halt_bit = 27,
2522 .clkr = {
2523 .enable_reg = 0x2a20,
2524 .enable_mask = BIT(4),
2525 .hw.init = &(struct clk_init_data){
2526 .name = "gsbi4_h_clk",
2527 .ops = &clk_branch_ops,
2528 },
2529 },
2530 };
2531
2532 static struct clk_branch gsbi5_h_clk = {
2533 .hwcg_reg = 0x2a40,
2534 .hwcg_bit = 6,
2535 .halt_reg = 0x2fd0,
2536 .halt_bit = 23,
2537 .clkr = {
2538 .enable_reg = 0x2a40,
2539 .enable_mask = BIT(4),
2540 .hw.init = &(struct clk_init_data){
2541 .name = "gsbi5_h_clk",
2542 .ops = &clk_branch_ops,
2543 },
2544 },
2545 };
2546
2547 static struct clk_branch gsbi6_h_clk = {
2548 .hwcg_reg = 0x2a60,
2549 .hwcg_bit = 6,
2550 .halt_reg = 0x2fd0,
2551 .halt_bit = 19,
2552 .clkr = {
2553 .enable_reg = 0x2a60,
2554 .enable_mask = BIT(4),
2555 .hw.init = &(struct clk_init_data){
2556 .name = "gsbi6_h_clk",
2557 .ops = &clk_branch_ops,
2558 },
2559 },
2560 };
2561
2562 static struct clk_branch gsbi7_h_clk = {
2563 .hwcg_reg = 0x2a80,
2564 .hwcg_bit = 6,
2565 .halt_reg = 0x2fd0,
2566 .halt_bit = 15,
2567 .clkr = {
2568 .enable_reg = 0x2a80,
2569 .enable_mask = BIT(4),
2570 .hw.init = &(struct clk_init_data){
2571 .name = "gsbi7_h_clk",
2572 .ops = &clk_branch_ops,
2573 },
2574 },
2575 };
2576
2577 static struct clk_branch gsbi8_h_clk = {
2578 .hwcg_reg = 0x2aa0,
2579 .hwcg_bit = 6,
2580 .halt_reg = 0x2fd0,
2581 .halt_bit = 11,
2582 .clkr = {
2583 .enable_reg = 0x2aa0,
2584 .enable_mask = BIT(4),
2585 .hw.init = &(struct clk_init_data){
2586 .name = "gsbi8_h_clk",
2587 .ops = &clk_branch_ops,
2588 },
2589 },
2590 };
2591
2592 static struct clk_branch gsbi9_h_clk = {
2593 .hwcg_reg = 0x2ac0,
2594 .hwcg_bit = 6,
2595 .halt_reg = 0x2fd0,
2596 .halt_bit = 7,
2597 .clkr = {
2598 .enable_reg = 0x2ac0,
2599 .enable_mask = BIT(4),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gsbi9_h_clk",
2602 .ops = &clk_branch_ops,
2603 },
2604 },
2605 };
2606
2607 static struct clk_branch gsbi10_h_clk = {
2608 .hwcg_reg = 0x2ae0,
2609 .hwcg_bit = 6,
2610 .halt_reg = 0x2fd0,
2611 .halt_bit = 3,
2612 .clkr = {
2613 .enable_reg = 0x2ae0,
2614 .enable_mask = BIT(4),
2615 .hw.init = &(struct clk_init_data){
2616 .name = "gsbi10_h_clk",
2617 .ops = &clk_branch_ops,
2618 },
2619 },
2620 };
2621
2622 static struct clk_branch gsbi11_h_clk = {
2623 .hwcg_reg = 0x2b00,
2624 .hwcg_bit = 6,
2625 .halt_reg = 0x2fd4,
2626 .halt_bit = 18,
2627 .clkr = {
2628 .enable_reg = 0x2b00,
2629 .enable_mask = BIT(4),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "gsbi11_h_clk",
2632 .ops = &clk_branch_ops,
2633 },
2634 },
2635 };
2636
2637 static struct clk_branch gsbi12_h_clk = {
2638 .hwcg_reg = 0x2b20,
2639 .hwcg_bit = 6,
2640 .halt_reg = 0x2fd4,
2641 .halt_bit = 14,
2642 .clkr = {
2643 .enable_reg = 0x2b20,
2644 .enable_mask = BIT(4),
2645 .hw.init = &(struct clk_init_data){
2646 .name = "gsbi12_h_clk",
2647 .ops = &clk_branch_ops,
2648 },
2649 },
2650 };
2651
2652 static struct clk_branch tsif_h_clk = {
2653 .hwcg_reg = 0x2700,
2654 .hwcg_bit = 6,
2655 .halt_reg = 0x2fd4,
2656 .halt_bit = 7,
2657 .clkr = {
2658 .enable_reg = 0x2700,
2659 .enable_mask = BIT(4),
2660 .hw.init = &(struct clk_init_data){
2661 .name = "tsif_h_clk",
2662 .ops = &clk_branch_ops,
2663 },
2664 },
2665 };
2666
2667 static struct clk_branch usb_fs1_h_clk = {
2668 .halt_reg = 0x2fcc,
2669 .halt_bit = 17,
2670 .clkr = {
2671 .enable_reg = 0x2960,
2672 .enable_mask = BIT(4),
2673 .hw.init = &(struct clk_init_data){
2674 .name = "usb_fs1_h_clk",
2675 .ops = &clk_branch_ops,
2676 },
2677 },
2678 };
2679
2680 static struct clk_branch usb_fs2_h_clk = {
2681 .halt_reg = 0x2fcc,
2682 .halt_bit = 14,
2683 .clkr = {
2684 .enable_reg = 0x2980,
2685 .enable_mask = BIT(4),
2686 .hw.init = &(struct clk_init_data){
2687 .name = "usb_fs2_h_clk",
2688 .ops = &clk_branch_ops,
2689 },
2690 },
2691 };
2692
2693 static struct clk_branch usb_hs1_h_clk = {
2694 .hwcg_reg = 0x2900,
2695 .hwcg_bit = 6,
2696 .halt_reg = 0x2fc8,
2697 .halt_bit = 1,
2698 .clkr = {
2699 .enable_reg = 0x2900,
2700 .enable_mask = BIT(4),
2701 .hw.init = &(struct clk_init_data){
2702 .name = "usb_hs1_h_clk",
2703 .ops = &clk_branch_ops,
2704 },
2705 },
2706 };
2707
2708 static struct clk_branch usb_hs3_h_clk = {
2709 .halt_reg = 0x2fc8,
2710 .halt_bit = 31,
2711 .clkr = {
2712 .enable_reg = 0x3700,
2713 .enable_mask = BIT(4),
2714 .hw.init = &(struct clk_init_data){
2715 .name = "usb_hs3_h_clk",
2716 .ops = &clk_branch_ops,
2717 },
2718 },
2719 };
2720
2721 static struct clk_branch usb_hs4_h_clk = {
2722 .halt_reg = 0x2fc8,
2723 .halt_bit = 7,
2724 .clkr = {
2725 .enable_reg = 0x3720,
2726 .enable_mask = BIT(4),
2727 .hw.init = &(struct clk_init_data){
2728 .name = "usb_hs4_h_clk",
2729 .ops = &clk_branch_ops,
2730 },
2731 },
2732 };
2733
2734 static struct clk_branch usb_hsic_h_clk = {
2735 .halt_reg = 0x2fcc,
2736 .halt_bit = 28,
2737 .clkr = {
2738 .enable_reg = 0x2920,
2739 .enable_mask = BIT(4),
2740 .hw.init = &(struct clk_init_data){
2741 .name = "usb_hsic_h_clk",
2742 .ops = &clk_branch_ops,
2743 },
2744 },
2745 };
2746
2747 static struct clk_branch sdc1_h_clk = {
2748 .hwcg_reg = 0x2820,
2749 .hwcg_bit = 6,
2750 .halt_reg = 0x2fc8,
2751 .halt_bit = 11,
2752 .clkr = {
2753 .enable_reg = 0x2820,
2754 .enable_mask = BIT(4),
2755 .hw.init = &(struct clk_init_data){
2756 .name = "sdc1_h_clk",
2757 .ops = &clk_branch_ops,
2758 },
2759 },
2760 };
2761
2762 static struct clk_branch sdc2_h_clk = {
2763 .hwcg_reg = 0x2840,
2764 .hwcg_bit = 6,
2765 .halt_reg = 0x2fc8,
2766 .halt_bit = 10,
2767 .clkr = {
2768 .enable_reg = 0x2840,
2769 .enable_mask = BIT(4),
2770 .hw.init = &(struct clk_init_data){
2771 .name = "sdc2_h_clk",
2772 .ops = &clk_branch_ops,
2773 },
2774 },
2775 };
2776
2777 static struct clk_branch sdc3_h_clk = {
2778 .hwcg_reg = 0x2860,
2779 .hwcg_bit = 6,
2780 .halt_reg = 0x2fc8,
2781 .halt_bit = 9,
2782 .clkr = {
2783 .enable_reg = 0x2860,
2784 .enable_mask = BIT(4),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "sdc3_h_clk",
2787 .ops = &clk_branch_ops,
2788 },
2789 },
2790 };
2791
2792 static struct clk_branch sdc4_h_clk = {
2793 .hwcg_reg = 0x2880,
2794 .hwcg_bit = 6,
2795 .halt_reg = 0x2fc8,
2796 .halt_bit = 8,
2797 .clkr = {
2798 .enable_reg = 0x2880,
2799 .enable_mask = BIT(4),
2800 .hw.init = &(struct clk_init_data){
2801 .name = "sdc4_h_clk",
2802 .ops = &clk_branch_ops,
2803 },
2804 },
2805 };
2806
2807 static struct clk_branch sdc5_h_clk = {
2808 .hwcg_reg = 0x28a0,
2809 .hwcg_bit = 6,
2810 .halt_reg = 0x2fc8,
2811 .halt_bit = 7,
2812 .clkr = {
2813 .enable_reg = 0x28a0,
2814 .enable_mask = BIT(4),
2815 .hw.init = &(struct clk_init_data){
2816 .name = "sdc5_h_clk",
2817 .ops = &clk_branch_ops,
2818 },
2819 },
2820 };
2821
2822 static struct clk_branch adm0_clk = {
2823 .halt_reg = 0x2fdc,
2824 .halt_check = BRANCH_HALT_VOTED,
2825 .halt_bit = 14,
2826 .clkr = {
2827 .enable_reg = 0x3080,
2828 .enable_mask = BIT(2),
2829 .hw.init = &(struct clk_init_data){
2830 .name = "adm0_clk",
2831 .ops = &clk_branch_ops,
2832 },
2833 },
2834 };
2835
2836 static struct clk_branch adm0_pbus_clk = {
2837 .hwcg_reg = 0x2208,
2838 .hwcg_bit = 6,
2839 .halt_reg = 0x2fdc,
2840 .halt_check = BRANCH_HALT_VOTED,
2841 .halt_bit = 13,
2842 .clkr = {
2843 .enable_reg = 0x3080,
2844 .enable_mask = BIT(3),
2845 .hw.init = &(struct clk_init_data){
2846 .name = "adm0_pbus_clk",
2847 .ops = &clk_branch_ops,
2848 },
2849 },
2850 };
2851
2852 static struct freq_tbl clk_tbl_ce3[] = {
2853 { 48000000, P_PLL8, 8 },
2854 { 100000000, P_PLL3, 12 },
2855 { 120000000, P_PLL3, 10 },
2856 { }
2857 };
2858
2859 static struct clk_rcg ce3_src = {
2860 .ns_reg = 0x36c0,
2861 .p = {
2862 .pre_div_shift = 3,
2863 .pre_div_width = 4,
2864 },
2865 .s = {
2866 .src_sel_shift = 0,
2867 .parent_map = gcc_pxo_pll8_pll3_map,
2868 },
2869 .freq_tbl = clk_tbl_ce3,
2870 .clkr = {
2871 .enable_reg = 0x36c0,
2872 .enable_mask = BIT(7),
2873 .hw.init = &(struct clk_init_data){
2874 .name = "ce3_src",
2875 .parent_names = gcc_pxo_pll8_pll3,
2876 .num_parents = 3,
2877 .ops = &clk_rcg_ops,
2878 .flags = CLK_SET_RATE_GATE,
2879 },
2880 },
2881 };
2882
2883 static struct clk_branch ce3_core_clk = {
2884 .halt_reg = 0x2fdc,
2885 .halt_bit = 5,
2886 .clkr = {
2887 .enable_reg = 0x36cc,
2888 .enable_mask = BIT(4),
2889 .hw.init = &(struct clk_init_data){
2890 .name = "ce3_core_clk",
2891 .parent_names = (const char *[]){ "ce3_src" },
2892 .num_parents = 1,
2893 .ops = &clk_branch_ops,
2894 .flags = CLK_SET_RATE_PARENT,
2895 },
2896 },
2897 };
2898
2899 static struct clk_branch ce3_h_clk = {
2900 .halt_reg = 0x2fc4,
2901 .halt_bit = 16,
2902 .clkr = {
2903 .enable_reg = 0x36c4,
2904 .enable_mask = BIT(4),
2905 .hw.init = &(struct clk_init_data){
2906 .name = "ce3_h_clk",
2907 .parent_names = (const char *[]){ "ce3_src" },
2908 .num_parents = 1,
2909 .ops = &clk_branch_ops,
2910 .flags = CLK_SET_RATE_PARENT,
2911 },
2912 },
2913 };
2914
2915 static const struct freq_tbl clk_tbl_sata_ref[] = {
2916 { 48000000, P_PLL8, 8, 0, 0 },
2917 { 100000000, P_PLL3, 12, 0, 0 },
2918 { }
2919 };
2920
2921 static struct clk_rcg sata_clk_src = {
2922 .ns_reg = 0x2c08,
2923 .p = {
2924 .pre_div_shift = 3,
2925 .pre_div_width = 4,
2926 },
2927 .s = {
2928 .src_sel_shift = 0,
2929 .parent_map = gcc_pxo_pll8_pll3_map,
2930 },
2931 .freq_tbl = clk_tbl_sata_ref,
2932 .clkr = {
2933 .enable_reg = 0x2c08,
2934 .enable_mask = BIT(7),
2935 .hw.init = &(struct clk_init_data){
2936 .name = "sata_clk_src",
2937 .parent_names = gcc_pxo_pll8_pll3,
2938 .num_parents = 3,
2939 .ops = &clk_rcg_ops,
2940 .flags = CLK_SET_RATE_GATE,
2941 },
2942 },
2943 };
2944
2945 static struct clk_branch sata_rxoob_clk = {
2946 .halt_reg = 0x2fdc,
2947 .halt_bit = 26,
2948 .clkr = {
2949 .enable_reg = 0x2c0c,
2950 .enable_mask = BIT(4),
2951 .hw.init = &(struct clk_init_data){
2952 .name = "sata_rxoob_clk",
2953 .parent_names = (const char *[]){ "sata_clk_src" },
2954 .num_parents = 1,
2955 .ops = &clk_branch_ops,
2956 .flags = CLK_SET_RATE_PARENT,
2957 },
2958 },
2959 };
2960
2961 static struct clk_branch sata_pmalive_clk = {
2962 .halt_reg = 0x2fdc,
2963 .halt_bit = 25,
2964 .clkr = {
2965 .enable_reg = 0x2c10,
2966 .enable_mask = BIT(4),
2967 .hw.init = &(struct clk_init_data){
2968 .name = "sata_pmalive_clk",
2969 .parent_names = (const char *[]){ "sata_clk_src" },
2970 .num_parents = 1,
2971 .ops = &clk_branch_ops,
2972 .flags = CLK_SET_RATE_PARENT,
2973 },
2974 },
2975 };
2976
2977 static struct clk_branch sata_phy_ref_clk = {
2978 .halt_reg = 0x2fdc,
2979 .halt_bit = 24,
2980 .clkr = {
2981 .enable_reg = 0x2c14,
2982 .enable_mask = BIT(4),
2983 .hw.init = &(struct clk_init_data){
2984 .name = "sata_phy_ref_clk",
2985 .parent_names = (const char *[]){ "pxo" },
2986 .num_parents = 1,
2987 .ops = &clk_branch_ops,
2988 },
2989 },
2990 };
2991
2992 static struct clk_branch sata_a_clk = {
2993 .halt_reg = 0x2fc0,
2994 .halt_bit = 12,
2995 .clkr = {
2996 .enable_reg = 0x2c20,
2997 .enable_mask = BIT(4),
2998 .hw.init = &(struct clk_init_data){
2999 .name = "sata_a_clk",
3000 .ops = &clk_branch_ops,
3001 },
3002 },
3003 };
3004
3005 static struct clk_branch sata_h_clk = {
3006 .halt_reg = 0x2fdc,
3007 .halt_bit = 27,
3008 .clkr = {
3009 .enable_reg = 0x2c00,
3010 .enable_mask = BIT(4),
3011 .hw.init = &(struct clk_init_data){
3012 .name = "sata_h_clk",
3013 .ops = &clk_branch_ops,
3014 },
3015 },
3016 };
3017
3018 static struct clk_branch sfab_sata_s_h_clk = {
3019 .halt_reg = 0x2fc4,
3020 .halt_bit = 14,
3021 .clkr = {
3022 .enable_reg = 0x2480,
3023 .enable_mask = BIT(4),
3024 .hw.init = &(struct clk_init_data){
3025 .name = "sfab_sata_s_h_clk",
3026 .ops = &clk_branch_ops,
3027 },
3028 },
3029 };
3030
3031 static struct clk_branch sata_phy_cfg_clk = {
3032 .halt_reg = 0x2fcc,
3033 .halt_bit = 12,
3034 .clkr = {
3035 .enable_reg = 0x2c40,
3036 .enable_mask = BIT(4),
3037 .hw.init = &(struct clk_init_data){
3038 .name = "sata_phy_cfg_clk",
3039 .ops = &clk_branch_ops,
3040 },
3041 },
3042 };
3043
3044 static struct clk_branch pcie_phy_ref_clk = {
3045 .halt_reg = 0x2fdc,
3046 .halt_bit = 29,
3047 .clkr = {
3048 .enable_reg = 0x22d0,
3049 .enable_mask = BIT(4),
3050 .hw.init = &(struct clk_init_data){
3051 .name = "pcie_phy_ref_clk",
3052 .ops = &clk_branch_ops,
3053 },
3054 },
3055 };
3056
3057 static struct clk_branch pcie_h_clk = {
3058 .halt_reg = 0x2fd4,
3059 .halt_bit = 8,
3060 .clkr = {
3061 .enable_reg = 0x22cc,
3062 .enable_mask = BIT(4),
3063 .hw.init = &(struct clk_init_data){
3064 .name = "pcie_h_clk",
3065 .ops = &clk_branch_ops,
3066 },
3067 },
3068 };
3069
3070 static struct clk_branch pcie_a_clk = {
3071 .halt_reg = 0x2fc0,
3072 .halt_bit = 13,
3073 .clkr = {
3074 .enable_reg = 0x22c0,
3075 .enable_mask = BIT(4),
3076 .hw.init = &(struct clk_init_data){
3077 .name = "pcie_a_clk",
3078 .ops = &clk_branch_ops,
3079 },
3080 },
3081 };
3082
3083 static struct clk_branch pmic_arb0_h_clk = {
3084 .halt_reg = 0x2fd8,
3085 .halt_check = BRANCH_HALT_VOTED,
3086 .halt_bit = 22,
3087 .clkr = {
3088 .enable_reg = 0x3080,
3089 .enable_mask = BIT(8),
3090 .hw.init = &(struct clk_init_data){
3091 .name = "pmic_arb0_h_clk",
3092 .ops = &clk_branch_ops,
3093 },
3094 },
3095 };
3096
3097 static struct clk_branch pmic_arb1_h_clk = {
3098 .halt_reg = 0x2fd8,
3099 .halt_check = BRANCH_HALT_VOTED,
3100 .halt_bit = 21,
3101 .clkr = {
3102 .enable_reg = 0x3080,
3103 .enable_mask = BIT(9),
3104 .hw.init = &(struct clk_init_data){
3105 .name = "pmic_arb1_h_clk",
3106 .ops = &clk_branch_ops,
3107 },
3108 },
3109 };
3110
3111 static struct clk_branch pmic_ssbi2_clk = {
3112 .halt_reg = 0x2fd8,
3113 .halt_check = BRANCH_HALT_VOTED,
3114 .halt_bit = 23,
3115 .clkr = {
3116 .enable_reg = 0x3080,
3117 .enable_mask = BIT(7),
3118 .hw.init = &(struct clk_init_data){
3119 .name = "pmic_ssbi2_clk",
3120 .ops = &clk_branch_ops,
3121 },
3122 },
3123 };
3124
3125 static struct clk_branch rpm_msg_ram_h_clk = {
3126 .hwcg_reg = 0x27e0,
3127 .hwcg_bit = 6,
3128 .halt_reg = 0x2fd8,
3129 .halt_check = BRANCH_HALT_VOTED,
3130 .halt_bit = 12,
3131 .clkr = {
3132 .enable_reg = 0x3080,
3133 .enable_mask = BIT(6),
3134 .hw.init = &(struct clk_init_data){
3135 .name = "rpm_msg_ram_h_clk",
3136 .ops = &clk_branch_ops,
3137 },
3138 },
3139 };
3140
3141 static struct clk_regmap *gcc_msm8960_clks[] = {
3142 [PLL3] = &pll3.clkr,
3143 [PLL4_VOTE] = &pll4_vote,
3144 [PLL8] = &pll8.clkr,
3145 [PLL8_VOTE] = &pll8_vote,
3146 [PLL14] = &pll14.clkr,
3147 [PLL14_VOTE] = &pll14_vote,
3148 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3149 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3150 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3151 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3152 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3153 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3154 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3155 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3156 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3157 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3158 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3159 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3160 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3161 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3162 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3163 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3164 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3165 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3166 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3167 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3168 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3169 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3170 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3171 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3172 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3173 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3174 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3175 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3176 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3177 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3178 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3179 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3180 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3181 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3182 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3183 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3184 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3185 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3186 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3187 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3188 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3189 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3190 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3191 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3192 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3193 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3194 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3195 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3196 [GP0_SRC] = &gp0_src.clkr,
3197 [GP0_CLK] = &gp0_clk.clkr,
3198 [GP1_SRC] = &gp1_src.clkr,
3199 [GP1_CLK] = &gp1_clk.clkr,
3200 [GP2_SRC] = &gp2_src.clkr,
3201 [GP2_CLK] = &gp2_clk.clkr,
3202 [PMEM_A_CLK] = &pmem_clk.clkr,
3203 [PRNG_SRC] = &prng_src.clkr,
3204 [PRNG_CLK] = &prng_clk.clkr,
3205 [SDC1_SRC] = &sdc1_src.clkr,
3206 [SDC1_CLK] = &sdc1_clk.clkr,
3207 [SDC2_SRC] = &sdc2_src.clkr,
3208 [SDC2_CLK] = &sdc2_clk.clkr,
3209 [SDC3_SRC] = &sdc3_src.clkr,
3210 [SDC3_CLK] = &sdc3_clk.clkr,
3211 [SDC4_SRC] = &sdc4_src.clkr,
3212 [SDC4_CLK] = &sdc4_clk.clkr,
3213 [SDC5_SRC] = &sdc5_src.clkr,
3214 [SDC5_CLK] = &sdc5_clk.clkr,
3215 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3216 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3217 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3218 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3219 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3220 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3221 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3222 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3223 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3224 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3225 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3226 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3227 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3228 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3229 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3230 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3231 [CE1_H_CLK] = &ce1_h_clk.clkr,
3232 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3233 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3234 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3235 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3236 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3237 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3238 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3239 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3240 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3241 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3242 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3243 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3244 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3245 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3246 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3247 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3248 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3249 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3250 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3251 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3252 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3253 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3254 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3255 [ADM0_CLK] = &adm0_clk.clkr,
3256 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3257 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3258 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3259 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3260 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3261 [PLL9] = &hfpll0.clkr,
3262 [PLL10] = &hfpll1.clkr,
3263 [PLL12] = &hfpll_l2.clkr,
3264 };
3265
3266 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3267 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3268 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3269 [QDSS_STM_RESET] = { 0x2060, 6 },
3270 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3271 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3272 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3273 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3274 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3275 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3276 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3277 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3278 [ADM0_C2_RESET] = { 0x220c, 4},
3279 [ADM0_C1_RESET] = { 0x220c, 3},
3280 [ADM0_C0_RESET] = { 0x220c, 2},
3281 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3282 [ADM0_RESET] = { 0x220c },
3283 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3284 [QDSS_POR_RESET] = { 0x2260, 4 },
3285 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3286 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3287 [QDSS_AXI_RESET] = { 0x2260, 1 },
3288 [QDSS_DBG_RESET] = { 0x2260 },
3289 [PCIE_A_RESET] = { 0x22c0, 7 },
3290 [PCIE_AUX_RESET] = { 0x22c8, 7 },
3291 [PCIE_H_RESET] = { 0x22d0, 7 },
3292 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3293 [SFAB_PCIE_S_RESET] = { 0x22d4 },
3294 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3295 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3296 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3297 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3298 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3299 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3300 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3301 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3302 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3303 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3304 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3305 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3306 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3307 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3308 [PPSS_PROC_RESET] = { 0x2594, 1 },
3309 [PPSS_RESET] = { 0x2594},
3310 [DMA_BAM_RESET] = { 0x25c0, 7 },
3311 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3312 [SLIMBUS_H_RESET] = { 0x2620, 7 },
3313 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3314 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3315 [TSIF_H_RESET] = { 0x2700, 7 },
3316 [CE1_H_RESET] = { 0x2720, 7 },
3317 [CE1_CORE_RESET] = { 0x2724, 7 },
3318 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3319 [CE2_H_RESET] = { 0x2740, 7 },
3320 [CE2_CORE_RESET] = { 0x2744, 7 },
3321 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3322 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3323 [RPM_PROC_RESET] = { 0x27c0, 7 },
3324 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3325 [SDC1_RESET] = { 0x2830 },
3326 [SDC2_RESET] = { 0x2850 },
3327 [SDC3_RESET] = { 0x2870 },
3328 [SDC4_RESET] = { 0x2890 },
3329 [SDC5_RESET] = { 0x28b0 },
3330 [DFAB_A2_RESET] = { 0x28c0, 7 },
3331 [USB_HS1_RESET] = { 0x2910 },
3332 [USB_HSIC_RESET] = { 0x2934 },
3333 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3334 [USB_FS1_RESET] = { 0x2974 },
3335 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3336 [USB_FS2_RESET] = { 0x2994 },
3337 [GSBI1_RESET] = { 0x29dc },
3338 [GSBI2_RESET] = { 0x29fc },
3339 [GSBI3_RESET] = { 0x2a1c },
3340 [GSBI4_RESET] = { 0x2a3c },
3341 [GSBI5_RESET] = { 0x2a5c },
3342 [GSBI6_RESET] = { 0x2a7c },
3343 [GSBI7_RESET] = { 0x2a9c },
3344 [GSBI8_RESET] = { 0x2abc },
3345 [GSBI9_RESET] = { 0x2adc },
3346 [GSBI10_RESET] = { 0x2afc },
3347 [GSBI11_RESET] = { 0x2b1c },
3348 [GSBI12_RESET] = { 0x2b3c },
3349 [SPDM_RESET] = { 0x2b6c },
3350 [TLMM_H_RESET] = { 0x2ba0, 7 },
3351 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3352 [MSS_SLP_RESET] = { 0x2c60, 7 },
3353 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3354 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3355 [MSS_RESET] = { 0x2c64 },
3356 [SATA_H_RESET] = { 0x2c80, 7 },
3357 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3358 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3359 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3360 [TSSC_RESET] = { 0x2ca0, 7 },
3361 [PDM_RESET] = { 0x2cc0, 12 },
3362 [MPM_H_RESET] = { 0x2da0, 7 },
3363 [MPM_RESET] = { 0x2da4 },
3364 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3365 [PRNG_RESET] = { 0x2e80, 12 },
3366 [RIVA_RESET] = { 0x35e0 },
3367 };
3368
3369 static struct clk_regmap *gcc_apq8064_clks[] = {
3370 [PLL3] = &pll3.clkr,
3371 [PLL4_VOTE] = &pll4_vote,
3372 [PLL8] = &pll8.clkr,
3373 [PLL8_VOTE] = &pll8_vote,
3374 [PLL14] = &pll14.clkr,
3375 [PLL14_VOTE] = &pll14_vote,
3376 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3377 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3378 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3379 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3380 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3381 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3382 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3383 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3384 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3385 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3386 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3387 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3388 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3389 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3390 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3391 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3392 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3393 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3394 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3395 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3396 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3397 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3398 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3399 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3400 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3401 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3402 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3403 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3404 [GP0_SRC] = &gp0_src.clkr,
3405 [GP0_CLK] = &gp0_clk.clkr,
3406 [GP1_SRC] = &gp1_src.clkr,
3407 [GP1_CLK] = &gp1_clk.clkr,
3408 [GP2_SRC] = &gp2_src.clkr,
3409 [GP2_CLK] = &gp2_clk.clkr,
3410 [PMEM_A_CLK] = &pmem_clk.clkr,
3411 [PRNG_SRC] = &prng_src.clkr,
3412 [PRNG_CLK] = &prng_clk.clkr,
3413 [SDC1_SRC] = &sdc1_src.clkr,
3414 [SDC1_CLK] = &sdc1_clk.clkr,
3415 [SDC2_SRC] = &sdc2_src.clkr,
3416 [SDC2_CLK] = &sdc2_clk.clkr,
3417 [SDC3_SRC] = &sdc3_src.clkr,
3418 [SDC3_CLK] = &sdc3_clk.clkr,
3419 [SDC4_SRC] = &sdc4_src.clkr,
3420 [SDC4_CLK] = &sdc4_clk.clkr,
3421 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3422 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3423 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3424 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3425 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3426 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3427 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3428 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3429 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3430 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3431 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3432 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3433 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3434 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3435 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3436 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3437 [SATA_H_CLK] = &sata_h_clk.clkr,
3438 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3439 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3440 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3441 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3442 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3443 [SATA_A_CLK] = &sata_a_clk.clkr,
3444 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3445 [CE3_SRC] = &ce3_src.clkr,
3446 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3447 [CE3_H_CLK] = &ce3_h_clk.clkr,
3448 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3449 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3450 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3451 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3452 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3453 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3454 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3455 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3456 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3457 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3458 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3459 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3460 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3461 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3462 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3463 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3464 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3465 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3466 [ADM0_CLK] = &adm0_clk.clkr,
3467 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3468 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3469 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3470 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3471 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3472 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3473 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3474 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3475 [PLL9] = &hfpll0.clkr,
3476 [PLL10] = &hfpll1.clkr,
3477 [PLL12] = &hfpll_l2.clkr,
3478 [PLL16] = &hfpll2.clkr,
3479 [PLL17] = &hfpll3.clkr,
3480 };
3481
3482 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3483 [QDSS_STM_RESET] = { 0x2060, 6 },
3484 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3485 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3486 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3487 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3488 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3489 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3490 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3491 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3492 [ADM0_C2_RESET] = { 0x220c, 4},
3493 [ADM0_C1_RESET] = { 0x220c, 3},
3494 [ADM0_C0_RESET] = { 0x220c, 2},
3495 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3496 [ADM0_RESET] = { 0x220c },
3497 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3498 [QDSS_POR_RESET] = { 0x2260, 4 },
3499 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3500 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3501 [QDSS_AXI_RESET] = { 0x2260, 1 },
3502 [QDSS_DBG_RESET] = { 0x2260 },
3503 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3504 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3505 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3506 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3507 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3508 [PCIE_POR_RESET] = { 0x22dc, 3 },
3509 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3510 [PCIE_ACLK_RESET] = { 0x22dc },
3511 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3512 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3513 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3514 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3515 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3516 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3517 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3518 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3519 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3520 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3521 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3522 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3523 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3524 [PPSS_PROC_RESET] = { 0x2594, 1 },
3525 [PPSS_RESET] = { 0x2594},
3526 [DMA_BAM_RESET] = { 0x25c0, 7 },
3527 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3528 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3529 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3530 [TSIF_H_RESET] = { 0x2700, 7 },
3531 [CE1_H_RESET] = { 0x2720, 7 },
3532 [CE1_CORE_RESET] = { 0x2724, 7 },
3533 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3534 [CE2_H_RESET] = { 0x2740, 7 },
3535 [CE2_CORE_RESET] = { 0x2744, 7 },
3536 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3537 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3538 [RPM_PROC_RESET] = { 0x27c0, 7 },
3539 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3540 [SDC1_RESET] = { 0x2830 },
3541 [SDC2_RESET] = { 0x2850 },
3542 [SDC3_RESET] = { 0x2870 },
3543 [SDC4_RESET] = { 0x2890 },
3544 [USB_HS1_RESET] = { 0x2910 },
3545 [USB_HSIC_RESET] = { 0x2934 },
3546 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3547 [USB_FS1_RESET] = { 0x2974 },
3548 [GSBI1_RESET] = { 0x29dc },
3549 [GSBI2_RESET] = { 0x29fc },
3550 [GSBI3_RESET] = { 0x2a1c },
3551 [GSBI4_RESET] = { 0x2a3c },
3552 [GSBI5_RESET] = { 0x2a5c },
3553 [GSBI6_RESET] = { 0x2a7c },
3554 [GSBI7_RESET] = { 0x2a9c },
3555 [SPDM_RESET] = { 0x2b6c },
3556 [TLMM_H_RESET] = { 0x2ba0, 7 },
3557 [SATA_SFAB_M_RESET] = { 0x2c18 },
3558 [SATA_RESET] = { 0x2c1c },
3559 [GSS_SLP_RESET] = { 0x2c60, 7 },
3560 [GSS_RESET] = { 0x2c64 },
3561 [TSSC_RESET] = { 0x2ca0, 7 },
3562 [PDM_RESET] = { 0x2cc0, 12 },
3563 [MPM_H_RESET] = { 0x2da0, 7 },
3564 [MPM_RESET] = { 0x2da4 },
3565 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3566 [PRNG_RESET] = { 0x2e80, 12 },
3567 [RIVA_RESET] = { 0x35e0 },
3568 [CE3_H_RESET] = { 0x36c4, 7 },
3569 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3570 [SFAB_CE3_S_RESET] = { 0x36c8 },
3571 [CE3_RESET] = { 0x36cc, 7 },
3572 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3573 [USB_HS3_RESET] = { 0x3710 },
3574 [USB_HS4_RESET] = { 0x3730 },
3575 };
3576
3577 static const struct regmap_config gcc_msm8960_regmap_config = {
3578 .reg_bits = 32,
3579 .reg_stride = 4,
3580 .val_bits = 32,
3581 .max_register = 0x3660,
3582 .fast_io = true,
3583 };
3584
3585 static const struct regmap_config gcc_apq8064_regmap_config = {
3586 .reg_bits = 32,
3587 .reg_stride = 4,
3588 .val_bits = 32,
3589 .max_register = 0x3880,
3590 .fast_io = true,
3591 };
3592
3593 static const struct qcom_cc_desc gcc_msm8960_desc = {
3594 .config = &gcc_msm8960_regmap_config,
3595 .clks = gcc_msm8960_clks,
3596 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3597 .resets = gcc_msm8960_resets,
3598 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3599 };
3600
3601 static const struct qcom_cc_desc gcc_apq8064_desc = {
3602 .config = &gcc_apq8064_regmap_config,
3603 .clks = gcc_apq8064_clks,
3604 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3605 .resets = gcc_apq8064_resets,
3606 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3607 };
3608
3609 static const struct of_device_id gcc_msm8960_match_table[] = {
3610 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3611 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3612 { }
3613 };
3614 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3615
3616 static int gcc_msm8960_probe(struct platform_device *pdev)
3617 {
3618 struct device *dev = &pdev->dev;
3619 const struct of_device_id *match;
3620 struct platform_device *tsens;
3621 int ret;
3622
3623 match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3624 if (!match)
3625 return -EINVAL;
3626
3627 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3628 if (ret)
3629 return ret;
3630
3631 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3632 if (ret)
3633 return ret;
3634
3635 ret = qcom_cc_probe(pdev, match->data);
3636 if (ret)
3637 return ret;
3638
3639 if (match->data == &gcc_apq8064_desc) {
3640 hfpll1.d = &hfpll1_8064_data;
3641 hfpll_l2.d = &hfpll_l2_8064_data;
3642 }
3643
3644 tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3645 NULL, 0);
3646 if (IS_ERR(tsens))
3647 return PTR_ERR(tsens);
3648
3649 platform_set_drvdata(pdev, tsens);
3650
3651 return 0;
3652 }
3653
3654 static int gcc_msm8960_remove(struct platform_device *pdev)
3655 {
3656 struct platform_device *tsens = platform_get_drvdata(pdev);
3657
3658 platform_device_unregister(tsens);
3659
3660 return 0;
3661 }
3662
3663 static struct platform_driver gcc_msm8960_driver = {
3664 .probe = gcc_msm8960_probe,
3665 .remove = gcc_msm8960_remove,
3666 .driver = {
3667 .name = "gcc-msm8960",
3668 .of_match_table = gcc_msm8960_match_table,
3669 },
3670 };
3671
3672 static int __init gcc_msm8960_init(void)
3673 {
3674 return platform_driver_register(&gcc_msm8960_driver);
3675 }
3676 core_initcall(gcc_msm8960_init);
3677
3678 static void __exit gcc_msm8960_exit(void)
3679 {
3680 platform_driver_unregister(&gcc_msm8960_driver);
3681 }
3682 module_exit(gcc_msm8960_exit);
3683
3684 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3685 MODULE_LICENSE("GPL v2");
3686 MODULE_ALIAS("platform:gcc-msm8960");