root/drivers/clk/qcom/clk-alpha-pll.c

DEFINITIONS

1. wait_for_pll
2. clk_alpha_pll_configure
3. clk_alpha_pll_hwfsm_enable
4. clk_alpha_pll_hwfsm_disable
5. pll_is_enabled
6. clk_alpha_pll_hwfsm_is_enabled
7. clk_alpha_pll_is_enabled
8. clk_alpha_pll_enable
9. clk_alpha_pll_disable
10. alpha_pll_calc_rate
11. alpha_pll_round_rate
12. alpha_pll_find_vco
13. clk_alpha_pll_recalc_rate
14. __clk_alpha_pll_update_latch
15. clk_alpha_pll_update_latch
16. __clk_alpha_pll_set_rate
17. clk_alpha_pll_set_rate
18. clk_alpha_pll_hwfsm_set_rate
19. clk_alpha_pll_round_rate
20. alpha_huayra_pll_calc_rate
21. alpha_huayra_pll_round_rate
22. alpha_pll_huayra_recalc_rate
23. alpha_pll_huayra_set_rate
24. alpha_pll_huayra_round_rate
25. trion_pll_is_enabled
26. clk_trion_pll_is_enabled
27. clk_trion_pll_enable
28. clk_trion_pll_disable
29. clk_trion_pll_recalc_rate
30. clk_trion_pll_round_rate
31. clk_alpha_pll_postdiv_recalc_rate
32. clk_alpha_pll_postdiv_round_rate
33. clk_alpha_pll_postdiv_round_ro_rate
34. clk_alpha_pll_postdiv_set_rate
35. clk_fabia_pll_configure
36. alpha_pll_fabia_enable
37. alpha_pll_fabia_disable
38. alpha_pll_fabia_recalc_rate
39. alpha_pll_fabia_set_rate
40. clk_alpha_pll_postdiv_fabia_recalc_rate
41. clk_trion_pll_postdiv_recalc_rate
42. clk_trion_pll_postdiv_round_rate
43. clk_trion_pll_postdiv_set_rate
44. clk_alpha_pll_postdiv_fabia_round_rate
45. clk_alpha_pll_postdiv_fabia_set_rate

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
   4  */
   5 
   6 #include <linux/kernel.h>
   7 #include <linux/export.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/regmap.h>
  10 #include <linux/delay.h>
  11 
  12 #include "clk-alpha-pll.h"
  13 #include "common.h"
  14 
  15 #define PLL_MODE(p)             ((p)->offset + 0x0)
  16 # define PLL_OUTCTRL            BIT(0)
  17 # define PLL_BYPASSNL           BIT(1)
  18 # define PLL_RESET_N            BIT(2)
  19 # define PLL_OFFLINE_REQ        BIT(7)
  20 # define PLL_LOCK_COUNT_SHIFT   8
  21 # define PLL_LOCK_COUNT_MASK    0x3f
  22 # define PLL_BIAS_COUNT_SHIFT   14
  23 # define PLL_BIAS_COUNT_MASK    0x3f
  24 # define PLL_VOTE_FSM_ENA       BIT(20)
  25 # define PLL_FSM_ENA            BIT(20)
  26 # define PLL_VOTE_FSM_RESET     BIT(21)
  27 # define PLL_UPDATE             BIT(22)
  28 # define PLL_UPDATE_BYPASS      BIT(23)
  29 # define PLL_OFFLINE_ACK        BIT(28)
  30 # define ALPHA_PLL_ACK_LATCH    BIT(29)
  31 # define PLL_ACTIVE_FLAG        BIT(30)
  32 # define PLL_LOCK_DET           BIT(31)
  33 
  34 #define PLL_L_VAL(p)            ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
  35 #define PLL_CAL_L_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
  36 #define PLL_ALPHA_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
  37 #define PLL_ALPHA_VAL_U(p)      ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
  38 
  39 #define PLL_USER_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
  40 # define PLL_POST_DIV_SHIFT     8
  41 # define PLL_POST_DIV_MASK(p)   GENMASK((p)->width, 0)
  42 # define PLL_ALPHA_EN           BIT(24)
  43 # define PLL_ALPHA_MODE         BIT(25)
  44 # define PLL_VCO_SHIFT          20
  45 # define PLL_VCO_MASK           0x3
  46 
  47 #define PLL_USER_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
  48 #define PLL_USER_CTL_U1(p)      ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
  49 
  50 #define PLL_CONFIG_CTL(p)       ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
  51 #define PLL_CONFIG_CTL_U(p)     ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
  52 #define PLL_CONFIG_CTL_U1(p)    ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
  53 #define PLL_TEST_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
  54 #define PLL_TEST_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
  55 #define PLL_STATUS(p)           ((p)->offset + (p)->regs[PLL_OFF_STATUS])
  56 #define PLL_OPMODE(p)           ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
  57 #define PLL_FRAC(p)             ((p)->offset + (p)->regs[PLL_OFF_FRAC])
  58 #define PLL_CAL_VAL(p)          ((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
  59 
  60 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
  61         [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
  62                 [PLL_OFF_L_VAL] = 0x04,
  63                 [PLL_OFF_ALPHA_VAL] = 0x08,
  64                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  65                 [PLL_OFF_USER_CTL] = 0x10,
  66                 [PLL_OFF_USER_CTL_U] = 0x14,
  67                 [PLL_OFF_CONFIG_CTL] = 0x18,
  68                 [PLL_OFF_TEST_CTL] = 0x1c,
  69                 [PLL_OFF_TEST_CTL_U] = 0x20,
  70                 [PLL_OFF_STATUS] = 0x24,
  71         },
  72         [CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
  73                 [PLL_OFF_L_VAL] = 0x04,
  74                 [PLL_OFF_ALPHA_VAL] = 0x08,
  75                 [PLL_OFF_USER_CTL] = 0x10,
  76                 [PLL_OFF_CONFIG_CTL] = 0x14,
  77                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  78                 [PLL_OFF_TEST_CTL] = 0x1c,
  79                 [PLL_OFF_TEST_CTL_U] = 0x20,
  80                 [PLL_OFF_STATUS] = 0x24,
  81         },
  82         [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
  83                 [PLL_OFF_L_VAL] = 0x04,
  84                 [PLL_OFF_ALPHA_VAL] = 0x08,
  85                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  86                 [PLL_OFF_USER_CTL] = 0x10,
  87                 [PLL_OFF_CONFIG_CTL] = 0x18,
  88                 [PLL_OFF_TEST_CTL] = 0x1c,
  89                 [PLL_OFF_STATUS] = 0x24,
  90         },
  91         [CLK_ALPHA_PLL_TYPE_FABIA] =  {
  92                 [PLL_OFF_L_VAL] = 0x04,
  93                 [PLL_OFF_USER_CTL] = 0x0c,
  94                 [PLL_OFF_USER_CTL_U] = 0x10,
  95                 [PLL_OFF_CONFIG_CTL] = 0x14,
  96                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  97                 [PLL_OFF_TEST_CTL] = 0x1c,
  98                 [PLL_OFF_TEST_CTL_U] = 0x20,
  99                 [PLL_OFF_STATUS] = 0x24,
 100                 [PLL_OFF_OPMODE] = 0x2c,
 101                 [PLL_OFF_FRAC] = 0x38,
 102         },
 103         [CLK_ALPHA_PLL_TYPE_TRION] = {
 104                 [PLL_OFF_L_VAL] = 0x04,
 105                 [PLL_OFF_CAL_L_VAL] = 0x08,
 106                 [PLL_OFF_USER_CTL] = 0x0c,
 107                 [PLL_OFF_USER_CTL_U] = 0x10,
 108                 [PLL_OFF_USER_CTL_U1] = 0x14,
 109                 [PLL_OFF_CONFIG_CTL] = 0x18,
 110                 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
 111                 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
 112                 [PLL_OFF_TEST_CTL] = 0x24,
 113                 [PLL_OFF_TEST_CTL_U] = 0x28,
 114                 [PLL_OFF_STATUS] = 0x30,
 115                 [PLL_OFF_OPMODE] = 0x38,
 116                 [PLL_OFF_ALPHA_VAL] = 0x40,
 117                 [PLL_OFF_CAL_VAL] = 0x44,
 118         },
 119 };
 120 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 121 
 122 /*
 123  * Even though 40 bits are present, use only 32 for ease of calculation.
 124  */
 125 #define ALPHA_REG_BITWIDTH      40
 126 #define ALPHA_REG_16BIT_WIDTH   16
 127 #define ALPHA_BITWIDTH          32U
 128 #define ALPHA_SHIFT(w)          min(w, ALPHA_BITWIDTH)
 129 
 130 #define PLL_HUAYRA_M_WIDTH              8
 131 #define PLL_HUAYRA_M_SHIFT              8
 132 #define PLL_HUAYRA_M_MASK               0xff
 133 #define PLL_HUAYRA_N_SHIFT              0
 134 #define PLL_HUAYRA_N_MASK               0xff
 135 #define PLL_HUAYRA_ALPHA_WIDTH          16
 136 
 137 #define FABIA_OPMODE_STANDBY    0x0
 138 #define FABIA_OPMODE_RUN        0x1
 139 
 140 #define FABIA_PLL_OUT_MASK      0x7
 141 #define FABIA_PLL_RATE_MARGIN   500
 142 
 143 #define TRION_PLL_STANDBY       0x0
 144 #define TRION_PLL_RUN           0x1
 145 #define TRION_PLL_OUT_MASK      0x7
 146 
 147 #define pll_alpha_width(p)                                      \
 148                 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
 149                                  ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
 150 
 151 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
 152 
 153 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
 154                                            struct clk_alpha_pll, clkr)
 155 
 156 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
 157                                            struct clk_alpha_pll_postdiv, clkr)
 158 
 159 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 160                         const char *action)
 161 {
 162         u32 val;
 163         int count;
 164         int ret;
 165         const char *name = clk_hw_get_name(&pll->clkr.hw);
 166 
 167         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 168         if (ret)
 169                 return ret;
 170 
 171         for (count = 100; count > 0; count--) {
 172                 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 173                 if (ret)
 174                         return ret;
 175                 if (inverse && !(val & mask))
 176                         return 0;
 177                 else if ((val & mask) == mask)
 178                         return 0;
 179 
 180                 udelay(1);
 181         }
 182 
 183         WARN(1, "%s failed to %s!\n", name, action);
 184         return -ETIMEDOUT;
 185 }
 186 
 187 #define wait_for_pll_enable_active(pll) \
 188         wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
 189 
 190 #define wait_for_pll_enable_lock(pll) \
 191         wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
 192 
 193 #define wait_for_pll_disable(pll) \
 194         wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
 195 
 196 #define wait_for_pll_offline(pll) \
 197         wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
 198 
 199 #define wait_for_pll_update(pll) \
 200         wait_for_pll(pll, PLL_UPDATE, 1, "update")
 201 
 202 #define wait_for_pll_update_ack_set(pll) \
 203         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
 204 
 205 #define wait_for_pll_update_ack_clear(pll) \
 206         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
 207 
 208 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 209                              const struct alpha_pll_config *config)
 210 {
 211         u32 val, mask;
 212 
 213         regmap_write(regmap, PLL_L_VAL(pll), config->l);
 214         regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
 215         regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
 216 
 217         if (pll_has_64bit_config(pll))
 218                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
 219                              config->config_ctl_hi_val);
 220 
 221         if (pll_alpha_width(pll) > 32)
 222                 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
 223 
 224         val = config->main_output_mask;
 225         val |= config->aux_output_mask;
 226         val |= config->aux2_output_mask;
 227         val |= config->early_output_mask;
 228         val |= config->pre_div_val;
 229         val |= config->post_div_val;
 230         val |= config->vco_val;
 231         val |= config->alpha_en_mask;
 232         val |= config->alpha_mode_mask;
 233 
 234         mask = config->main_output_mask;
 235         mask |= config->aux_output_mask;
 236         mask |= config->aux2_output_mask;
 237         mask |= config->early_output_mask;
 238         mask |= config->pre_div_mask;
 239         mask |= config->post_div_mask;
 240         mask |= config->vco_mask;
 241 
 242         regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
 243 
 244         if (pll->flags & SUPPORTS_FSM_MODE)
 245                 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
 246 }
 247 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
 248 
 249 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 250 {
 251         int ret;
 252         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 253         u32 val;
 254 
 255         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 256         if (ret)
 257                 return ret;
 258 
 259         val |= PLL_FSM_ENA;
 260 
 261         if (pll->flags & SUPPORTS_OFFLINE_REQ)
 262                 val &= ~PLL_OFFLINE_REQ;
 263 
 264         ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
 265         if (ret)
 266                 return ret;
 267 
 268         /* Make sure enable request goes through before waiting for update */
 269         mb();
 270 
 271         return wait_for_pll_enable_active(pll);
 272 }
 273 
 274 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 275 {
 276         int ret;
 277         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 278         u32 val;
 279 
 280         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 281         if (ret)
 282                 return;
 283 
 284         if (pll->flags & SUPPORTS_OFFLINE_REQ) {
 285                 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 286                                          PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
 287                 if (ret)
 288                         return;
 289 
 290                 ret = wait_for_pll_offline(pll);
 291                 if (ret)
 292                         return;
 293         }
 294 
 295         /* Disable hwfsm */
 296         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 297                                  PLL_FSM_ENA, 0);
 298         if (ret)
 299                 return;
 300 
 301         wait_for_pll_disable(pll);
 302 }
 303 
 304 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
 305 {
 306         int ret;
 307         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 308         u32 val;
 309 
 310         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 311         if (ret)
 312                 return ret;
 313 
 314         return !!(val & mask);
 315 }
 316 
 317 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
 318 {
 319         return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
 320 }
 321 
 322 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
 323 {
 324         return pll_is_enabled(hw, PLL_LOCK_DET);
 325 }
 326 
 327 static int clk_alpha_pll_enable(struct clk_hw *hw)
 328 {
 329         int ret;
 330         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 331         u32 val, mask;
 332 
 333         mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
 334         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 335         if (ret)
 336                 return ret;
 337 
 338         /* If in FSM mode, just vote for it */
 339         if (val & PLL_VOTE_FSM_ENA) {
 340                 ret = clk_enable_regmap(hw);
 341                 if (ret)
 342                         return ret;
 343                 return wait_for_pll_enable_active(pll);
 344         }
 345 
 346         /* Skip if already enabled */
 347         if ((val & mask) == mask)
 348                 return 0;
 349 
 350         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 351                                  PLL_BYPASSNL, PLL_BYPASSNL);
 352         if (ret)
 353                 return ret;
 354 
 355         /*
 356          * H/W requires a 5us delay between disabling the bypass and
 357          * de-asserting the reset.
 358          */
 359         mb();
 360         udelay(5);
 361 
 362         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 363                                  PLL_RESET_N, PLL_RESET_N);
 364         if (ret)
 365                 return ret;
 366 
 367         ret = wait_for_pll_enable_lock(pll);
 368         if (ret)
 369                 return ret;
 370 
 371         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 372                                  PLL_OUTCTRL, PLL_OUTCTRL);
 373 
 374         /* Ensure that the write above goes through before returning. */
 375         mb();
 376         return ret;
 377 }
 378 
 379 static void clk_alpha_pll_disable(struct clk_hw *hw)
 380 {
 381         int ret;
 382         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 383         u32 val, mask;
 384 
 385         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 386         if (ret)
 387                 return;
 388 
 389         /* If in FSM mode, just unvote it */
 390         if (val & PLL_VOTE_FSM_ENA) {
 391                 clk_disable_regmap(hw);
 392                 return;
 393         }
 394 
 395         mask = PLL_OUTCTRL;
 396         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 397 
 398         /* Delay of 2 output clock ticks required until output is disabled */
 399         mb();
 400         udelay(1);
 401 
 402         mask = PLL_RESET_N | PLL_BYPASSNL;
 403         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 404 }
 405 
 406 static unsigned long
 407 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
 408 {
 409         return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
 410 }
 411 
 412 static unsigned long
 413 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
 414                      u32 alpha_width)
 415 {
 416         u64 remainder;
 417         u64 quotient;
 418 
 419         quotient = rate;
 420         remainder = do_div(quotient, prate);
 421         *l = quotient;
 422 
 423         if (!remainder) {
 424                 *a = 0;
 425                 return rate;
 426         }
 427 
 428         /* Upper ALPHA_BITWIDTH bits of Alpha */
 429         quotient = remainder << ALPHA_SHIFT(alpha_width);
 430 
 431         remainder = do_div(quotient, prate);
 432 
 433         if (remainder)
 434                 quotient++;
 435 
 436         *a = quotient;
 437         return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
 438 }
 439 
 440 static const struct pll_vco *
 441 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
 442 {
 443         const struct pll_vco *v = pll->vco_table;
 444         const struct pll_vco *end = v + pll->num_vco;
 445 
 446         for (; v < end; v++)
 447                 if (rate >= v->min_freq && rate <= v->max_freq)
 448                         return v;
 449 
 450         return NULL;
 451 }
 452 
 453 static unsigned long
 454 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 455 {
 456         u32 l, low, high, ctl;
 457         u64 a = 0, prate = parent_rate;
 458         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 459         u32 alpha_width = pll_alpha_width(pll);
 460 
 461         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 462 
 463         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 464         if (ctl & PLL_ALPHA_EN) {
 465                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
 466                 if (alpha_width > 32) {
 467                         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
 468                                     &high);
 469                         a = (u64)high << 32 | low;
 470                 } else {
 471                         a = low & GENMASK(alpha_width - 1, 0);
 472                 }
 473 
 474                 if (alpha_width > ALPHA_BITWIDTH)
 475                         a >>= alpha_width - ALPHA_BITWIDTH;
 476         }
 477 
 478         return alpha_pll_calc_rate(prate, l, a, alpha_width);
 479 }
 480 
 481 
 482 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
 483 {
 484         int ret;
 485         u32 mode;
 486 
 487         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
 488 
 489         /* Latch the input to the PLL */
 490         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
 491                            PLL_UPDATE);
 492 
 493         /* Wait for 2 reference cycle before checking ACK bit */
 494         udelay(1);
 495 
 496         /*
 497          * PLL will latch the new L, Alpha and freq control word.
 498          * PLL will respond by raising PLL_ACK_LATCH output when new programming
 499          * has been latched in and PLL is being updated. When
 500          * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
 501          * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
 502          */
 503         if (mode & PLL_UPDATE_BYPASS) {
 504                 ret = wait_for_pll_update_ack_set(pll);
 505                 if (ret)
 506                         return ret;
 507 
 508                 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
 509         } else {
 510                 ret = wait_for_pll_update(pll);
 511                 if (ret)
 512                         return ret;
 513         }
 514 
 515         ret = wait_for_pll_update_ack_clear(pll);
 516         if (ret)
 517                 return ret;
 518 
 519         /* Wait for PLL output to stabilize */
 520         udelay(10);
 521 
 522         return 0;
 523 }
 524 
 525 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
 526                                       int (*is_enabled)(struct clk_hw *))
 527 {
 528         if (!is_enabled(&pll->clkr.hw) ||
 529             !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
 530                 return 0;
 531 
 532         return __clk_alpha_pll_update_latch(pll);
 533 }
 534 
 535 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 536                                     unsigned long prate,
 537                                     int (*is_enabled)(struct clk_hw *))
 538 {
 539         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 540         const struct pll_vco *vco;
 541         u32 l, alpha_width = pll_alpha_width(pll);
 542         u64 a;
 543 
 544         rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
 545         vco = alpha_pll_find_vco(pll, rate);
 546         if (pll->vco_table && !vco) {
 547                 pr_err("alpha pll not in a valid vco range\n");
 548                 return -EINVAL;
 549         }
 550 
 551         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 552 
 553         if (alpha_width > ALPHA_BITWIDTH)
 554                 a <<= alpha_width - ALPHA_BITWIDTH;
 555 
 556         if (alpha_width > 32)
 557                 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
 558 
 559         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 560 
 561         if (vco) {
 562                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 563                                    PLL_VCO_MASK << PLL_VCO_SHIFT,
 564                                    vco->val << PLL_VCO_SHIFT);
 565         }
 566 
 567         regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 568                            PLL_ALPHA_EN, PLL_ALPHA_EN);
 569 
 570         return clk_alpha_pll_update_latch(pll, is_enabled);
 571 }
 572 
 573 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 574                                   unsigned long prate)
 575 {
 576         return __clk_alpha_pll_set_rate(hw, rate, prate,
 577                                         clk_alpha_pll_is_enabled);
 578 }
 579 
 580 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
 581                                         unsigned long prate)
 582 {
 583         return __clk_alpha_pll_set_rate(hw, rate, prate,
 584                                         clk_alpha_pll_hwfsm_is_enabled);
 585 }
 586 
 587 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 588                                      unsigned long *prate)
 589 {
 590         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 591         u32 l, alpha_width = pll_alpha_width(pll);
 592         u64 a;
 593         unsigned long min_freq, max_freq;
 594 
 595         rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
 596         if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
 597                 return rate;
 598 
 599         min_freq = pll->vco_table[0].min_freq;
 600         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 601 
 602         return clamp(rate, min_freq, max_freq);
 603 }
 604 
 605 static unsigned long
 606 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
 607 {
 608         /*
 609          * a contains 16 bit alpha_val in two’s compliment number in the range
 610          * of [-0.5, 0.5).
 611          */
 612         if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 613                 l -= 1;
 614 
 615         return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
 616 }
 617 
 618 static unsigned long
 619 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
 620                             u32 *l, u32 *a)
 621 {
 622         u64 remainder;
 623         u64 quotient;
 624 
 625         quotient = rate;
 626         remainder = do_div(quotient, prate);
 627         *l = quotient;
 628 
 629         if (!remainder) {
 630                 *a = 0;
 631                 return rate;
 632         }
 633 
 634         quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
 635         remainder = do_div(quotient, prate);
 636 
 637         if (remainder)
 638                 quotient++;
 639 
 640         /*
 641          * alpha_val should be in two’s compliment number in the range
 642          * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
 643          * since alpha value will be subtracted in this case.
 644          */
 645         if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 646                 *l += 1;
 647 
 648         *a = quotient;
 649         return alpha_huayra_pll_calc_rate(prate, *l, *a);
 650 }
 651 
 652 static unsigned long
 653 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 654 {
 655         u64 rate = parent_rate, tmp;
 656         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 657         u32 l, alpha = 0, ctl, alpha_m, alpha_n;
 658 
 659         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 660         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 661 
 662         if (ctl & PLL_ALPHA_EN) {
 663                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
 664                 /*
 665                  * Depending upon alpha_mode, it can be treated as M/N value or
 666                  * as a two’s compliment number. When alpha_mode=1,
 667                  * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
 668                  *
 669                  *              Fout=FIN*(L+(M/N))
 670                  *
 671                  * M is a signed number (-128 to 127) and N is unsigned
 672                  * (0 to 255). M/N has to be within +/-0.5.
 673                  *
 674                  * When alpha_mode=0, it is a two’s compliment number in the
 675                  * range [-0.5, 0.5).
 676                  *
 677                  *              Fout=FIN*(L+(alpha_val)/2^16)
 678                  *
 679                  * where alpha_val is two’s compliment number.
 680                  */
 681                 if (!(ctl & PLL_ALPHA_MODE))
 682                         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 683 
 684                 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
 685                 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
 686 
 687                 rate *= l;
 688                 tmp = parent_rate;
 689                 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
 690                         alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
 691                         tmp *= alpha_m;
 692                         do_div(tmp, alpha_n);
 693                         rate -= tmp;
 694                 } else {
 695                         tmp *= alpha_m;
 696                         do_div(tmp, alpha_n);
 697                         rate += tmp;
 698                 }
 699 
 700                 return rate;
 701         }
 702 
 703         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 704 }
 705 
 706 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
 707                                      unsigned long prate)
 708 {
 709         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 710         u32 l, a, ctl, cur_alpha = 0;
 711 
 712         rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
 713 
 714         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 715 
 716         if (ctl & PLL_ALPHA_EN)
 717                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
 718 
 719         /*
 720          * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
 721          * without having to go through the power on sequence.
 722          */
 723         if (clk_alpha_pll_is_enabled(hw)) {
 724                 if (cur_alpha != a) {
 725                         pr_err("clock needs to be gated %s\n",
 726                                clk_hw_get_name(hw));
 727                         return -EBUSY;
 728                 }
 729 
 730                 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 731                 /* Ensure that the write above goes to detect L val change. */
 732                 mb();
 733                 return wait_for_pll_enable_lock(pll);
 734         }
 735 
 736         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 737         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 738 
 739         if (a == 0)
 740                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 741                                    PLL_ALPHA_EN, 0x0);
 742         else
 743                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 744                                    PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
 745 
 746         return 0;
 747 }
 748 
 749 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
 750                                         unsigned long *prate)
 751 {
 752         u32 l, a;
 753 
 754         return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
 755 }
 756 
 757 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
 758                                 struct regmap *regmap)
 759 {
 760         u32 mode_regval, opmode_regval;
 761         int ret;
 762 
 763         ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
 764         ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
 765         if (ret)
 766                 return 0;
 767 
 768         return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
 769 }
 770 
 771 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
 772 {
 773         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 774 
 775         return trion_pll_is_enabled(pll, pll->clkr.regmap);
 776 }
 777 
 778 static int clk_trion_pll_enable(struct clk_hw *hw)
 779 {
 780         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 781         struct regmap *regmap = pll->clkr.regmap;
 782         u32 val;
 783         int ret;
 784 
 785         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 786         if (ret)
 787                 return ret;
 788 
 789         /* If in FSM mode, just vote for it */
 790         if (val & PLL_VOTE_FSM_ENA) {
 791                 ret = clk_enable_regmap(hw);
 792                 if (ret)
 793                         return ret;
 794                 return wait_for_pll_enable_active(pll);
 795         }
 796 
 797         /* Set operation mode to RUN */
 798         regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
 799 
 800         ret = wait_for_pll_enable_lock(pll);
 801         if (ret)
 802                 return ret;
 803 
 804         /* Enable the PLL outputs */
 805         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 806                                  TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
 807         if (ret)
 808                 return ret;
 809 
 810         /* Enable the global PLL outputs */
 811         return regmap_update_bits(regmap, PLL_MODE(pll),
 812                                  PLL_OUTCTRL, PLL_OUTCTRL);
 813 }
 814 
 815 static void clk_trion_pll_disable(struct clk_hw *hw)
 816 {
 817         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 818         struct regmap *regmap = pll->clkr.regmap;
 819         u32 val;
 820         int ret;
 821 
 822         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 823         if (ret)
 824                 return;
 825 
 826         /* If in FSM mode, just unvote it */
 827         if (val & PLL_VOTE_FSM_ENA) {
 828                 clk_disable_regmap(hw);
 829                 return;
 830         }
 831 
 832         /* Disable the global PLL output */
 833         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
 834         if (ret)
 835                 return;
 836 
 837         /* Disable the PLL outputs */
 838         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 839                                  TRION_PLL_OUT_MASK, 0);
 840         if (ret)
 841                 return;
 842 
 843         /* Place the PLL mode in STANDBY */
 844         regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
 845         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
 846 }
 847 
 848 static unsigned long
 849 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 850 {
 851         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 852         struct regmap *regmap = pll->clkr.regmap;
 853         u32 l, frac;
 854         u64 prate = parent_rate;
 855 
 856         regmap_read(regmap, PLL_L_VAL(pll), &l);
 857         regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
 858 
 859         return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
 860 }
 861 
 862 static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 863                                      unsigned long *prate)
 864 {
 865         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 866         unsigned long min_freq, max_freq;
 867         u32 l;
 868         u64 a;
 869 
 870         rate = alpha_pll_round_rate(rate, *prate,
 871                                     &l, &a, ALPHA_REG_16BIT_WIDTH);
 872         if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
 873                 return rate;
 874 
 875         min_freq = pll->vco_table[0].min_freq;
 876         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 877 
 878         return clamp(rate, min_freq, max_freq);
 879 }
 880 
 881 const struct clk_ops clk_alpha_pll_ops = {
 882         .enable = clk_alpha_pll_enable,
 883         .disable = clk_alpha_pll_disable,
 884         .is_enabled = clk_alpha_pll_is_enabled,
 885         .recalc_rate = clk_alpha_pll_recalc_rate,
 886         .round_rate = clk_alpha_pll_round_rate,
 887         .set_rate = clk_alpha_pll_set_rate,
 888 };
 889 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
 890 
 891 const struct clk_ops clk_alpha_pll_huayra_ops = {
 892         .enable = clk_alpha_pll_enable,
 893         .disable = clk_alpha_pll_disable,
 894         .is_enabled = clk_alpha_pll_is_enabled,
 895         .recalc_rate = alpha_pll_huayra_recalc_rate,
 896         .round_rate = alpha_pll_huayra_round_rate,
 897         .set_rate = alpha_pll_huayra_set_rate,
 898 };
 899 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
 900 
 901 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
 902         .enable = clk_alpha_pll_hwfsm_enable,
 903         .disable = clk_alpha_pll_hwfsm_disable,
 904         .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
 905         .recalc_rate = clk_alpha_pll_recalc_rate,
 906         .round_rate = clk_alpha_pll_round_rate,
 907         .set_rate = clk_alpha_pll_hwfsm_set_rate,
 908 };
 909 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
 910 
 911 const struct clk_ops clk_trion_fixed_pll_ops = {
 912         .enable = clk_trion_pll_enable,
 913         .disable = clk_trion_pll_disable,
 914         .is_enabled = clk_trion_pll_is_enabled,
 915         .recalc_rate = clk_trion_pll_recalc_rate,
 916         .round_rate = clk_trion_pll_round_rate,
 917 };
 918 EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
 919 
 920 static unsigned long
 921 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 922 {
 923         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 924         u32 ctl;
 925 
 926         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 927 
 928         ctl >>= PLL_POST_DIV_SHIFT;
 929         ctl &= PLL_POST_DIV_MASK(pll);
 930 
 931         return parent_rate >> fls(ctl);
 932 }
 933 
 934 static const struct clk_div_table clk_alpha_div_table[] = {
 935         { 0x0, 1 },
 936         { 0x1, 2 },
 937         { 0x3, 4 },
 938         { 0x7, 8 },
 939         { 0xf, 16 },
 940         { }
 941 };
 942 
 943 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
 944         { 0x0, 1 },
 945         { 0x1, 2 },
 946         { 0x3, 4 },
 947         { }
 948 };
 949 
 950 static long
 951 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
 952                                  unsigned long *prate)
 953 {
 954         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 955         const struct clk_div_table *table;
 956 
 957         if (pll->width == 2)
 958                 table = clk_alpha_2bit_div_table;
 959         else
 960                 table = clk_alpha_div_table;
 961 
 962         return divider_round_rate(hw, rate, prate, table,
 963                                   pll->width, CLK_DIVIDER_POWER_OF_TWO);
 964 }
 965 
 966 static long
 967 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
 968                                     unsigned long *prate)
 969 {
 970         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 971         u32 ctl, div;
 972 
 973         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 974 
 975         ctl >>= PLL_POST_DIV_SHIFT;
 976         ctl &= BIT(pll->width) - 1;
 977         div = 1 << fls(ctl);
 978 
 979         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
 980                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
 981 
 982         return DIV_ROUND_UP_ULL((u64)*prate, div);
 983 }
 984 
 985 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 986                                           unsigned long parent_rate)
 987 {
 988         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 989         int div;
 990 
 991         /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
 992         div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
 993 
 994         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 995                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
 996                                   div << PLL_POST_DIV_SHIFT);
 997 }
 998 
 999 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1000         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1001         .round_rate = clk_alpha_pll_postdiv_round_rate,
1002         .set_rate = clk_alpha_pll_postdiv_set_rate,
1003 };
1004 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1005 
1006 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1007         .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1008         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1009 };
1010 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1011 
1012 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1013                              const struct alpha_pll_config *config)
1014 {
1015         u32 val, mask;
1016 
1017         if (config->l)
1018                 regmap_write(regmap, PLL_L_VAL(pll), config->l);
1019 
1020         if (config->alpha)
1021                 regmap_write(regmap, PLL_FRAC(pll), config->alpha);
1022 
1023         if (config->config_ctl_val)
1024                 regmap_write(regmap, PLL_CONFIG_CTL(pll),
1025                                                 config->config_ctl_val);
1026 
1027         if (config->post_div_mask) {
1028                 mask = config->post_div_mask;
1029                 val = config->post_div_val;
1030                 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1031         }
1032 
1033         regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1034                                                         PLL_UPDATE_BYPASS);
1035 
1036         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1037 }
1038 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1039 
1040 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1041 {
1042         int ret;
1043         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1044         u32 val, opmode_val;
1045         struct regmap *regmap = pll->clkr.regmap;
1046 
1047         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1048         if (ret)
1049                 return ret;
1050 
1051         /* If in FSM mode, just vote for it */
1052         if (val & PLL_VOTE_FSM_ENA) {
1053                 ret = clk_enable_regmap(hw);
1054                 if (ret)
1055                         return ret;
1056                 return wait_for_pll_enable_active(pll);
1057         }
1058 
1059         ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1060         if (ret)
1061                 return ret;
1062 
1063         /* Skip If PLL is already running */
1064         if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
1065                 return 0;
1066 
1067         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1068         if (ret)
1069                 return ret;
1070 
1071         ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
1072         if (ret)
1073                 return ret;
1074 
1075         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1076                                  PLL_RESET_N);
1077         if (ret)
1078                 return ret;
1079 
1080         ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
1081         if (ret)
1082                 return ret;
1083 
1084         ret = wait_for_pll_enable_lock(pll);
1085         if (ret)
1086                 return ret;
1087 
1088         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1089                                  FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
1090         if (ret)
1091                 return ret;
1092 
1093         return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1094                                  PLL_OUTCTRL);
1095 }
1096 
1097 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1098 {
1099         int ret;
1100         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1101         u32 val;
1102         struct regmap *regmap = pll->clkr.regmap;
1103 
1104         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1105         if (ret)
1106                 return;
1107 
1108         /* If in FSM mode, just unvote it */
1109         if (val & PLL_FSM_ENA) {
1110                 clk_disable_regmap(hw);
1111                 return;
1112         }
1113 
1114         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1115         if (ret)
1116                 return;
1117 
1118         /* Disable main outputs */
1119         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
1120                                  0);
1121         if (ret)
1122                 return;
1123 
1124         /* Place the PLL in STANDBY */
1125         regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
1126 }
1127 
1128 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1129                                                 unsigned long parent_rate)
1130 {
1131         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1132         u32 l, frac, alpha_width = pll_alpha_width(pll);
1133 
1134         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1135         regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1136 
1137         return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1138 }
1139 
1140 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1141                                                 unsigned long prate)
1142 {
1143         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1144         u32 val, l, alpha_width = pll_alpha_width(pll);
1145         u64 a;
1146         unsigned long rrate;
1147         int ret = 0;
1148 
1149         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1150         if (ret)
1151                 return ret;
1152 
1153         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1154 
1155         /*
1156          * Due to limited number of bits for fractional rate programming, the
1157          * rounded up rate could be marginally higher than the requested rate.
1158          */
1159         if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
1160                 pr_err("Call set rate on the PLL with rounded rates!\n");
1161                 return -EINVAL;
1162         }
1163 
1164         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1165         regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1166 
1167         return __clk_alpha_pll_update_latch(pll);
1168 }
1169 
1170 const struct clk_ops clk_alpha_pll_fabia_ops = {
1171         .enable = alpha_pll_fabia_enable,
1172         .disable = alpha_pll_fabia_disable,
1173         .is_enabled = clk_alpha_pll_is_enabled,
1174         .set_rate = alpha_pll_fabia_set_rate,
1175         .recalc_rate = alpha_pll_fabia_recalc_rate,
1176         .round_rate = clk_alpha_pll_round_rate,
1177 };
1178 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1179 
1180 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1181         .enable = alpha_pll_fabia_enable,
1182         .disable = alpha_pll_fabia_disable,
1183         .is_enabled = clk_alpha_pll_is_enabled,
1184         .recalc_rate = alpha_pll_fabia_recalc_rate,
1185         .round_rate = clk_alpha_pll_round_rate,
1186 };
1187 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1188 
1189 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1190                                         unsigned long parent_rate)
1191 {
1192         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1193         u32 i, div = 1, val;
1194         int ret;
1195 
1196         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1197         if (ret)
1198                 return ret;
1199 
1200         val >>= pll->post_div_shift;
1201         val &= BIT(pll->width) - 1;
1202 
1203         for (i = 0; i < pll->num_post_div; i++) {
1204                 if (pll->post_div_table[i].val == val) {
1205                         div = pll->post_div_table[i].div;
1206                         break;
1207                 }
1208         }
1209 
1210         return (parent_rate / div);
1211 }
1212 
1213 static unsigned long
1214 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1215 {
1216         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1217         struct regmap *regmap = pll->clkr.regmap;
1218         u32 i, div = 1, val;
1219 
1220         regmap_read(regmap, PLL_USER_CTL(pll), &val);
1221 
1222         val >>= pll->post_div_shift;
1223         val &= PLL_POST_DIV_MASK(pll);
1224 
1225         for (i = 0; i < pll->num_post_div; i++) {
1226                 if (pll->post_div_table[i].val == val) {
1227                         div = pll->post_div_table[i].div;
1228                         break;
1229                 }
1230         }
1231 
1232         return (parent_rate / div);
1233 }
1234 
1235 static long
1236 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1237                                  unsigned long *prate)
1238 {
1239         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1240 
1241         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1242                                   pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1243 };
1244 
1245 static int
1246 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1247                                unsigned long parent_rate)
1248 {
1249         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1250         struct regmap *regmap = pll->clkr.regmap;
1251         int i, val = 0, div;
1252 
1253         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1254         for (i = 0; i < pll->num_post_div; i++) {
1255                 if (pll->post_div_table[i].div == div) {
1256                         val = pll->post_div_table[i].val;
1257                         break;
1258                 }
1259         }
1260 
1261         return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1262                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1263                                   val << PLL_POST_DIV_SHIFT);
1264 }
1265 
1266 const struct clk_ops clk_trion_pll_postdiv_ops = {
1267         .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1268         .round_rate = clk_trion_pll_postdiv_round_rate,
1269         .set_rate = clk_trion_pll_postdiv_set_rate,
1270 };
1271 EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
1272 
1273 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1274                                 unsigned long rate, unsigned long *prate)
1275 {
1276         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1277 
1278         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1279                                 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1280 }
1281 
1282 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1283                                 unsigned long rate, unsigned long parent_rate)
1284 {
1285         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1286         int i, val = 0, div, ret;
1287 
1288         /*
1289          * If the PLL is in FSM mode, then treat set_rate callback as a
1290          * no-operation.
1291          */
1292         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1293         if (ret)
1294                 return ret;
1295 
1296         if (val & PLL_VOTE_FSM_ENA)
1297                 return 0;
1298 
1299         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1300         for (i = 0; i < pll->num_post_div; i++) {
1301                 if (pll->post_div_table[i].div == div) {
1302                         val = pll->post_div_table[i].val;
1303                         break;
1304                 }
1305         }
1306 
1307         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1308                                 (BIT(pll->width) - 1) << pll->post_div_shift,
1309                                 val << pll->post_div_shift);
1310 }
1311 
1312 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1313         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1314         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1315         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1316 };
1317 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);