This source file includes following definitions.
- gcc_sdm845_probe
- gcc_sdm845_init
- gcc_sdm845_exit
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5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
18
19 #include "common.h"
20 #include "clk-regmap.h"
21 #include "clk-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
24 #include "clk-alpha-pll.h"
25 #include "gdsc.h"
26 #include "reset.h"
27
28 enum {
29 P_BI_TCXO,
30 P_AUD_REF_CLK,
31 P_CORE_BI_PLL_TEST_SE,
32 P_GPLL0_OUT_EVEN,
33 P_GPLL0_OUT_MAIN,
34 P_GPLL4_OUT_MAIN,
35 P_SLEEP_CLK,
36 };
37
38 static const struct parent_map gcc_parent_map_0[] = {
39 { P_BI_TCXO, 0 },
40 { P_GPLL0_OUT_MAIN, 1 },
41 { P_GPLL0_OUT_EVEN, 6 },
42 { P_CORE_BI_PLL_TEST_SE, 7 },
43 };
44
45 static const char * const gcc_parent_names_0[] = {
46 "bi_tcxo",
47 "gpll0",
48 "gpll0_out_even",
49 "core_bi_pll_test_se",
50 };
51
52 static const struct parent_map gcc_parent_map_1[] = {
53 { P_BI_TCXO, 0 },
54 { P_GPLL0_OUT_MAIN, 1 },
55 { P_SLEEP_CLK, 5 },
56 { P_GPLL0_OUT_EVEN, 6 },
57 { P_CORE_BI_PLL_TEST_SE, 7 },
58 };
59
60 static const char * const gcc_parent_names_1[] = {
61 "bi_tcxo",
62 "gpll0",
63 "core_pi_sleep_clk",
64 "gpll0_out_even",
65 "core_bi_pll_test_se",
66 };
67
68 static const struct parent_map gcc_parent_map_2[] = {
69 { P_BI_TCXO, 0 },
70 { P_SLEEP_CLK, 5 },
71 { P_CORE_BI_PLL_TEST_SE, 7 },
72 };
73
74 static const char * const gcc_parent_names_2[] = {
75 "bi_tcxo",
76 "core_pi_sleep_clk",
77 "core_bi_pll_test_se",
78 };
79
80 static const struct parent_map gcc_parent_map_3[] = {
81 { P_BI_TCXO, 0 },
82 { P_GPLL0_OUT_MAIN, 1 },
83 { P_CORE_BI_PLL_TEST_SE, 7 },
84 };
85
86 static const char * const gcc_parent_names_3[] = {
87 "bi_tcxo",
88 "gpll0",
89 "core_bi_pll_test_se",
90 };
91
92 static const struct parent_map gcc_parent_map_4[] = {
93 { P_BI_TCXO, 0 },
94 { P_CORE_BI_PLL_TEST_SE, 7 },
95 };
96
97 static const char * const gcc_parent_names_4[] = {
98 "bi_tcxo",
99 "core_bi_pll_test_se",
100 };
101
102 static const struct parent_map gcc_parent_map_6[] = {
103 { P_BI_TCXO, 0 },
104 { P_GPLL0_OUT_MAIN, 1 },
105 { P_AUD_REF_CLK, 2 },
106 { P_GPLL0_OUT_EVEN, 6 },
107 { P_CORE_BI_PLL_TEST_SE, 7 },
108 };
109
110 static const char * const gcc_parent_names_6[] = {
111 "bi_tcxo",
112 "gpll0",
113 "aud_ref_clk",
114 "gpll0_out_even",
115 "core_bi_pll_test_se",
116 };
117
118 static const char * const gcc_parent_names_7_ao[] = {
119 "bi_tcxo_ao",
120 "gpll0",
121 "gpll0_out_even",
122 "core_bi_pll_test_se",
123 };
124
125 static const char * const gcc_parent_names_8[] = {
126 "bi_tcxo",
127 "gpll0",
128 "core_bi_pll_test_se",
129 };
130
131 static const char * const gcc_parent_names_8_ao[] = {
132 "bi_tcxo_ao",
133 "gpll0",
134 "core_bi_pll_test_se",
135 };
136
137 static const struct parent_map gcc_parent_map_10[] = {
138 { P_BI_TCXO, 0 },
139 { P_GPLL0_OUT_MAIN, 1 },
140 { P_GPLL4_OUT_MAIN, 5 },
141 { P_GPLL0_OUT_EVEN, 6 },
142 { P_CORE_BI_PLL_TEST_SE, 7 },
143 };
144
145 static const char * const gcc_parent_names_10[] = {
146 "bi_tcxo",
147 "gpll0",
148 "gpll4",
149 "gpll0_out_even",
150 "core_bi_pll_test_se",
151 };
152
153 static struct clk_alpha_pll gpll0 = {
154 .offset = 0x0,
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
156 .clkr = {
157 .enable_reg = 0x52000,
158 .enable_mask = BIT(0),
159 .hw.init = &(struct clk_init_data){
160 .name = "gpll0",
161 .parent_names = (const char *[]){ "bi_tcxo" },
162 .num_parents = 1,
163 .ops = &clk_alpha_pll_fixed_fabia_ops,
164 },
165 },
166 };
167
168 static struct clk_alpha_pll gpll4 = {
169 .offset = 0x76000,
170 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
171 .clkr = {
172 .enable_reg = 0x52000,
173 .enable_mask = BIT(4),
174 .hw.init = &(struct clk_init_data){
175 .name = "gpll4",
176 .parent_names = (const char *[]){ "bi_tcxo" },
177 .num_parents = 1,
178 .ops = &clk_alpha_pll_fixed_fabia_ops,
179 },
180 },
181 };
182
183 static const struct clk_div_table post_div_table_fabia_even[] = {
184 { 0x0, 1 },
185 { 0x1, 2 },
186 { 0x3, 4 },
187 { 0x7, 8 },
188 { }
189 };
190
191 static struct clk_alpha_pll_postdiv gpll0_out_even = {
192 .offset = 0x0,
193 .post_div_shift = 8,
194 .post_div_table = post_div_table_fabia_even,
195 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
196 .width = 4,
197 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
198 .clkr.hw.init = &(struct clk_init_data){
199 .name = "gpll0_out_even",
200 .parent_names = (const char *[]){ "gpll0" },
201 .num_parents = 1,
202 .ops = &clk_alpha_pll_postdiv_fabia_ops,
203 },
204 };
205
206 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
207 F(19200000, P_BI_TCXO, 1, 0, 0),
208 { }
209 };
210
211 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
212 .cmd_rcgr = 0x48014,
213 .mnd_width = 0,
214 .hid_width = 5,
215 .parent_map = gcc_parent_map_0,
216 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
217 .clkr.hw.init = &(struct clk_init_data){
218 .name = "gcc_cpuss_ahb_clk_src",
219 .parent_names = gcc_parent_names_7_ao,
220 .num_parents = 4,
221 .ops = &clk_rcg2_ops,
222 },
223 };
224
225 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
226 F(19200000, P_BI_TCXO, 1, 0, 0),
227 { }
228 };
229
230 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
231 .cmd_rcgr = 0x4815c,
232 .mnd_width = 0,
233 .hid_width = 5,
234 .parent_map = gcc_parent_map_3,
235 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
236 .clkr.hw.init = &(struct clk_init_data){
237 .name = "gcc_cpuss_rbcpr_clk_src",
238 .parent_names = gcc_parent_names_8_ao,
239 .num_parents = 3,
240 .ops = &clk_rcg2_ops,
241 },
242 };
243
244 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
245 F(19200000, P_BI_TCXO, 1, 0, 0),
246 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
247 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
248 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
249 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
250 { }
251 };
252
253 static struct clk_rcg2 gcc_gp1_clk_src = {
254 .cmd_rcgr = 0x64004,
255 .mnd_width = 8,
256 .hid_width = 5,
257 .parent_map = gcc_parent_map_1,
258 .freq_tbl = ftbl_gcc_gp1_clk_src,
259 .clkr.hw.init = &(struct clk_init_data){
260 .name = "gcc_gp1_clk_src",
261 .parent_names = gcc_parent_names_1,
262 .num_parents = 5,
263 .ops = &clk_rcg2_ops,
264 },
265 };
266
267 static struct clk_rcg2 gcc_gp2_clk_src = {
268 .cmd_rcgr = 0x65004,
269 .mnd_width = 8,
270 .hid_width = 5,
271 .parent_map = gcc_parent_map_1,
272 .freq_tbl = ftbl_gcc_gp1_clk_src,
273 .clkr.hw.init = &(struct clk_init_data){
274 .name = "gcc_gp2_clk_src",
275 .parent_names = gcc_parent_names_1,
276 .num_parents = 5,
277 .ops = &clk_rcg2_ops,
278 },
279 };
280
281 static struct clk_rcg2 gcc_gp3_clk_src = {
282 .cmd_rcgr = 0x66004,
283 .mnd_width = 8,
284 .hid_width = 5,
285 .parent_map = gcc_parent_map_1,
286 .freq_tbl = ftbl_gcc_gp1_clk_src,
287 .clkr.hw.init = &(struct clk_init_data){
288 .name = "gcc_gp3_clk_src",
289 .parent_names = gcc_parent_names_1,
290 .num_parents = 5,
291 .ops = &clk_rcg2_ops,
292 },
293 };
294
295 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
296 F(9600000, P_BI_TCXO, 2, 0, 0),
297 F(19200000, P_BI_TCXO, 1, 0, 0),
298 { }
299 };
300
301 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
302 .cmd_rcgr = 0x6b028,
303 .mnd_width = 16,
304 .hid_width = 5,
305 .parent_map = gcc_parent_map_2,
306 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
307 .clkr.hw.init = &(struct clk_init_data){
308 .name = "gcc_pcie_0_aux_clk_src",
309 .parent_names = gcc_parent_names_2,
310 .num_parents = 3,
311 .ops = &clk_rcg2_ops,
312 },
313 };
314
315 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
316 .cmd_rcgr = 0x8d028,
317 .mnd_width = 16,
318 .hid_width = 5,
319 .parent_map = gcc_parent_map_2,
320 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
321 .clkr.hw.init = &(struct clk_init_data){
322 .name = "gcc_pcie_1_aux_clk_src",
323 .parent_names = gcc_parent_names_2,
324 .num_parents = 3,
325 .ops = &clk_rcg2_ops,
326 },
327 };
328
329 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
332 { }
333 };
334
335 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
336 .cmd_rcgr = 0x6f014,
337 .mnd_width = 0,
338 .hid_width = 5,
339 .parent_map = gcc_parent_map_0,
340 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
341 .clkr.hw.init = &(struct clk_init_data){
342 .name = "gcc_pcie_phy_refgen_clk_src",
343 .parent_names = gcc_parent_names_0,
344 .num_parents = 4,
345 .ops = &clk_rcg2_ops,
346 },
347 };
348
349 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
350 F(19200000, P_BI_TCXO, 1, 0, 0),
351 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
352 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
353 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
354 { }
355 };
356
357 static struct clk_rcg2 gcc_qspi_core_clk_src = {
358 .cmd_rcgr = 0x4b008,
359 .mnd_width = 0,
360 .hid_width = 5,
361 .parent_map = gcc_parent_map_0,
362 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
363 .clkr.hw.init = &(struct clk_init_data){
364 .name = "gcc_qspi_core_clk_src",
365 .parent_names = gcc_parent_names_0,
366 .num_parents = 4,
367 .ops = &clk_rcg2_floor_ops,
368 },
369 };
370
371 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
372 F(9600000, P_BI_TCXO, 2, 0, 0),
373 F(19200000, P_BI_TCXO, 1, 0, 0),
374 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
375 { }
376 };
377
378 static struct clk_rcg2 gcc_pdm2_clk_src = {
379 .cmd_rcgr = 0x33010,
380 .mnd_width = 0,
381 .hid_width = 5,
382 .parent_map = gcc_parent_map_0,
383 .freq_tbl = ftbl_gcc_pdm2_clk_src,
384 .clkr.hw.init = &(struct clk_init_data){
385 .name = "gcc_pdm2_clk_src",
386 .parent_names = gcc_parent_names_0,
387 .num_parents = 4,
388 .ops = &clk_rcg2_ops,
389 },
390 };
391
392 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
393 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
394 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
395 F(19200000, P_BI_TCXO, 1, 0, 0),
396 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
397 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
398 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
399 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
400 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
401 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
402 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
403 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
404 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
405 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
406 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
407 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
408 { }
409 };
410
411 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
412 .name = "gcc_qupv3_wrap0_s0_clk_src",
413 .parent_names = gcc_parent_names_0,
414 .num_parents = 4,
415 .ops = &clk_rcg2_shared_ops,
416 };
417
418 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
419 .cmd_rcgr = 0x17034,
420 .mnd_width = 16,
421 .hid_width = 5,
422 .parent_map = gcc_parent_map_0,
423 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
424 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
425 };
426
427 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
428 .name = "gcc_qupv3_wrap0_s1_clk_src",
429 .parent_names = gcc_parent_names_0,
430 .num_parents = 4,
431 .ops = &clk_rcg2_shared_ops,
432 };
433
434 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
435 .cmd_rcgr = 0x17164,
436 .mnd_width = 16,
437 .hid_width = 5,
438 .parent_map = gcc_parent_map_0,
439 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
440 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
441 };
442
443 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
444 .name = "gcc_qupv3_wrap0_s2_clk_src",
445 .parent_names = gcc_parent_names_0,
446 .num_parents = 4,
447 .ops = &clk_rcg2_shared_ops,
448 };
449
450 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
451 .cmd_rcgr = 0x17294,
452 .mnd_width = 16,
453 .hid_width = 5,
454 .parent_map = gcc_parent_map_0,
455 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
456 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
457 };
458
459 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
460 .name = "gcc_qupv3_wrap0_s3_clk_src",
461 .parent_names = gcc_parent_names_0,
462 .num_parents = 4,
463 .ops = &clk_rcg2_shared_ops,
464 };
465
466 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
467 .cmd_rcgr = 0x173c4,
468 .mnd_width = 16,
469 .hid_width = 5,
470 .parent_map = gcc_parent_map_0,
471 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
472 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
473 };
474
475 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
476 .name = "gcc_qupv3_wrap0_s4_clk_src",
477 .parent_names = gcc_parent_names_0,
478 .num_parents = 4,
479 .ops = &clk_rcg2_shared_ops,
480 };
481
482 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
483 .cmd_rcgr = 0x174f4,
484 .mnd_width = 16,
485 .hid_width = 5,
486 .parent_map = gcc_parent_map_0,
487 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
488 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
489 };
490
491 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
492 .name = "gcc_qupv3_wrap0_s5_clk_src",
493 .parent_names = gcc_parent_names_0,
494 .num_parents = 4,
495 .ops = &clk_rcg2_shared_ops,
496 };
497
498 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
499 .cmd_rcgr = 0x17624,
500 .mnd_width = 16,
501 .hid_width = 5,
502 .parent_map = gcc_parent_map_0,
503 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
504 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
505 };
506
507 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
508 .name = "gcc_qupv3_wrap0_s6_clk_src",
509 .parent_names = gcc_parent_names_0,
510 .num_parents = 4,
511 .ops = &clk_rcg2_shared_ops,
512 };
513
514 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
515 .cmd_rcgr = 0x17754,
516 .mnd_width = 16,
517 .hid_width = 5,
518 .parent_map = gcc_parent_map_0,
519 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
520 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
521 };
522
523 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
524 .name = "gcc_qupv3_wrap0_s7_clk_src",
525 .parent_names = gcc_parent_names_0,
526 .num_parents = 4,
527 .ops = &clk_rcg2_shared_ops,
528 };
529
530 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
531 .cmd_rcgr = 0x17884,
532 .mnd_width = 16,
533 .hid_width = 5,
534 .parent_map = gcc_parent_map_0,
535 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
536 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
537 };
538
539 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
540 .name = "gcc_qupv3_wrap1_s0_clk_src",
541 .parent_names = gcc_parent_names_0,
542 .num_parents = 4,
543 .ops = &clk_rcg2_shared_ops,
544 };
545
546 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
547 .cmd_rcgr = 0x18018,
548 .mnd_width = 16,
549 .hid_width = 5,
550 .parent_map = gcc_parent_map_0,
551 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
552 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
553 };
554
555 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
556 .name = "gcc_qupv3_wrap1_s1_clk_src",
557 .parent_names = gcc_parent_names_0,
558 .num_parents = 4,
559 .ops = &clk_rcg2_shared_ops,
560 };
561
562 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
563 .cmd_rcgr = 0x18148,
564 .mnd_width = 16,
565 .hid_width = 5,
566 .parent_map = gcc_parent_map_0,
567 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
568 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
569 };
570
571 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
572 .name = "gcc_qupv3_wrap1_s2_clk_src",
573 .parent_names = gcc_parent_names_0,
574 .num_parents = 4,
575 .ops = &clk_rcg2_shared_ops,
576 };
577
578 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
579 .cmd_rcgr = 0x18278,
580 .mnd_width = 16,
581 .hid_width = 5,
582 .parent_map = gcc_parent_map_0,
583 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
584 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
585 };
586
587 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
588 .name = "gcc_qupv3_wrap1_s3_clk_src",
589 .parent_names = gcc_parent_names_0,
590 .num_parents = 4,
591 .ops = &clk_rcg2_shared_ops,
592 };
593
594 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
595 .cmd_rcgr = 0x183a8,
596 .mnd_width = 16,
597 .hid_width = 5,
598 .parent_map = gcc_parent_map_0,
599 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
600 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
601 };
602
603 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
604 .name = "gcc_qupv3_wrap1_s4_clk_src",
605 .parent_names = gcc_parent_names_0,
606 .num_parents = 4,
607 .ops = &clk_rcg2_shared_ops,
608 };
609
610 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
611 .cmd_rcgr = 0x184d8,
612 .mnd_width = 16,
613 .hid_width = 5,
614 .parent_map = gcc_parent_map_0,
615 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
616 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
617 };
618
619 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
620 .name = "gcc_qupv3_wrap1_s5_clk_src",
621 .parent_names = gcc_parent_names_0,
622 .num_parents = 4,
623 .ops = &clk_rcg2_shared_ops,
624 };
625
626 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
627 .cmd_rcgr = 0x18608,
628 .mnd_width = 16,
629 .hid_width = 5,
630 .parent_map = gcc_parent_map_0,
631 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
632 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
633 };
634
635 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
636 .name = "gcc_qupv3_wrap1_s6_clk_src",
637 .parent_names = gcc_parent_names_0,
638 .num_parents = 4,
639 .ops = &clk_rcg2_shared_ops,
640 };
641
642 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
643 .cmd_rcgr = 0x18738,
644 .mnd_width = 16,
645 .hid_width = 5,
646 .parent_map = gcc_parent_map_0,
647 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
648 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
649 };
650
651 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
652 .name = "gcc_qupv3_wrap1_s7_clk_src",
653 .parent_names = gcc_parent_names_0,
654 .num_parents = 4,
655 .ops = &clk_rcg2_shared_ops,
656 };
657
658 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
659 .cmd_rcgr = 0x18868,
660 .mnd_width = 16,
661 .hid_width = 5,
662 .parent_map = gcc_parent_map_0,
663 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
664 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
665 };
666
667 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
668 F(400000, P_BI_TCXO, 12, 1, 4),
669 F(9600000, P_BI_TCXO, 2, 0, 0),
670 F(19200000, P_BI_TCXO, 1, 0, 0),
671 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
672 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
673 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
674 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
675 { }
676 };
677
678 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
679 .cmd_rcgr = 0x1400c,
680 .mnd_width = 8,
681 .hid_width = 5,
682 .parent_map = gcc_parent_map_10,
683 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
684 .clkr.hw.init = &(struct clk_init_data){
685 .name = "gcc_sdcc2_apps_clk_src",
686 .parent_names = gcc_parent_names_10,
687 .num_parents = 5,
688 .ops = &clk_rcg2_floor_ops,
689 },
690 };
691
692 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
693 F(400000, P_BI_TCXO, 12, 1, 4),
694 F(9600000, P_BI_TCXO, 2, 0, 0),
695 F(19200000, P_BI_TCXO, 1, 0, 0),
696 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
697 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
698 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
699 { }
700 };
701
702 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
703 .cmd_rcgr = 0x1600c,
704 .mnd_width = 8,
705 .hid_width = 5,
706 .parent_map = gcc_parent_map_0,
707 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
708 .clkr.hw.init = &(struct clk_init_data){
709 .name = "gcc_sdcc4_apps_clk_src",
710 .parent_names = gcc_parent_names_0,
711 .num_parents = 4,
712 .ops = &clk_rcg2_floor_ops,
713 },
714 };
715
716 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
717 F(105495, P_BI_TCXO, 2, 1, 91),
718 { }
719 };
720
721 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
722 .cmd_rcgr = 0x36010,
723 .mnd_width = 8,
724 .hid_width = 5,
725 .parent_map = gcc_parent_map_6,
726 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "gcc_tsif_ref_clk_src",
729 .parent_names = gcc_parent_names_6,
730 .num_parents = 5,
731 .ops = &clk_rcg2_ops,
732 },
733 };
734
735 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
736 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
737 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
738 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
739 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
740 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
741 { }
742 };
743
744 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
745 .cmd_rcgr = 0x7501c,
746 .mnd_width = 8,
747 .hid_width = 5,
748 .parent_map = gcc_parent_map_0,
749 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
750 .clkr.hw.init = &(struct clk_init_data){
751 .name = "gcc_ufs_card_axi_clk_src",
752 .parent_names = gcc_parent_names_0,
753 .num_parents = 4,
754 .ops = &clk_rcg2_shared_ops,
755 },
756 };
757
758 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
759 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
760 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
761 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
762 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
763 { }
764 };
765
766 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
767 .cmd_rcgr = 0x7505c,
768 .mnd_width = 0,
769 .hid_width = 5,
770 .parent_map = gcc_parent_map_0,
771 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
772 .clkr.hw.init = &(struct clk_init_data){
773 .name = "gcc_ufs_card_ice_core_clk_src",
774 .parent_names = gcc_parent_names_0,
775 .num_parents = 4,
776 .ops = &clk_rcg2_shared_ops,
777 },
778 };
779
780 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
781 .cmd_rcgr = 0x75090,
782 .mnd_width = 0,
783 .hid_width = 5,
784 .parent_map = gcc_parent_map_4,
785 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
786 .clkr.hw.init = &(struct clk_init_data){
787 .name = "gcc_ufs_card_phy_aux_clk_src",
788 .parent_names = gcc_parent_names_4,
789 .num_parents = 2,
790 .ops = &clk_rcg2_ops,
791 },
792 };
793
794 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
795 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
796 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
797 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
798 { }
799 };
800
801 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
802 .cmd_rcgr = 0x75074,
803 .mnd_width = 0,
804 .hid_width = 5,
805 .parent_map = gcc_parent_map_0,
806 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
807 .clkr.hw.init = &(struct clk_init_data){
808 .name = "gcc_ufs_card_unipro_core_clk_src",
809 .parent_names = gcc_parent_names_0,
810 .num_parents = 4,
811 .ops = &clk_rcg2_shared_ops,
812 },
813 };
814
815 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
816 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
817 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
818 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
819 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
820 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
821 { }
822 };
823
824 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
825 .cmd_rcgr = 0x7701c,
826 .mnd_width = 8,
827 .hid_width = 5,
828 .parent_map = gcc_parent_map_0,
829 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
830 .clkr.hw.init = &(struct clk_init_data){
831 .name = "gcc_ufs_phy_axi_clk_src",
832 .parent_names = gcc_parent_names_0,
833 .num_parents = 4,
834 .ops = &clk_rcg2_shared_ops,
835 },
836 };
837
838 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
839 .cmd_rcgr = 0x7705c,
840 .mnd_width = 0,
841 .hid_width = 5,
842 .parent_map = gcc_parent_map_0,
843 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
844 .clkr.hw.init = &(struct clk_init_data){
845 .name = "gcc_ufs_phy_ice_core_clk_src",
846 .parent_names = gcc_parent_names_0,
847 .num_parents = 4,
848 .ops = &clk_rcg2_shared_ops,
849 },
850 };
851
852 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
853 .cmd_rcgr = 0x77090,
854 .mnd_width = 0,
855 .hid_width = 5,
856 .parent_map = gcc_parent_map_4,
857 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
858 .clkr.hw.init = &(struct clk_init_data){
859 .name = "gcc_ufs_phy_phy_aux_clk_src",
860 .parent_names = gcc_parent_names_4,
861 .num_parents = 2,
862 .ops = &clk_rcg2_shared_ops,
863 },
864 };
865
866 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
867 .cmd_rcgr = 0x77074,
868 .mnd_width = 0,
869 .hid_width = 5,
870 .parent_map = gcc_parent_map_0,
871 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
872 .clkr.hw.init = &(struct clk_init_data){
873 .name = "gcc_ufs_phy_unipro_core_clk_src",
874 .parent_names = gcc_parent_names_0,
875 .num_parents = 4,
876 .ops = &clk_rcg2_shared_ops,
877 },
878 };
879
880 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
881 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
882 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
883 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
884 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
885 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
886 { }
887 };
888
889 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
890 .cmd_rcgr = 0xf018,
891 .mnd_width = 8,
892 .hid_width = 5,
893 .parent_map = gcc_parent_map_0,
894 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
895 .clkr.hw.init = &(struct clk_init_data){
896 .name = "gcc_usb30_prim_master_clk_src",
897 .parent_names = gcc_parent_names_0,
898 .num_parents = 4,
899 .ops = &clk_rcg2_shared_ops,
900 },
901 };
902
903 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
904 F(19200000, P_BI_TCXO, 1, 0, 0),
905 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
906 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
907 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
908 { }
909 };
910
911 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
912 .cmd_rcgr = 0xf030,
913 .mnd_width = 0,
914 .hid_width = 5,
915 .parent_map = gcc_parent_map_0,
916 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
917 .clkr.hw.init = &(struct clk_init_data){
918 .name = "gcc_usb30_prim_mock_utmi_clk_src",
919 .parent_names = gcc_parent_names_0,
920 .num_parents = 4,
921 .ops = &clk_rcg2_shared_ops,
922 },
923 };
924
925 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
926 .cmd_rcgr = 0x10018,
927 .mnd_width = 8,
928 .hid_width = 5,
929 .parent_map = gcc_parent_map_0,
930 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
931 .clkr.hw.init = &(struct clk_init_data){
932 .name = "gcc_usb30_sec_master_clk_src",
933 .parent_names = gcc_parent_names_0,
934 .num_parents = 4,
935 .ops = &clk_rcg2_ops,
936 },
937 };
938
939 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
940 .cmd_rcgr = 0x10030,
941 .mnd_width = 0,
942 .hid_width = 5,
943 .parent_map = gcc_parent_map_0,
944 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "gcc_usb30_sec_mock_utmi_clk_src",
947 .parent_names = gcc_parent_names_0,
948 .num_parents = 4,
949 .ops = &clk_rcg2_ops,
950 },
951 };
952
953 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
954 .cmd_rcgr = 0xf05c,
955 .mnd_width = 0,
956 .hid_width = 5,
957 .parent_map = gcc_parent_map_2,
958 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
959 .clkr.hw.init = &(struct clk_init_data){
960 .name = "gcc_usb3_prim_phy_aux_clk_src",
961 .parent_names = gcc_parent_names_2,
962 .num_parents = 3,
963 .ops = &clk_rcg2_ops,
964 },
965 };
966
967 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
968 .cmd_rcgr = 0x1005c,
969 .mnd_width = 0,
970 .hid_width = 5,
971 .parent_map = gcc_parent_map_2,
972 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
973 .clkr.hw.init = &(struct clk_init_data){
974 .name = "gcc_usb3_sec_phy_aux_clk_src",
975 .parent_names = gcc_parent_names_2,
976 .num_parents = 3,
977 .ops = &clk_rcg2_shared_ops,
978 },
979 };
980
981 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
982 .cmd_rcgr = 0x7a030,
983 .mnd_width = 0,
984 .hid_width = 5,
985 .parent_map = gcc_parent_map_3,
986 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
987 .clkr.hw.init = &(struct clk_init_data){
988 .name = "gcc_vs_ctrl_clk_src",
989 .parent_names = gcc_parent_names_3,
990 .num_parents = 3,
991 .ops = &clk_rcg2_ops,
992 },
993 };
994
995 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
996 F(19200000, P_BI_TCXO, 1, 0, 0),
997 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
998 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
999 { }
1000 };
1001
1002 static struct clk_rcg2 gcc_vsensor_clk_src = {
1003 .cmd_rcgr = 0x7a018,
1004 .mnd_width = 0,
1005 .hid_width = 5,
1006 .parent_map = gcc_parent_map_3,
1007 .freq_tbl = ftbl_gcc_vsensor_clk_src,
1008 .clkr.hw.init = &(struct clk_init_data){
1009 .name = "gcc_vsensor_clk_src",
1010 .parent_names = gcc_parent_names_8,
1011 .num_parents = 3,
1012 .ops = &clk_rcg2_ops,
1013 },
1014 };
1015
1016 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1017 .halt_reg = 0x90014,
1018 .halt_check = BRANCH_HALT,
1019 .clkr = {
1020 .enable_reg = 0x90014,
1021 .enable_mask = BIT(0),
1022 .hw.init = &(struct clk_init_data){
1023 .name = "gcc_aggre_noc_pcie_tbu_clk",
1024 .ops = &clk_branch2_ops,
1025 },
1026 },
1027 };
1028
1029 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1030 .halt_reg = 0x82028,
1031 .halt_check = BRANCH_HALT,
1032 .hwcg_reg = 0x82028,
1033 .hwcg_bit = 1,
1034 .clkr = {
1035 .enable_reg = 0x82028,
1036 .enable_mask = BIT(0),
1037 .hw.init = &(struct clk_init_data){
1038 .name = "gcc_aggre_ufs_card_axi_clk",
1039 .parent_names = (const char *[]){
1040 "gcc_ufs_card_axi_clk_src",
1041 },
1042 .num_parents = 1,
1043 .flags = CLK_SET_RATE_PARENT,
1044 .ops = &clk_branch2_ops,
1045 },
1046 },
1047 };
1048
1049 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1050 .halt_reg = 0x82024,
1051 .halt_check = BRANCH_HALT,
1052 .hwcg_reg = 0x82024,
1053 .hwcg_bit = 1,
1054 .clkr = {
1055 .enable_reg = 0x82024,
1056 .enable_mask = BIT(0),
1057 .hw.init = &(struct clk_init_data){
1058 .name = "gcc_aggre_ufs_phy_axi_clk",
1059 .parent_names = (const char *[]){
1060 "gcc_ufs_phy_axi_clk_src",
1061 },
1062 .num_parents = 1,
1063 .flags = CLK_SET_RATE_PARENT,
1064 .ops = &clk_branch2_ops,
1065 },
1066 },
1067 };
1068
1069 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1070 .halt_reg = 0x8201c,
1071 .halt_check = BRANCH_HALT,
1072 .clkr = {
1073 .enable_reg = 0x8201c,
1074 .enable_mask = BIT(0),
1075 .hw.init = &(struct clk_init_data){
1076 .name = "gcc_aggre_usb3_prim_axi_clk",
1077 .parent_names = (const char *[]){
1078 "gcc_usb30_prim_master_clk_src",
1079 },
1080 .num_parents = 1,
1081 .flags = CLK_SET_RATE_PARENT,
1082 .ops = &clk_branch2_ops,
1083 },
1084 },
1085 };
1086
1087 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1088 .halt_reg = 0x82020,
1089 .halt_check = BRANCH_HALT,
1090 .clkr = {
1091 .enable_reg = 0x82020,
1092 .enable_mask = BIT(0),
1093 .hw.init = &(struct clk_init_data){
1094 .name = "gcc_aggre_usb3_sec_axi_clk",
1095 .parent_names = (const char *[]){
1096 "gcc_usb30_sec_master_clk_src",
1097 },
1098 .num_parents = 1,
1099 .flags = CLK_SET_RATE_PARENT,
1100 .ops = &clk_branch2_ops,
1101 },
1102 },
1103 };
1104
1105 static struct clk_branch gcc_apc_vs_clk = {
1106 .halt_reg = 0x7a050,
1107 .halt_check = BRANCH_HALT,
1108 .clkr = {
1109 .enable_reg = 0x7a050,
1110 .enable_mask = BIT(0),
1111 .hw.init = &(struct clk_init_data){
1112 .name = "gcc_apc_vs_clk",
1113 .parent_names = (const char *[]){
1114 "gcc_vsensor_clk_src",
1115 },
1116 .num_parents = 1,
1117 .flags = CLK_SET_RATE_PARENT,
1118 .ops = &clk_branch2_ops,
1119 },
1120 },
1121 };
1122
1123 static struct clk_branch gcc_boot_rom_ahb_clk = {
1124 .halt_reg = 0x38004,
1125 .halt_check = BRANCH_HALT_VOTED,
1126 .hwcg_reg = 0x38004,
1127 .hwcg_bit = 1,
1128 .clkr = {
1129 .enable_reg = 0x52004,
1130 .enable_mask = BIT(10),
1131 .hw.init = &(struct clk_init_data){
1132 .name = "gcc_boot_rom_ahb_clk",
1133 .ops = &clk_branch2_ops,
1134 },
1135 },
1136 };
1137
1138 static struct clk_branch gcc_camera_ahb_clk = {
1139 .halt_reg = 0xb008,
1140 .halt_check = BRANCH_HALT,
1141 .hwcg_reg = 0xb008,
1142 .hwcg_bit = 1,
1143 .clkr = {
1144 .enable_reg = 0xb008,
1145 .enable_mask = BIT(0),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "gcc_camera_ahb_clk",
1148 .flags = CLK_IS_CRITICAL,
1149 .ops = &clk_branch2_ops,
1150 },
1151 },
1152 };
1153
1154 static struct clk_branch gcc_camera_axi_clk = {
1155 .halt_reg = 0xb020,
1156 .halt_check = BRANCH_VOTED,
1157 .clkr = {
1158 .enable_reg = 0xb020,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data){
1161 .name = "gcc_camera_axi_clk",
1162 .ops = &clk_branch2_ops,
1163 },
1164 },
1165 };
1166
1167 static struct clk_branch gcc_camera_xo_clk = {
1168 .halt_reg = 0xb02c,
1169 .halt_check = BRANCH_HALT,
1170 .clkr = {
1171 .enable_reg = 0xb02c,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data){
1174 .name = "gcc_camera_xo_clk",
1175 .flags = CLK_IS_CRITICAL,
1176 .ops = &clk_branch2_ops,
1177 },
1178 },
1179 };
1180
1181 static struct clk_branch gcc_ce1_ahb_clk = {
1182 .halt_reg = 0x4100c,
1183 .halt_check = BRANCH_HALT_VOTED,
1184 .hwcg_reg = 0x4100c,
1185 .hwcg_bit = 1,
1186 .clkr = {
1187 .enable_reg = 0x52004,
1188 .enable_mask = BIT(3),
1189 .hw.init = &(struct clk_init_data){
1190 .name = "gcc_ce1_ahb_clk",
1191 .ops = &clk_branch2_ops,
1192 },
1193 },
1194 };
1195
1196 static struct clk_branch gcc_ce1_axi_clk = {
1197 .halt_reg = 0x41008,
1198 .halt_check = BRANCH_HALT_VOTED,
1199 .clkr = {
1200 .enable_reg = 0x52004,
1201 .enable_mask = BIT(4),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "gcc_ce1_axi_clk",
1204 .ops = &clk_branch2_ops,
1205 },
1206 },
1207 };
1208
1209 static struct clk_branch gcc_ce1_clk = {
1210 .halt_reg = 0x41004,
1211 .halt_check = BRANCH_HALT_VOTED,
1212 .clkr = {
1213 .enable_reg = 0x52004,
1214 .enable_mask = BIT(5),
1215 .hw.init = &(struct clk_init_data){
1216 .name = "gcc_ce1_clk",
1217 .ops = &clk_branch2_ops,
1218 },
1219 },
1220 };
1221
1222 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1223 .halt_reg = 0x502c,
1224 .halt_check = BRANCH_HALT,
1225 .clkr = {
1226 .enable_reg = 0x502c,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1230 .parent_names = (const char *[]){
1231 "gcc_usb30_prim_master_clk_src",
1232 },
1233 .num_parents = 1,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238 };
1239
1240 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1241 .halt_reg = 0x5030,
1242 .halt_check = BRANCH_HALT,
1243 .clkr = {
1244 .enable_reg = 0x5030,
1245 .enable_mask = BIT(0),
1246 .hw.init = &(struct clk_init_data){
1247 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1248 .parent_names = (const char *[]){
1249 "gcc_usb30_sec_master_clk_src",
1250 },
1251 .num_parents = 1,
1252 .flags = CLK_SET_RATE_PARENT,
1253 .ops = &clk_branch2_ops,
1254 },
1255 },
1256 };
1257
1258 static struct clk_branch gcc_cpuss_ahb_clk = {
1259 .halt_reg = 0x48000,
1260 .halt_check = BRANCH_HALT_VOTED,
1261 .clkr = {
1262 .enable_reg = 0x52004,
1263 .enable_mask = BIT(21),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "gcc_cpuss_ahb_clk",
1266 .parent_names = (const char *[]){
1267 "gcc_cpuss_ahb_clk_src",
1268 },
1269 .num_parents = 1,
1270 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1271 .ops = &clk_branch2_ops,
1272 },
1273 },
1274 };
1275
1276 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1277 .halt_reg = 0x48008,
1278 .halt_check = BRANCH_HALT,
1279 .clkr = {
1280 .enable_reg = 0x48008,
1281 .enable_mask = BIT(0),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "gcc_cpuss_rbcpr_clk",
1284 .parent_names = (const char *[]){
1285 "gcc_cpuss_rbcpr_clk_src",
1286 },
1287 .num_parents = 1,
1288 .flags = CLK_SET_RATE_PARENT,
1289 .ops = &clk_branch2_ops,
1290 },
1291 },
1292 };
1293
1294 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1295 .halt_reg = 0x44038,
1296 .halt_check = BRANCH_VOTED,
1297 .clkr = {
1298 .enable_reg = 0x44038,
1299 .enable_mask = BIT(0),
1300 .hw.init = &(struct clk_init_data){
1301 .name = "gcc_ddrss_gpu_axi_clk",
1302 .ops = &clk_branch2_ops,
1303 },
1304 },
1305 };
1306
1307 static struct clk_branch gcc_disp_ahb_clk = {
1308 .halt_reg = 0xb00c,
1309 .halt_check = BRANCH_HALT,
1310 .hwcg_reg = 0xb00c,
1311 .hwcg_bit = 1,
1312 .clkr = {
1313 .enable_reg = 0xb00c,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "gcc_disp_ahb_clk",
1317 .flags = CLK_IS_CRITICAL,
1318 .ops = &clk_branch2_ops,
1319 },
1320 },
1321 };
1322
1323 static struct clk_branch gcc_disp_axi_clk = {
1324 .halt_reg = 0xb024,
1325 .halt_check = BRANCH_VOTED,
1326 .clkr = {
1327 .enable_reg = 0xb024,
1328 .enable_mask = BIT(0),
1329 .hw.init = &(struct clk_init_data){
1330 .name = "gcc_disp_axi_clk",
1331 .ops = &clk_branch2_ops,
1332 },
1333 },
1334 };
1335
1336 static struct clk_branch gcc_disp_gpll0_clk_src = {
1337 .halt_check = BRANCH_HALT_DELAY,
1338 .clkr = {
1339 .enable_reg = 0x52004,
1340 .enable_mask = BIT(18),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_disp_gpll0_clk_src",
1343 .parent_names = (const char *[]){
1344 "gpll0",
1345 },
1346 .num_parents = 1,
1347 .ops = &clk_branch2_ops,
1348 },
1349 },
1350 };
1351
1352 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1353 .halt_check = BRANCH_HALT_DELAY,
1354 .clkr = {
1355 .enable_reg = 0x52004,
1356 .enable_mask = BIT(19),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "gcc_disp_gpll0_div_clk_src",
1359 .parent_names = (const char *[]){
1360 "gpll0_out_even",
1361 },
1362 .num_parents = 1,
1363 .ops = &clk_branch2_ops,
1364 },
1365 },
1366 };
1367
1368 static struct clk_branch gcc_disp_xo_clk = {
1369 .halt_reg = 0xb030,
1370 .halt_check = BRANCH_HALT,
1371 .clkr = {
1372 .enable_reg = 0xb030,
1373 .enable_mask = BIT(0),
1374 .hw.init = &(struct clk_init_data){
1375 .name = "gcc_disp_xo_clk",
1376 .flags = CLK_IS_CRITICAL,
1377 .ops = &clk_branch2_ops,
1378 },
1379 },
1380 };
1381
1382 static struct clk_branch gcc_gp1_clk = {
1383 .halt_reg = 0x64000,
1384 .halt_check = BRANCH_HALT,
1385 .clkr = {
1386 .enable_reg = 0x64000,
1387 .enable_mask = BIT(0),
1388 .hw.init = &(struct clk_init_data){
1389 .name = "gcc_gp1_clk",
1390 .parent_names = (const char *[]){
1391 "gcc_gp1_clk_src",
1392 },
1393 .num_parents = 1,
1394 .flags = CLK_SET_RATE_PARENT,
1395 .ops = &clk_branch2_ops,
1396 },
1397 },
1398 };
1399
1400 static struct clk_branch gcc_gp2_clk = {
1401 .halt_reg = 0x65000,
1402 .halt_check = BRANCH_HALT,
1403 .clkr = {
1404 .enable_reg = 0x65000,
1405 .enable_mask = BIT(0),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "gcc_gp2_clk",
1408 .parent_names = (const char *[]){
1409 "gcc_gp2_clk_src",
1410 },
1411 .num_parents = 1,
1412 .flags = CLK_SET_RATE_PARENT,
1413 .ops = &clk_branch2_ops,
1414 },
1415 },
1416 };
1417
1418 static struct clk_branch gcc_gp3_clk = {
1419 .halt_reg = 0x66000,
1420 .halt_check = BRANCH_HALT,
1421 .clkr = {
1422 .enable_reg = 0x66000,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_gp3_clk",
1426 .parent_names = (const char *[]){
1427 "gcc_gp3_clk_src",
1428 },
1429 .num_parents = 1,
1430 .flags = CLK_SET_RATE_PARENT,
1431 .ops = &clk_branch2_ops,
1432 },
1433 },
1434 };
1435
1436 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1437 .halt_reg = 0x71004,
1438 .halt_check = BRANCH_HALT,
1439 .hwcg_reg = 0x71004,
1440 .hwcg_bit = 1,
1441 .clkr = {
1442 .enable_reg = 0x71004,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "gcc_gpu_cfg_ahb_clk",
1446 .flags = CLK_IS_CRITICAL,
1447 .ops = &clk_branch2_ops,
1448 },
1449 },
1450 };
1451
1452 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1453 .halt_check = BRANCH_HALT_DELAY,
1454 .clkr = {
1455 .enable_reg = 0x52004,
1456 .enable_mask = BIT(15),
1457 .hw.init = &(struct clk_init_data){
1458 .name = "gcc_gpu_gpll0_clk_src",
1459 .parent_names = (const char *[]){
1460 "gpll0",
1461 },
1462 .num_parents = 1,
1463 .ops = &clk_branch2_ops,
1464 },
1465 },
1466 };
1467
1468 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1469 .halt_check = BRANCH_HALT_DELAY,
1470 .clkr = {
1471 .enable_reg = 0x52004,
1472 .enable_mask = BIT(16),
1473 .hw.init = &(struct clk_init_data){
1474 .name = "gcc_gpu_gpll0_div_clk_src",
1475 .parent_names = (const char *[]){
1476 "gpll0_out_even",
1477 },
1478 .num_parents = 1,
1479 .ops = &clk_branch2_ops,
1480 },
1481 },
1482 };
1483
1484 static struct clk_branch gcc_gpu_iref_clk = {
1485 .halt_reg = 0x8c010,
1486 .halt_check = BRANCH_HALT,
1487 .clkr = {
1488 .enable_reg = 0x8c010,
1489 .enable_mask = BIT(0),
1490 .hw.init = &(struct clk_init_data){
1491 .name = "gcc_gpu_iref_clk",
1492 .ops = &clk_branch2_ops,
1493 },
1494 },
1495 };
1496
1497 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1498 .halt_reg = 0x7100c,
1499 .halt_check = BRANCH_VOTED,
1500 .clkr = {
1501 .enable_reg = 0x7100c,
1502 .enable_mask = BIT(0),
1503 .hw.init = &(struct clk_init_data){
1504 .name = "gcc_gpu_memnoc_gfx_clk",
1505 .ops = &clk_branch2_ops,
1506 },
1507 },
1508 };
1509
1510 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1511 .halt_reg = 0x71018,
1512 .halt_check = BRANCH_HALT,
1513 .clkr = {
1514 .enable_reg = 0x71018,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1518 .ops = &clk_branch2_ops,
1519 },
1520 },
1521 };
1522
1523 static struct clk_branch gcc_gpu_vs_clk = {
1524 .halt_reg = 0x7a04c,
1525 .halt_check = BRANCH_HALT,
1526 .clkr = {
1527 .enable_reg = 0x7a04c,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_gpu_vs_clk",
1531 .parent_names = (const char *[]){
1532 "gcc_vsensor_clk_src",
1533 },
1534 .num_parents = 1,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1537 },
1538 },
1539 };
1540
1541 static struct clk_branch gcc_mss_axis2_clk = {
1542 .halt_reg = 0x8a008,
1543 .halt_check = BRANCH_HALT,
1544 .clkr = {
1545 .enable_reg = 0x8a008,
1546 .enable_mask = BIT(0),
1547 .hw.init = &(struct clk_init_data){
1548 .name = "gcc_mss_axis2_clk",
1549 .ops = &clk_branch2_ops,
1550 },
1551 },
1552 };
1553
1554 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1555 .halt_reg = 0x8a000,
1556 .halt_check = BRANCH_HALT,
1557 .hwcg_reg = 0x8a000,
1558 .hwcg_bit = 1,
1559 .clkr = {
1560 .enable_reg = 0x8a000,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(struct clk_init_data){
1563 .name = "gcc_mss_cfg_ahb_clk",
1564 .ops = &clk_branch2_ops,
1565 },
1566 },
1567 };
1568
1569 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1570 .halt_check = BRANCH_HALT_DELAY,
1571 .clkr = {
1572 .enable_reg = 0x52004,
1573 .enable_mask = BIT(17),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_mss_gpll0_div_clk_src",
1576 .ops = &clk_branch2_ops,
1577 },
1578 },
1579 };
1580
1581 static struct clk_branch gcc_mss_mfab_axis_clk = {
1582 .halt_reg = 0x8a004,
1583 .halt_check = BRANCH_VOTED,
1584 .hwcg_reg = 0x8a004,
1585 .hwcg_bit = 1,
1586 .clkr = {
1587 .enable_reg = 0x8a004,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_mss_mfab_axis_clk",
1591 .ops = &clk_branch2_ops,
1592 },
1593 },
1594 };
1595
1596 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1597 .halt_reg = 0x8a154,
1598 .halt_check = BRANCH_VOTED,
1599 .clkr = {
1600 .enable_reg = 0x8a154,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "gcc_mss_q6_memnoc_axi_clk",
1604 .ops = &clk_branch2_ops,
1605 },
1606 },
1607 };
1608
1609 static struct clk_branch gcc_mss_snoc_axi_clk = {
1610 .halt_reg = 0x8a150,
1611 .halt_check = BRANCH_HALT,
1612 .clkr = {
1613 .enable_reg = 0x8a150,
1614 .enable_mask = BIT(0),
1615 .hw.init = &(struct clk_init_data){
1616 .name = "gcc_mss_snoc_axi_clk",
1617 .ops = &clk_branch2_ops,
1618 },
1619 },
1620 };
1621
1622 static struct clk_branch gcc_mss_vs_clk = {
1623 .halt_reg = 0x7a048,
1624 .halt_check = BRANCH_HALT,
1625 .clkr = {
1626 .enable_reg = 0x7a048,
1627 .enable_mask = BIT(0),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "gcc_mss_vs_clk",
1630 .parent_names = (const char *[]){
1631 "gcc_vsensor_clk_src",
1632 },
1633 .num_parents = 1,
1634 .flags = CLK_SET_RATE_PARENT,
1635 .ops = &clk_branch2_ops,
1636 },
1637 },
1638 };
1639
1640 static struct clk_branch gcc_pcie_0_aux_clk = {
1641 .halt_reg = 0x6b01c,
1642 .halt_check = BRANCH_HALT_VOTED,
1643 .clkr = {
1644 .enable_reg = 0x5200c,
1645 .enable_mask = BIT(3),
1646 .hw.init = &(struct clk_init_data){
1647 .name = "gcc_pcie_0_aux_clk",
1648 .parent_names = (const char *[]){
1649 "gcc_pcie_0_aux_clk_src",
1650 },
1651 .num_parents = 1,
1652 .flags = CLK_SET_RATE_PARENT,
1653 .ops = &clk_branch2_ops,
1654 },
1655 },
1656 };
1657
1658 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1659 .halt_reg = 0x6b018,
1660 .halt_check = BRANCH_HALT_VOTED,
1661 .hwcg_reg = 0x6b018,
1662 .hwcg_bit = 1,
1663 .clkr = {
1664 .enable_reg = 0x5200c,
1665 .enable_mask = BIT(2),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_pcie_0_cfg_ahb_clk",
1668 .ops = &clk_branch2_ops,
1669 },
1670 },
1671 };
1672
1673 static struct clk_branch gcc_pcie_0_clkref_clk = {
1674 .halt_reg = 0x8c00c,
1675 .halt_check = BRANCH_HALT,
1676 .clkr = {
1677 .enable_reg = 0x8c00c,
1678 .enable_mask = BIT(0),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "gcc_pcie_0_clkref_clk",
1681 .ops = &clk_branch2_ops,
1682 },
1683 },
1684 };
1685
1686 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1687 .halt_reg = 0x6b014,
1688 .halt_check = BRANCH_HALT_VOTED,
1689 .clkr = {
1690 .enable_reg = 0x5200c,
1691 .enable_mask = BIT(1),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "gcc_pcie_0_mstr_axi_clk",
1694 .ops = &clk_branch2_ops,
1695 },
1696 },
1697 };
1698
1699 static struct clk_branch gcc_pcie_0_pipe_clk = {
1700 .halt_check = BRANCH_HALT_SKIP,
1701 .clkr = {
1702 .enable_reg = 0x5200c,
1703 .enable_mask = BIT(4),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "gcc_pcie_0_pipe_clk",
1706 .parent_names = (const char *[]){ "pcie_0_pipe_clk" },
1707 .num_parents = 1,
1708 .flags = CLK_SET_RATE_PARENT,
1709 .ops = &clk_branch2_ops,
1710 },
1711 },
1712 };
1713
1714 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1715 .halt_reg = 0x6b010,
1716 .halt_check = BRANCH_HALT_VOTED,
1717 .hwcg_reg = 0x6b010,
1718 .hwcg_bit = 1,
1719 .clkr = {
1720 .enable_reg = 0x5200c,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_pcie_0_slv_axi_clk",
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727 };
1728
1729 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1730 .halt_reg = 0x6b00c,
1731 .halt_check = BRANCH_HALT_VOTED,
1732 .clkr = {
1733 .enable_reg = 0x5200c,
1734 .enable_mask = BIT(5),
1735 .hw.init = &(struct clk_init_data){
1736 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1737 .ops = &clk_branch2_ops,
1738 },
1739 },
1740 };
1741
1742 static struct clk_branch gcc_pcie_1_aux_clk = {
1743 .halt_reg = 0x8d01c,
1744 .halt_check = BRANCH_HALT_VOTED,
1745 .clkr = {
1746 .enable_reg = 0x52004,
1747 .enable_mask = BIT(29),
1748 .hw.init = &(struct clk_init_data){
1749 .name = "gcc_pcie_1_aux_clk",
1750 .parent_names = (const char *[]){
1751 "gcc_pcie_1_aux_clk_src",
1752 },
1753 .num_parents = 1,
1754 .flags = CLK_SET_RATE_PARENT,
1755 .ops = &clk_branch2_ops,
1756 },
1757 },
1758 };
1759
1760 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1761 .halt_reg = 0x8d018,
1762 .halt_check = BRANCH_HALT_VOTED,
1763 .hwcg_reg = 0x8d018,
1764 .hwcg_bit = 1,
1765 .clkr = {
1766 .enable_reg = 0x52004,
1767 .enable_mask = BIT(28),
1768 .hw.init = &(struct clk_init_data){
1769 .name = "gcc_pcie_1_cfg_ahb_clk",
1770 .ops = &clk_branch2_ops,
1771 },
1772 },
1773 };
1774
1775 static struct clk_branch gcc_pcie_1_clkref_clk = {
1776 .halt_reg = 0x8c02c,
1777 .halt_check = BRANCH_HALT,
1778 .clkr = {
1779 .enable_reg = 0x8c02c,
1780 .enable_mask = BIT(0),
1781 .hw.init = &(struct clk_init_data){
1782 .name = "gcc_pcie_1_clkref_clk",
1783 .ops = &clk_branch2_ops,
1784 },
1785 },
1786 };
1787
1788 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1789 .halt_reg = 0x8d014,
1790 .halt_check = BRANCH_HALT_VOTED,
1791 .clkr = {
1792 .enable_reg = 0x52004,
1793 .enable_mask = BIT(27),
1794 .hw.init = &(struct clk_init_data){
1795 .name = "gcc_pcie_1_mstr_axi_clk",
1796 .ops = &clk_branch2_ops,
1797 },
1798 },
1799 };
1800
1801 static struct clk_branch gcc_pcie_1_pipe_clk = {
1802 .halt_check = BRANCH_HALT_SKIP,
1803 .clkr = {
1804 .enable_reg = 0x52004,
1805 .enable_mask = BIT(30),
1806 .hw.init = &(struct clk_init_data){
1807 .name = "gcc_pcie_1_pipe_clk",
1808 .parent_names = (const char *[]){ "pcie_1_pipe_clk" },
1809 .num_parents = 1,
1810 .ops = &clk_branch2_ops,
1811 },
1812 },
1813 };
1814
1815 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1816 .halt_reg = 0x8d010,
1817 .halt_check = BRANCH_HALT_VOTED,
1818 .hwcg_reg = 0x8d010,
1819 .hwcg_bit = 1,
1820 .clkr = {
1821 .enable_reg = 0x52004,
1822 .enable_mask = BIT(26),
1823 .hw.init = &(struct clk_init_data){
1824 .name = "gcc_pcie_1_slv_axi_clk",
1825 .ops = &clk_branch2_ops,
1826 },
1827 },
1828 };
1829
1830 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1831 .halt_reg = 0x8d00c,
1832 .halt_check = BRANCH_HALT_VOTED,
1833 .clkr = {
1834 .enable_reg = 0x52004,
1835 .enable_mask = BIT(25),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1838 .ops = &clk_branch2_ops,
1839 },
1840 },
1841 };
1842
1843 static struct clk_branch gcc_pcie_phy_aux_clk = {
1844 .halt_reg = 0x6f004,
1845 .halt_check = BRANCH_HALT,
1846 .clkr = {
1847 .enable_reg = 0x6f004,
1848 .enable_mask = BIT(0),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "gcc_pcie_phy_aux_clk",
1851 .parent_names = (const char *[]){
1852 "gcc_pcie_0_aux_clk_src",
1853 },
1854 .num_parents = 1,
1855 .flags = CLK_SET_RATE_PARENT,
1856 .ops = &clk_branch2_ops,
1857 },
1858 },
1859 };
1860
1861 static struct clk_branch gcc_pcie_phy_refgen_clk = {
1862 .halt_reg = 0x6f02c,
1863 .halt_check = BRANCH_HALT,
1864 .clkr = {
1865 .enable_reg = 0x6f02c,
1866 .enable_mask = BIT(0),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "gcc_pcie_phy_refgen_clk",
1869 .parent_names = (const char *[]){
1870 "gcc_pcie_phy_refgen_clk_src",
1871 },
1872 .num_parents = 1,
1873 .flags = CLK_SET_RATE_PARENT,
1874 .ops = &clk_branch2_ops,
1875 },
1876 },
1877 };
1878
1879 static struct clk_branch gcc_pdm2_clk = {
1880 .halt_reg = 0x3300c,
1881 .halt_check = BRANCH_HALT,
1882 .clkr = {
1883 .enable_reg = 0x3300c,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "gcc_pdm2_clk",
1887 .parent_names = (const char *[]){
1888 "gcc_pdm2_clk_src",
1889 },
1890 .num_parents = 1,
1891 .flags = CLK_SET_RATE_PARENT,
1892 .ops = &clk_branch2_ops,
1893 },
1894 },
1895 };
1896
1897 static struct clk_branch gcc_pdm_ahb_clk = {
1898 .halt_reg = 0x33004,
1899 .halt_check = BRANCH_HALT,
1900 .hwcg_reg = 0x33004,
1901 .hwcg_bit = 1,
1902 .clkr = {
1903 .enable_reg = 0x33004,
1904 .enable_mask = BIT(0),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "gcc_pdm_ahb_clk",
1907 .ops = &clk_branch2_ops,
1908 },
1909 },
1910 };
1911
1912 static struct clk_branch gcc_pdm_xo4_clk = {
1913 .halt_reg = 0x33008,
1914 .halt_check = BRANCH_HALT,
1915 .clkr = {
1916 .enable_reg = 0x33008,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "gcc_pdm_xo4_clk",
1920 .ops = &clk_branch2_ops,
1921 },
1922 },
1923 };
1924
1925 static struct clk_branch gcc_prng_ahb_clk = {
1926 .halt_reg = 0x34004,
1927 .halt_check = BRANCH_HALT_VOTED,
1928 .hwcg_reg = 0x34004,
1929 .hwcg_bit = 1,
1930 .clkr = {
1931 .enable_reg = 0x52004,
1932 .enable_mask = BIT(13),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "gcc_prng_ahb_clk",
1935 .ops = &clk_branch2_ops,
1936 },
1937 },
1938 };
1939
1940 static struct clk_branch gcc_qmip_camera_ahb_clk = {
1941 .halt_reg = 0xb014,
1942 .halt_check = BRANCH_HALT,
1943 .hwcg_reg = 0xb014,
1944 .hwcg_bit = 1,
1945 .clkr = {
1946 .enable_reg = 0xb014,
1947 .enable_mask = BIT(0),
1948 .hw.init = &(struct clk_init_data){
1949 .name = "gcc_qmip_camera_ahb_clk",
1950 .ops = &clk_branch2_ops,
1951 },
1952 },
1953 };
1954
1955 static struct clk_branch gcc_qmip_disp_ahb_clk = {
1956 .halt_reg = 0xb018,
1957 .halt_check = BRANCH_HALT,
1958 .hwcg_reg = 0xb018,
1959 .hwcg_bit = 1,
1960 .clkr = {
1961 .enable_reg = 0xb018,
1962 .enable_mask = BIT(0),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "gcc_qmip_disp_ahb_clk",
1965 .ops = &clk_branch2_ops,
1966 },
1967 },
1968 };
1969
1970 static struct clk_branch gcc_qmip_video_ahb_clk = {
1971 .halt_reg = 0xb010,
1972 .halt_check = BRANCH_HALT,
1973 .hwcg_reg = 0xb010,
1974 .hwcg_bit = 1,
1975 .clkr = {
1976 .enable_reg = 0xb010,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_qmip_video_ahb_clk",
1980 .ops = &clk_branch2_ops,
1981 },
1982 },
1983 };
1984
1985 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1986 .halt_reg = 0x4b000,
1987 .halt_check = BRANCH_HALT,
1988 .clkr = {
1989 .enable_reg = 0x4b000,
1990 .enable_mask = BIT(0),
1991 .hw.init = &(struct clk_init_data){
1992 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1993 .ops = &clk_branch2_ops,
1994 },
1995 },
1996 };
1997
1998 static struct clk_branch gcc_qspi_core_clk = {
1999 .halt_reg = 0x4b004,
2000 .halt_check = BRANCH_HALT,
2001 .clkr = {
2002 .enable_reg = 0x4b004,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data){
2005 .name = "gcc_qspi_core_clk",
2006 .parent_names = (const char *[]){
2007 "gcc_qspi_core_clk_src",
2008 },
2009 .num_parents = 1,
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2012 },
2013 },
2014 };
2015
2016 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2017 .halt_reg = 0x17030,
2018 .halt_check = BRANCH_HALT_VOTED,
2019 .clkr = {
2020 .enable_reg = 0x5200c,
2021 .enable_mask = BIT(10),
2022 .hw.init = &(struct clk_init_data){
2023 .name = "gcc_qupv3_wrap0_s0_clk",
2024 .parent_names = (const char *[]){
2025 "gcc_qupv3_wrap0_s0_clk_src",
2026 },
2027 .num_parents = 1,
2028 .flags = CLK_SET_RATE_PARENT,
2029 .ops = &clk_branch2_ops,
2030 },
2031 },
2032 };
2033
2034 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2035 .halt_reg = 0x17160,
2036 .halt_check = BRANCH_HALT_VOTED,
2037 .clkr = {
2038 .enable_reg = 0x5200c,
2039 .enable_mask = BIT(11),
2040 .hw.init = &(struct clk_init_data){
2041 .name = "gcc_qupv3_wrap0_s1_clk",
2042 .parent_names = (const char *[]){
2043 "gcc_qupv3_wrap0_s1_clk_src",
2044 },
2045 .num_parents = 1,
2046 .flags = CLK_SET_RATE_PARENT,
2047 .ops = &clk_branch2_ops,
2048 },
2049 },
2050 };
2051
2052 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2053 .halt_reg = 0x17290,
2054 .halt_check = BRANCH_HALT_VOTED,
2055 .clkr = {
2056 .enable_reg = 0x5200c,
2057 .enable_mask = BIT(12),
2058 .hw.init = &(struct clk_init_data){
2059 .name = "gcc_qupv3_wrap0_s2_clk",
2060 .parent_names = (const char *[]){
2061 "gcc_qupv3_wrap0_s2_clk_src",
2062 },
2063 .num_parents = 1,
2064 .flags = CLK_SET_RATE_PARENT,
2065 .ops = &clk_branch2_ops,
2066 },
2067 },
2068 };
2069
2070 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2071 .halt_reg = 0x173c0,
2072 .halt_check = BRANCH_HALT_VOTED,
2073 .clkr = {
2074 .enable_reg = 0x5200c,
2075 .enable_mask = BIT(13),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_qupv3_wrap0_s3_clk",
2078 .parent_names = (const char *[]){
2079 "gcc_qupv3_wrap0_s3_clk_src",
2080 },
2081 .num_parents = 1,
2082 .flags = CLK_SET_RATE_PARENT,
2083 .ops = &clk_branch2_ops,
2084 },
2085 },
2086 };
2087
2088 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2089 .halt_reg = 0x174f0,
2090 .halt_check = BRANCH_HALT_VOTED,
2091 .clkr = {
2092 .enable_reg = 0x5200c,
2093 .enable_mask = BIT(14),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gcc_qupv3_wrap0_s4_clk",
2096 .parent_names = (const char *[]){
2097 "gcc_qupv3_wrap0_s4_clk_src",
2098 },
2099 .num_parents = 1,
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2102 },
2103 },
2104 };
2105
2106 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2107 .halt_reg = 0x17620,
2108 .halt_check = BRANCH_HALT_VOTED,
2109 .clkr = {
2110 .enable_reg = 0x5200c,
2111 .enable_mask = BIT(15),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_qupv3_wrap0_s5_clk",
2114 .parent_names = (const char *[]){
2115 "gcc_qupv3_wrap0_s5_clk_src",
2116 },
2117 .num_parents = 1,
2118 .flags = CLK_SET_RATE_PARENT,
2119 .ops = &clk_branch2_ops,
2120 },
2121 },
2122 };
2123
2124 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2125 .halt_reg = 0x17750,
2126 .halt_check = BRANCH_HALT_VOTED,
2127 .clkr = {
2128 .enable_reg = 0x5200c,
2129 .enable_mask = BIT(16),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "gcc_qupv3_wrap0_s6_clk",
2132 .parent_names = (const char *[]){
2133 "gcc_qupv3_wrap0_s6_clk_src",
2134 },
2135 .num_parents = 1,
2136 .flags = CLK_SET_RATE_PARENT,
2137 .ops = &clk_branch2_ops,
2138 },
2139 },
2140 };
2141
2142 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2143 .halt_reg = 0x17880,
2144 .halt_check = BRANCH_HALT_VOTED,
2145 .clkr = {
2146 .enable_reg = 0x5200c,
2147 .enable_mask = BIT(17),
2148 .hw.init = &(struct clk_init_data){
2149 .name = "gcc_qupv3_wrap0_s7_clk",
2150 .parent_names = (const char *[]){
2151 "gcc_qupv3_wrap0_s7_clk_src",
2152 },
2153 .num_parents = 1,
2154 .flags = CLK_SET_RATE_PARENT,
2155 .ops = &clk_branch2_ops,
2156 },
2157 },
2158 };
2159
2160 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2161 .halt_reg = 0x18014,
2162 .halt_check = BRANCH_HALT_VOTED,
2163 .clkr = {
2164 .enable_reg = 0x5200c,
2165 .enable_mask = BIT(22),
2166 .hw.init = &(struct clk_init_data){
2167 .name = "gcc_qupv3_wrap1_s0_clk",
2168 .parent_names = (const char *[]){
2169 "gcc_qupv3_wrap1_s0_clk_src",
2170 },
2171 .num_parents = 1,
2172 .flags = CLK_SET_RATE_PARENT,
2173 .ops = &clk_branch2_ops,
2174 },
2175 },
2176 };
2177
2178 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2179 .halt_reg = 0x18144,
2180 .halt_check = BRANCH_HALT_VOTED,
2181 .clkr = {
2182 .enable_reg = 0x5200c,
2183 .enable_mask = BIT(23),
2184 .hw.init = &(struct clk_init_data){
2185 .name = "gcc_qupv3_wrap1_s1_clk",
2186 .parent_names = (const char *[]){
2187 "gcc_qupv3_wrap1_s1_clk_src",
2188 },
2189 .num_parents = 1,
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2192 },
2193 },
2194 };
2195
2196 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2197 .halt_reg = 0x18274,
2198 .halt_check = BRANCH_HALT_VOTED,
2199 .clkr = {
2200 .enable_reg = 0x5200c,
2201 .enable_mask = BIT(24),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "gcc_qupv3_wrap1_s2_clk",
2204 .parent_names = (const char *[]){
2205 "gcc_qupv3_wrap1_s2_clk_src",
2206 },
2207 .num_parents = 1,
2208 .flags = CLK_SET_RATE_PARENT,
2209 .ops = &clk_branch2_ops,
2210 },
2211 },
2212 };
2213
2214 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2215 .halt_reg = 0x183a4,
2216 .halt_check = BRANCH_HALT_VOTED,
2217 .clkr = {
2218 .enable_reg = 0x5200c,
2219 .enable_mask = BIT(25),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "gcc_qupv3_wrap1_s3_clk",
2222 .parent_names = (const char *[]){
2223 "gcc_qupv3_wrap1_s3_clk_src",
2224 },
2225 .num_parents = 1,
2226 .flags = CLK_SET_RATE_PARENT,
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230 };
2231
2232 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2233 .halt_reg = 0x184d4,
2234 .halt_check = BRANCH_HALT_VOTED,
2235 .clkr = {
2236 .enable_reg = 0x5200c,
2237 .enable_mask = BIT(26),
2238 .hw.init = &(struct clk_init_data){
2239 .name = "gcc_qupv3_wrap1_s4_clk",
2240 .parent_names = (const char *[]){
2241 "gcc_qupv3_wrap1_s4_clk_src",
2242 },
2243 .num_parents = 1,
2244 .flags = CLK_SET_RATE_PARENT,
2245 .ops = &clk_branch2_ops,
2246 },
2247 },
2248 };
2249
2250 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2251 .halt_reg = 0x18604,
2252 .halt_check = BRANCH_HALT_VOTED,
2253 .clkr = {
2254 .enable_reg = 0x5200c,
2255 .enable_mask = BIT(27),
2256 .hw.init = &(struct clk_init_data){
2257 .name = "gcc_qupv3_wrap1_s5_clk",
2258 .parent_names = (const char *[]){
2259 "gcc_qupv3_wrap1_s5_clk_src",
2260 },
2261 .num_parents = 1,
2262 .flags = CLK_SET_RATE_PARENT,
2263 .ops = &clk_branch2_ops,
2264 },
2265 },
2266 };
2267
2268 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2269 .halt_reg = 0x18734,
2270 .halt_check = BRANCH_HALT_VOTED,
2271 .clkr = {
2272 .enable_reg = 0x5200c,
2273 .enable_mask = BIT(28),
2274 .hw.init = &(struct clk_init_data){
2275 .name = "gcc_qupv3_wrap1_s6_clk",
2276 .parent_names = (const char *[]){
2277 "gcc_qupv3_wrap1_s6_clk_src",
2278 },
2279 .num_parents = 1,
2280 .flags = CLK_SET_RATE_PARENT,
2281 .ops = &clk_branch2_ops,
2282 },
2283 },
2284 };
2285
2286 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2287 .halt_reg = 0x18864,
2288 .halt_check = BRANCH_HALT_VOTED,
2289 .clkr = {
2290 .enable_reg = 0x5200c,
2291 .enable_mask = BIT(29),
2292 .hw.init = &(struct clk_init_data){
2293 .name = "gcc_qupv3_wrap1_s7_clk",
2294 .parent_names = (const char *[]){
2295 "gcc_qupv3_wrap1_s7_clk_src",
2296 },
2297 .num_parents = 1,
2298 .flags = CLK_SET_RATE_PARENT,
2299 .ops = &clk_branch2_ops,
2300 },
2301 },
2302 };
2303
2304 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2305 .halt_reg = 0x17004,
2306 .halt_check = BRANCH_HALT_VOTED,
2307 .clkr = {
2308 .enable_reg = 0x5200c,
2309 .enable_mask = BIT(6),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2312 .ops = &clk_branch2_ops,
2313 },
2314 },
2315 };
2316
2317 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2318 .halt_reg = 0x17008,
2319 .halt_check = BRANCH_HALT_VOTED,
2320 .hwcg_reg = 0x17008,
2321 .hwcg_bit = 1,
2322 .clkr = {
2323 .enable_reg = 0x5200c,
2324 .enable_mask = BIT(7),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2327 .ops = &clk_branch2_ops,
2328 },
2329 },
2330 };
2331
2332 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2333 .halt_reg = 0x1800c,
2334 .halt_check = BRANCH_HALT_VOTED,
2335 .clkr = {
2336 .enable_reg = 0x5200c,
2337 .enable_mask = BIT(20),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2340 .ops = &clk_branch2_ops,
2341 },
2342 },
2343 };
2344
2345 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2346 .halt_reg = 0x18010,
2347 .halt_check = BRANCH_HALT_VOTED,
2348 .hwcg_reg = 0x18010,
2349 .hwcg_bit = 1,
2350 .clkr = {
2351 .enable_reg = 0x5200c,
2352 .enable_mask = BIT(21),
2353 .hw.init = &(struct clk_init_data){
2354 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2355 .ops = &clk_branch2_ops,
2356 },
2357 },
2358 };
2359
2360 static struct clk_branch gcc_sdcc2_ahb_clk = {
2361 .halt_reg = 0x14008,
2362 .halt_check = BRANCH_HALT,
2363 .clkr = {
2364 .enable_reg = 0x14008,
2365 .enable_mask = BIT(0),
2366 .hw.init = &(struct clk_init_data){
2367 .name = "gcc_sdcc2_ahb_clk",
2368 .ops = &clk_branch2_ops,
2369 },
2370 },
2371 };
2372
2373 static struct clk_branch gcc_sdcc2_apps_clk = {
2374 .halt_reg = 0x14004,
2375 .halt_check = BRANCH_HALT,
2376 .clkr = {
2377 .enable_reg = 0x14004,
2378 .enable_mask = BIT(0),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "gcc_sdcc2_apps_clk",
2381 .parent_names = (const char *[]){
2382 "gcc_sdcc2_apps_clk_src",
2383 },
2384 .num_parents = 1,
2385 .flags = CLK_SET_RATE_PARENT,
2386 .ops = &clk_branch2_ops,
2387 },
2388 },
2389 };
2390
2391 static struct clk_branch gcc_sdcc4_ahb_clk = {
2392 .halt_reg = 0x16008,
2393 .halt_check = BRANCH_HALT,
2394 .clkr = {
2395 .enable_reg = 0x16008,
2396 .enable_mask = BIT(0),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "gcc_sdcc4_ahb_clk",
2399 .ops = &clk_branch2_ops,
2400 },
2401 },
2402 };
2403
2404 static struct clk_branch gcc_sdcc4_apps_clk = {
2405 .halt_reg = 0x16004,
2406 .halt_check = BRANCH_HALT,
2407 .clkr = {
2408 .enable_reg = 0x16004,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gcc_sdcc4_apps_clk",
2412 .parent_names = (const char *[]){
2413 "gcc_sdcc4_apps_clk_src",
2414 },
2415 .num_parents = 1,
2416 .flags = CLK_SET_RATE_PARENT,
2417 .ops = &clk_branch2_ops,
2418 },
2419 },
2420 };
2421
2422 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2423 .halt_reg = 0x414c,
2424 .halt_check = BRANCH_HALT_VOTED,
2425 .clkr = {
2426 .enable_reg = 0x52004,
2427 .enable_mask = BIT(0),
2428 .hw.init = &(struct clk_init_data){
2429 .name = "gcc_sys_noc_cpuss_ahb_clk",
2430 .parent_names = (const char *[]){
2431 "gcc_cpuss_ahb_clk_src",
2432 },
2433 .num_parents = 1,
2434 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2435 .ops = &clk_branch2_ops,
2436 },
2437 },
2438 };
2439
2440 static struct clk_branch gcc_tsif_ahb_clk = {
2441 .halt_reg = 0x36004,
2442 .halt_check = BRANCH_HALT,
2443 .clkr = {
2444 .enable_reg = 0x36004,
2445 .enable_mask = BIT(0),
2446 .hw.init = &(struct clk_init_data){
2447 .name = "gcc_tsif_ahb_clk",
2448 .ops = &clk_branch2_ops,
2449 },
2450 },
2451 };
2452
2453 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2454 .halt_reg = 0x3600c,
2455 .halt_check = BRANCH_HALT,
2456 .clkr = {
2457 .enable_reg = 0x3600c,
2458 .enable_mask = BIT(0),
2459 .hw.init = &(struct clk_init_data){
2460 .name = "gcc_tsif_inactivity_timers_clk",
2461 .ops = &clk_branch2_ops,
2462 },
2463 },
2464 };
2465
2466 static struct clk_branch gcc_tsif_ref_clk = {
2467 .halt_reg = 0x36008,
2468 .halt_check = BRANCH_HALT,
2469 .clkr = {
2470 .enable_reg = 0x36008,
2471 .enable_mask = BIT(0),
2472 .hw.init = &(struct clk_init_data){
2473 .name = "gcc_tsif_ref_clk",
2474 .parent_names = (const char *[]){
2475 "gcc_tsif_ref_clk_src",
2476 },
2477 .num_parents = 1,
2478 .flags = CLK_SET_RATE_PARENT,
2479 .ops = &clk_branch2_ops,
2480 },
2481 },
2482 };
2483
2484 static struct clk_branch gcc_ufs_card_ahb_clk = {
2485 .halt_reg = 0x75010,
2486 .halt_check = BRANCH_HALT,
2487 .hwcg_reg = 0x75010,
2488 .hwcg_bit = 1,
2489 .clkr = {
2490 .enable_reg = 0x75010,
2491 .enable_mask = BIT(0),
2492 .hw.init = &(struct clk_init_data){
2493 .name = "gcc_ufs_card_ahb_clk",
2494 .ops = &clk_branch2_ops,
2495 },
2496 },
2497 };
2498
2499 static struct clk_branch gcc_ufs_card_axi_clk = {
2500 .halt_reg = 0x7500c,
2501 .halt_check = BRANCH_HALT,
2502 .hwcg_reg = 0x7500c,
2503 .hwcg_bit = 1,
2504 .clkr = {
2505 .enable_reg = 0x7500c,
2506 .enable_mask = BIT(0),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "gcc_ufs_card_axi_clk",
2509 .parent_names = (const char *[]){
2510 "gcc_ufs_card_axi_clk_src",
2511 },
2512 .num_parents = 1,
2513 .flags = CLK_SET_RATE_PARENT,
2514 .ops = &clk_branch2_ops,
2515 },
2516 },
2517 };
2518
2519 static struct clk_branch gcc_ufs_card_clkref_clk = {
2520 .halt_reg = 0x8c004,
2521 .halt_check = BRANCH_HALT,
2522 .clkr = {
2523 .enable_reg = 0x8c004,
2524 .enable_mask = BIT(0),
2525 .hw.init = &(struct clk_init_data){
2526 .name = "gcc_ufs_card_clkref_clk",
2527 .ops = &clk_branch2_ops,
2528 },
2529 },
2530 };
2531
2532 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2533 .halt_reg = 0x75058,
2534 .halt_check = BRANCH_HALT,
2535 .hwcg_reg = 0x75058,
2536 .hwcg_bit = 1,
2537 .clkr = {
2538 .enable_reg = 0x75058,
2539 .enable_mask = BIT(0),
2540 .hw.init = &(struct clk_init_data){
2541 .name = "gcc_ufs_card_ice_core_clk",
2542 .parent_names = (const char *[]){
2543 "gcc_ufs_card_ice_core_clk_src",
2544 },
2545 .num_parents = 1,
2546 .flags = CLK_SET_RATE_PARENT,
2547 .ops = &clk_branch2_ops,
2548 },
2549 },
2550 };
2551
2552 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2553 .halt_reg = 0x7508c,
2554 .halt_check = BRANCH_HALT,
2555 .hwcg_reg = 0x7508c,
2556 .hwcg_bit = 1,
2557 .clkr = {
2558 .enable_reg = 0x7508c,
2559 .enable_mask = BIT(0),
2560 .hw.init = &(struct clk_init_data){
2561 .name = "gcc_ufs_card_phy_aux_clk",
2562 .parent_names = (const char *[]){
2563 "gcc_ufs_card_phy_aux_clk_src",
2564 },
2565 .num_parents = 1,
2566 .flags = CLK_SET_RATE_PARENT,
2567 .ops = &clk_branch2_ops,
2568 },
2569 },
2570 };
2571
2572 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2573 .halt_check = BRANCH_HALT_SKIP,
2574 .clkr = {
2575 .enable_reg = 0x75018,
2576 .enable_mask = BIT(0),
2577 .hw.init = &(struct clk_init_data){
2578 .name = "gcc_ufs_card_rx_symbol_0_clk",
2579 .ops = &clk_branch2_ops,
2580 },
2581 },
2582 };
2583
2584 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2585 .halt_check = BRANCH_HALT_SKIP,
2586 .clkr = {
2587 .enable_reg = 0x750a8,
2588 .enable_mask = BIT(0),
2589 .hw.init = &(struct clk_init_data){
2590 .name = "gcc_ufs_card_rx_symbol_1_clk",
2591 .ops = &clk_branch2_ops,
2592 },
2593 },
2594 };
2595
2596 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2597 .halt_check = BRANCH_HALT_SKIP,
2598 .clkr = {
2599 .enable_reg = 0x75014,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gcc_ufs_card_tx_symbol_0_clk",
2603 .ops = &clk_branch2_ops,
2604 },
2605 },
2606 };
2607
2608 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2609 .halt_reg = 0x75054,
2610 .halt_check = BRANCH_HALT,
2611 .hwcg_reg = 0x75054,
2612 .hwcg_bit = 1,
2613 .clkr = {
2614 .enable_reg = 0x75054,
2615 .enable_mask = BIT(0),
2616 .hw.init = &(struct clk_init_data){
2617 .name = "gcc_ufs_card_unipro_core_clk",
2618 .parent_names = (const char *[]){
2619 "gcc_ufs_card_unipro_core_clk_src",
2620 },
2621 .num_parents = 1,
2622 .flags = CLK_SET_RATE_PARENT,
2623 .ops = &clk_branch2_ops,
2624 },
2625 },
2626 };
2627
2628 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2629 .halt_reg = 0x8c000,
2630 .halt_check = BRANCH_HALT,
2631 .clkr = {
2632 .enable_reg = 0x8c000,
2633 .enable_mask = BIT(0),
2634 .hw.init = &(struct clk_init_data){
2635 .name = "gcc_ufs_mem_clkref_clk",
2636 .ops = &clk_branch2_ops,
2637 },
2638 },
2639 };
2640
2641 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2642 .halt_reg = 0x77010,
2643 .halt_check = BRANCH_HALT,
2644 .hwcg_reg = 0x77010,
2645 .hwcg_bit = 1,
2646 .clkr = {
2647 .enable_reg = 0x77010,
2648 .enable_mask = BIT(0),
2649 .hw.init = &(struct clk_init_data){
2650 .name = "gcc_ufs_phy_ahb_clk",
2651 .ops = &clk_branch2_ops,
2652 },
2653 },
2654 };
2655
2656 static struct clk_branch gcc_ufs_phy_axi_clk = {
2657 .halt_reg = 0x7700c,
2658 .halt_check = BRANCH_HALT,
2659 .hwcg_reg = 0x7700c,
2660 .hwcg_bit = 1,
2661 .clkr = {
2662 .enable_reg = 0x7700c,
2663 .enable_mask = BIT(0),
2664 .hw.init = &(struct clk_init_data){
2665 .name = "gcc_ufs_phy_axi_clk",
2666 .parent_names = (const char *[]){
2667 "gcc_ufs_phy_axi_clk_src",
2668 },
2669 .num_parents = 1,
2670 .flags = CLK_SET_RATE_PARENT,
2671 .ops = &clk_branch2_ops,
2672 },
2673 },
2674 };
2675
2676 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2677 .halt_reg = 0x77058,
2678 .halt_check = BRANCH_HALT,
2679 .hwcg_reg = 0x77058,
2680 .hwcg_bit = 1,
2681 .clkr = {
2682 .enable_reg = 0x77058,
2683 .enable_mask = BIT(0),
2684 .hw.init = &(struct clk_init_data){
2685 .name = "gcc_ufs_phy_ice_core_clk",
2686 .parent_names = (const char *[]){
2687 "gcc_ufs_phy_ice_core_clk_src",
2688 },
2689 .num_parents = 1,
2690 .flags = CLK_SET_RATE_PARENT,
2691 .ops = &clk_branch2_ops,
2692 },
2693 },
2694 };
2695
2696 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2697 .halt_reg = 0x7708c,
2698 .halt_check = BRANCH_HALT,
2699 .hwcg_reg = 0x7708c,
2700 .hwcg_bit = 1,
2701 .clkr = {
2702 .enable_reg = 0x7708c,
2703 .enable_mask = BIT(0),
2704 .hw.init = &(struct clk_init_data){
2705 .name = "gcc_ufs_phy_phy_aux_clk",
2706 .parent_names = (const char *[]){
2707 "gcc_ufs_phy_phy_aux_clk_src",
2708 },
2709 .num_parents = 1,
2710 .flags = CLK_SET_RATE_PARENT,
2711 .ops = &clk_branch2_ops,
2712 },
2713 },
2714 };
2715
2716 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2717 .halt_check = BRANCH_HALT_SKIP,
2718 .clkr = {
2719 .enable_reg = 0x77018,
2720 .enable_mask = BIT(0),
2721 .hw.init = &(struct clk_init_data){
2722 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2723 .ops = &clk_branch2_ops,
2724 },
2725 },
2726 };
2727
2728 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2729 .halt_check = BRANCH_HALT_SKIP,
2730 .clkr = {
2731 .enable_reg = 0x770a8,
2732 .enable_mask = BIT(0),
2733 .hw.init = &(struct clk_init_data){
2734 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2735 .ops = &clk_branch2_ops,
2736 },
2737 },
2738 };
2739
2740 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2741 .halt_check = BRANCH_HALT_SKIP,
2742 .clkr = {
2743 .enable_reg = 0x77014,
2744 .enable_mask = BIT(0),
2745 .hw.init = &(struct clk_init_data){
2746 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2747 .ops = &clk_branch2_ops,
2748 },
2749 },
2750 };
2751
2752 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2753 .halt_reg = 0x77054,
2754 .halt_check = BRANCH_HALT,
2755 .hwcg_reg = 0x77054,
2756 .hwcg_bit = 1,
2757 .clkr = {
2758 .enable_reg = 0x77054,
2759 .enable_mask = BIT(0),
2760 .hw.init = &(struct clk_init_data){
2761 .name = "gcc_ufs_phy_unipro_core_clk",
2762 .parent_names = (const char *[]){
2763 "gcc_ufs_phy_unipro_core_clk_src",
2764 },
2765 .num_parents = 1,
2766 .flags = CLK_SET_RATE_PARENT,
2767 .ops = &clk_branch2_ops,
2768 },
2769 },
2770 };
2771
2772 static struct clk_branch gcc_usb30_prim_master_clk = {
2773 .halt_reg = 0xf00c,
2774 .halt_check = BRANCH_HALT,
2775 .clkr = {
2776 .enable_reg = 0xf00c,
2777 .enable_mask = BIT(0),
2778 .hw.init = &(struct clk_init_data){
2779 .name = "gcc_usb30_prim_master_clk",
2780 .parent_names = (const char *[]){
2781 "gcc_usb30_prim_master_clk_src",
2782 },
2783 .num_parents = 1,
2784 .flags = CLK_SET_RATE_PARENT,
2785 .ops = &clk_branch2_ops,
2786 },
2787 },
2788 };
2789
2790 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2791 .halt_reg = 0xf014,
2792 .halt_check = BRANCH_HALT,
2793 .clkr = {
2794 .enable_reg = 0xf014,
2795 .enable_mask = BIT(0),
2796 .hw.init = &(struct clk_init_data){
2797 .name = "gcc_usb30_prim_mock_utmi_clk",
2798 .parent_names = (const char *[]){
2799 "gcc_usb30_prim_mock_utmi_clk_src",
2800 },
2801 .num_parents = 1,
2802 .flags = CLK_SET_RATE_PARENT,
2803 .ops = &clk_branch2_ops,
2804 },
2805 },
2806 };
2807
2808 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2809 .halt_reg = 0xf010,
2810 .halt_check = BRANCH_HALT,
2811 .clkr = {
2812 .enable_reg = 0xf010,
2813 .enable_mask = BIT(0),
2814 .hw.init = &(struct clk_init_data){
2815 .name = "gcc_usb30_prim_sleep_clk",
2816 .ops = &clk_branch2_ops,
2817 },
2818 },
2819 };
2820
2821 static struct clk_branch gcc_usb30_sec_master_clk = {
2822 .halt_reg = 0x1000c,
2823 .halt_check = BRANCH_HALT,
2824 .clkr = {
2825 .enable_reg = 0x1000c,
2826 .enable_mask = BIT(0),
2827 .hw.init = &(struct clk_init_data){
2828 .name = "gcc_usb30_sec_master_clk",
2829 .parent_names = (const char *[]){
2830 "gcc_usb30_sec_master_clk_src",
2831 },
2832 .num_parents = 1,
2833 .flags = CLK_SET_RATE_PARENT,
2834 .ops = &clk_branch2_ops,
2835 },
2836 },
2837 };
2838
2839 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2840 .halt_reg = 0x10014,
2841 .halt_check = BRANCH_HALT,
2842 .clkr = {
2843 .enable_reg = 0x10014,
2844 .enable_mask = BIT(0),
2845 .hw.init = &(struct clk_init_data){
2846 .name = "gcc_usb30_sec_mock_utmi_clk",
2847 .parent_names = (const char *[]){
2848 "gcc_usb30_sec_mock_utmi_clk_src",
2849 },
2850 .num_parents = 1,
2851 .flags = CLK_SET_RATE_PARENT,
2852 .ops = &clk_branch2_ops,
2853 },
2854 },
2855 };
2856
2857 static struct clk_branch gcc_usb30_sec_sleep_clk = {
2858 .halt_reg = 0x10010,
2859 .halt_check = BRANCH_HALT,
2860 .clkr = {
2861 .enable_reg = 0x10010,
2862 .enable_mask = BIT(0),
2863 .hw.init = &(struct clk_init_data){
2864 .name = "gcc_usb30_sec_sleep_clk",
2865 .ops = &clk_branch2_ops,
2866 },
2867 },
2868 };
2869
2870 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2871 .halt_reg = 0x8c008,
2872 .halt_check = BRANCH_HALT,
2873 .clkr = {
2874 .enable_reg = 0x8c008,
2875 .enable_mask = BIT(0),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "gcc_usb3_prim_clkref_clk",
2878 .ops = &clk_branch2_ops,
2879 },
2880 },
2881 };
2882
2883 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2884 .halt_reg = 0xf04c,
2885 .halt_check = BRANCH_HALT,
2886 .clkr = {
2887 .enable_reg = 0xf04c,
2888 .enable_mask = BIT(0),
2889 .hw.init = &(struct clk_init_data){
2890 .name = "gcc_usb3_prim_phy_aux_clk",
2891 .parent_names = (const char *[]){
2892 "gcc_usb3_prim_phy_aux_clk_src",
2893 },
2894 .num_parents = 1,
2895 .flags = CLK_SET_RATE_PARENT,
2896 .ops = &clk_branch2_ops,
2897 },
2898 },
2899 };
2900
2901 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2902 .halt_reg = 0xf050,
2903 .halt_check = BRANCH_HALT,
2904 .clkr = {
2905 .enable_reg = 0xf050,
2906 .enable_mask = BIT(0),
2907 .hw.init = &(struct clk_init_data){
2908 .name = "gcc_usb3_prim_phy_com_aux_clk",
2909 .parent_names = (const char *[]){
2910 "gcc_usb3_prim_phy_aux_clk_src",
2911 },
2912 .num_parents = 1,
2913 .flags = CLK_SET_RATE_PARENT,
2914 .ops = &clk_branch2_ops,
2915 },
2916 },
2917 };
2918
2919 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2920 .halt_check = BRANCH_HALT_SKIP,
2921 .clkr = {
2922 .enable_reg = 0xf054,
2923 .enable_mask = BIT(0),
2924 .hw.init = &(struct clk_init_data){
2925 .name = "gcc_usb3_prim_phy_pipe_clk",
2926 .ops = &clk_branch2_ops,
2927 },
2928 },
2929 };
2930
2931 static struct clk_branch gcc_usb3_sec_clkref_clk = {
2932 .halt_reg = 0x8c028,
2933 .halt_check = BRANCH_HALT,
2934 .clkr = {
2935 .enable_reg = 0x8c028,
2936 .enable_mask = BIT(0),
2937 .hw.init = &(struct clk_init_data){
2938 .name = "gcc_usb3_sec_clkref_clk",
2939 .ops = &clk_branch2_ops,
2940 },
2941 },
2942 };
2943
2944 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2945 .halt_reg = 0x1004c,
2946 .halt_check = BRANCH_HALT,
2947 .clkr = {
2948 .enable_reg = 0x1004c,
2949 .enable_mask = BIT(0),
2950 .hw.init = &(struct clk_init_data){
2951 .name = "gcc_usb3_sec_phy_aux_clk",
2952 .parent_names = (const char *[]){
2953 "gcc_usb3_sec_phy_aux_clk_src",
2954 },
2955 .num_parents = 1,
2956 .flags = CLK_SET_RATE_PARENT,
2957 .ops = &clk_branch2_ops,
2958 },
2959 },
2960 };
2961
2962 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2963 .halt_reg = 0x10050,
2964 .halt_check = BRANCH_HALT,
2965 .clkr = {
2966 .enable_reg = 0x10050,
2967 .enable_mask = BIT(0),
2968 .hw.init = &(struct clk_init_data){
2969 .name = "gcc_usb3_sec_phy_com_aux_clk",
2970 .parent_names = (const char *[]){
2971 "gcc_usb3_sec_phy_aux_clk_src",
2972 },
2973 .num_parents = 1,
2974 .flags = CLK_SET_RATE_PARENT,
2975 .ops = &clk_branch2_ops,
2976 },
2977 },
2978 };
2979
2980 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
2981 .halt_check = BRANCH_HALT_SKIP,
2982 .clkr = {
2983 .enable_reg = 0x10054,
2984 .enable_mask = BIT(0),
2985 .hw.init = &(struct clk_init_data){
2986 .name = "gcc_usb3_sec_phy_pipe_clk",
2987 .ops = &clk_branch2_ops,
2988 },
2989 },
2990 };
2991
2992 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2993 .halt_reg = 0x6a004,
2994 .halt_check = BRANCH_HALT,
2995 .hwcg_reg = 0x6a004,
2996 .hwcg_bit = 1,
2997 .clkr = {
2998 .enable_reg = 0x6a004,
2999 .enable_mask = BIT(0),
3000 .hw.init = &(struct clk_init_data){
3001 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
3002 .ops = &clk_branch2_ops,
3003 },
3004 },
3005 };
3006
3007 static struct clk_branch gcc_vdda_vs_clk = {
3008 .halt_reg = 0x7a00c,
3009 .halt_check = BRANCH_HALT,
3010 .clkr = {
3011 .enable_reg = 0x7a00c,
3012 .enable_mask = BIT(0),
3013 .hw.init = &(struct clk_init_data){
3014 .name = "gcc_vdda_vs_clk",
3015 .parent_names = (const char *[]){
3016 "gcc_vsensor_clk_src",
3017 },
3018 .num_parents = 1,
3019 .flags = CLK_SET_RATE_PARENT,
3020 .ops = &clk_branch2_ops,
3021 },
3022 },
3023 };
3024
3025 static struct clk_branch gcc_vddcx_vs_clk = {
3026 .halt_reg = 0x7a004,
3027 .halt_check = BRANCH_HALT,
3028 .clkr = {
3029 .enable_reg = 0x7a004,
3030 .enable_mask = BIT(0),
3031 .hw.init = &(struct clk_init_data){
3032 .name = "gcc_vddcx_vs_clk",
3033 .parent_names = (const char *[]){
3034 "gcc_vsensor_clk_src",
3035 },
3036 .num_parents = 1,
3037 .flags = CLK_SET_RATE_PARENT,
3038 .ops = &clk_branch2_ops,
3039 },
3040 },
3041 };
3042
3043 static struct clk_branch gcc_vddmx_vs_clk = {
3044 .halt_reg = 0x7a008,
3045 .halt_check = BRANCH_HALT,
3046 .clkr = {
3047 .enable_reg = 0x7a008,
3048 .enable_mask = BIT(0),
3049 .hw.init = &(struct clk_init_data){
3050 .name = "gcc_vddmx_vs_clk",
3051 .parent_names = (const char *[]){
3052 "gcc_vsensor_clk_src",
3053 },
3054 .num_parents = 1,
3055 .flags = CLK_SET_RATE_PARENT,
3056 .ops = &clk_branch2_ops,
3057 },
3058 },
3059 };
3060
3061 static struct clk_branch gcc_video_ahb_clk = {
3062 .halt_reg = 0xb004,
3063 .halt_check = BRANCH_HALT,
3064 .hwcg_reg = 0xb004,
3065 .hwcg_bit = 1,
3066 .clkr = {
3067 .enable_reg = 0xb004,
3068 .enable_mask = BIT(0),
3069 .hw.init = &(struct clk_init_data){
3070 .name = "gcc_video_ahb_clk",
3071 .flags = CLK_IS_CRITICAL,
3072 .ops = &clk_branch2_ops,
3073 },
3074 },
3075 };
3076
3077 static struct clk_branch gcc_video_axi_clk = {
3078 .halt_reg = 0xb01c,
3079 .halt_check = BRANCH_VOTED,
3080 .clkr = {
3081 .enable_reg = 0xb01c,
3082 .enable_mask = BIT(0),
3083 .hw.init = &(struct clk_init_data){
3084 .name = "gcc_video_axi_clk",
3085 .ops = &clk_branch2_ops,
3086 },
3087 },
3088 };
3089
3090 static struct clk_branch gcc_video_xo_clk = {
3091 .halt_reg = 0xb028,
3092 .halt_check = BRANCH_HALT,
3093 .clkr = {
3094 .enable_reg = 0xb028,
3095 .enable_mask = BIT(0),
3096 .hw.init = &(struct clk_init_data){
3097 .name = "gcc_video_xo_clk",
3098 .flags = CLK_IS_CRITICAL,
3099 .ops = &clk_branch2_ops,
3100 },
3101 },
3102 };
3103
3104 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3105 .halt_reg = 0x7a014,
3106 .halt_check = BRANCH_HALT,
3107 .hwcg_reg = 0x7a014,
3108 .hwcg_bit = 1,
3109 .clkr = {
3110 .enable_reg = 0x7a014,
3111 .enable_mask = BIT(0),
3112 .hw.init = &(struct clk_init_data){
3113 .name = "gcc_vs_ctrl_ahb_clk",
3114 .ops = &clk_branch2_ops,
3115 },
3116 },
3117 };
3118
3119 static struct clk_branch gcc_vs_ctrl_clk = {
3120 .halt_reg = 0x7a010,
3121 .halt_check = BRANCH_HALT,
3122 .clkr = {
3123 .enable_reg = 0x7a010,
3124 .enable_mask = BIT(0),
3125 .hw.init = &(struct clk_init_data){
3126 .name = "gcc_vs_ctrl_clk",
3127 .parent_names = (const char *[]){
3128 "gcc_vs_ctrl_clk_src",
3129 },
3130 .num_parents = 1,
3131 .flags = CLK_SET_RATE_PARENT,
3132 .ops = &clk_branch2_ops,
3133 },
3134 },
3135 };
3136
3137 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
3138 .halt_reg = 0x48190,
3139 .halt_check = BRANCH_HALT,
3140 .clkr = {
3141 .enable_reg = 0x48190,
3142 .enable_mask = BIT(0),
3143 .hw.init = &(struct clk_init_data){
3144 .name = "gcc_cpuss_dvm_bus_clk",
3145 .flags = CLK_IS_CRITICAL,
3146 .ops = &clk_branch2_ops,
3147 },
3148 },
3149 };
3150
3151 static struct clk_branch gcc_cpuss_gnoc_clk = {
3152 .halt_reg = 0x48004,
3153 .halt_check = BRANCH_HALT_VOTED,
3154 .hwcg_reg = 0x48004,
3155 .hwcg_bit = 1,
3156 .clkr = {
3157 .enable_reg = 0x52004,
3158 .enable_mask = BIT(22),
3159 .hw.init = &(struct clk_init_data){
3160 .name = "gcc_cpuss_gnoc_clk",
3161 .flags = CLK_IS_CRITICAL,
3162 .ops = &clk_branch2_ops,
3163 },
3164 },
3165 };
3166
3167
3168 #ifdef CONFIG_SDM_LPASSCC_845
3169 static struct clk_branch gcc_lpass_q6_axi_clk = {
3170 .halt_reg = 0x47000,
3171 .halt_check = BRANCH_HALT,
3172 .clkr = {
3173 .enable_reg = 0x47000,
3174 .enable_mask = BIT(0),
3175 .hw.init = &(struct clk_init_data){
3176 .name = "gcc_lpass_q6_axi_clk",
3177 .flags = CLK_IS_CRITICAL,
3178 .ops = &clk_branch2_ops,
3179 },
3180 },
3181 };
3182
3183 static struct clk_branch gcc_lpass_sway_clk = {
3184 .halt_reg = 0x47008,
3185 .halt_check = BRANCH_HALT,
3186 .clkr = {
3187 .enable_reg = 0x47008,
3188 .enable_mask = BIT(0),
3189 .hw.init = &(struct clk_init_data){
3190 .name = "gcc_lpass_sway_clk",
3191 .flags = CLK_IS_CRITICAL,
3192 .ops = &clk_branch2_ops,
3193 },
3194 },
3195 };
3196 #endif
3197
3198 static struct gdsc pcie_0_gdsc = {
3199 .gdscr = 0x6b004,
3200 .pd = {
3201 .name = "pcie_0_gdsc",
3202 },
3203 .pwrsts = PWRSTS_OFF_ON,
3204 .flags = POLL_CFG_GDSCR,
3205 };
3206
3207 static struct gdsc pcie_1_gdsc = {
3208 .gdscr = 0x8d004,
3209 .pd = {
3210 .name = "pcie_1_gdsc",
3211 },
3212 .pwrsts = PWRSTS_OFF_ON,
3213 .flags = POLL_CFG_GDSCR,
3214 };
3215
3216 static struct gdsc ufs_card_gdsc = {
3217 .gdscr = 0x75004,
3218 .pd = {
3219 .name = "ufs_card_gdsc",
3220 },
3221 .pwrsts = PWRSTS_OFF_ON,
3222 .flags = POLL_CFG_GDSCR,
3223 };
3224
3225 static struct gdsc ufs_phy_gdsc = {
3226 .gdscr = 0x77004,
3227 .pd = {
3228 .name = "ufs_phy_gdsc",
3229 },
3230 .pwrsts = PWRSTS_OFF_ON,
3231 .flags = POLL_CFG_GDSCR,
3232 };
3233
3234 static struct gdsc usb30_prim_gdsc = {
3235 .gdscr = 0xf004,
3236 .pd = {
3237 .name = "usb30_prim_gdsc",
3238 },
3239 .pwrsts = PWRSTS_OFF_ON,
3240 .flags = POLL_CFG_GDSCR,
3241 };
3242
3243 static struct gdsc usb30_sec_gdsc = {
3244 .gdscr = 0x10004,
3245 .pd = {
3246 .name = "usb30_sec_gdsc",
3247 },
3248 .pwrsts = PWRSTS_OFF_ON,
3249 .flags = POLL_CFG_GDSCR,
3250 };
3251
3252 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3253 .gdscr = 0x7d030,
3254 .pd = {
3255 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3256 },
3257 .pwrsts = PWRSTS_OFF_ON,
3258 .flags = VOTABLE,
3259 };
3260
3261 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3262 .gdscr = 0x7d03c,
3263 .pd = {
3264 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3265 },
3266 .pwrsts = PWRSTS_OFF_ON,
3267 .flags = VOTABLE,
3268 };
3269
3270 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3271 .gdscr = 0x7d034,
3272 .pd = {
3273 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3274 },
3275 .pwrsts = PWRSTS_OFF_ON,
3276 .flags = VOTABLE,
3277 };
3278
3279 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3280 .gdscr = 0x7d038,
3281 .pd = {
3282 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3283 },
3284 .pwrsts = PWRSTS_OFF_ON,
3285 .flags = VOTABLE,
3286 };
3287
3288 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3289 .gdscr = 0x7d040,
3290 .pd = {
3291 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3292 },
3293 .pwrsts = PWRSTS_OFF_ON,
3294 .flags = VOTABLE,
3295 };
3296
3297 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3298 .gdscr = 0x7d048,
3299 .pd = {
3300 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3301 },
3302 .pwrsts = PWRSTS_OFF_ON,
3303 .flags = VOTABLE,
3304 };
3305
3306 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3307 .gdscr = 0x7d044,
3308 .pd = {
3309 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3310 },
3311 .pwrsts = PWRSTS_OFF_ON,
3312 .flags = VOTABLE,
3313 };
3314
3315 static struct clk_regmap *gcc_sdm845_clocks[] = {
3316 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3317 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3318 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3319 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3320 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3321 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3322 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3323 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3324 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3325 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3326 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3327 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3328 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3329 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3330 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3331 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3332 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3333 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3334 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3335 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3336 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3337 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3338 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3339 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3340 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3341 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3342 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3343 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3344 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3345 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3346 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3347 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3348 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3349 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3350 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3351 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3352 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3353 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3354 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3355 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3356 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3357 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3358 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3359 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3360 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3361 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3362 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3363 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3364 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3365 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3366 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3367 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3368 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3369 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3370 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3371 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3372 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3373 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3374 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3375 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3376 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3377 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3378 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3379 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3380 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3381 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3382 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3383 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3384 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3385 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3386 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3387 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3388 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3389 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3390 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3391 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3392 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3393 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3394 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3395 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3396 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3397 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3398 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3399 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3400 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3401 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3402 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3403 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3404 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3405 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3406 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3407 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3408 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3409 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3410 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3411 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3412 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3413 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3414 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3415 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3416 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3417 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3418 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3419 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3420 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3421 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3422 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3423 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3424 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3425 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3426 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3427 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3428 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3429 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3430 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3431 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3432 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3433 &gcc_tsif_inactivity_timers_clk.clkr,
3434 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3435 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3436 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3437 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3438 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3439 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3440 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3441 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3442 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3443 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3444 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3445 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3446 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3447 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3448 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3449 &gcc_ufs_card_unipro_core_clk_src.clkr,
3450 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3451 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3452 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3453 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3454 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3455 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3456 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3457 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3458 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3459 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3460 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3461 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3462 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3463 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3464 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3465 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3466 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3467 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3468 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3469 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3470 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3471 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3472 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3473 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3474 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3475 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3476 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3477 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3478 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3479 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3480 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3481 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3482 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3483 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3484 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3485 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3486 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3487 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3488 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3489 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3490 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3491 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3492 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3493 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3494 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3495 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3496 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3497 [GPLL0] = &gpll0.clkr,
3498 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3499 [GPLL4] = &gpll4.clkr,
3500 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3501 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3502 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3503 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3504 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3505 #ifdef CONFIG_SDM_LPASSCC_845
3506 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
3507 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3508 #endif
3509 };
3510
3511 static const struct qcom_reset_map gcc_sdm845_resets[] = {
3512 [GCC_MMSS_BCR] = { 0xb000 },
3513 [GCC_PCIE_0_BCR] = { 0x6b000 },
3514 [GCC_PCIE_1_BCR] = { 0x8d000 },
3515 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3516 [GCC_PDM_BCR] = { 0x33000 },
3517 [GCC_PRNG_BCR] = { 0x34000 },
3518 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3519 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3520 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3521 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3522 [GCC_SDCC2_BCR] = { 0x14000 },
3523 [GCC_SDCC4_BCR] = { 0x16000 },
3524 [GCC_TSIF_BCR] = { 0x36000 },
3525 [GCC_UFS_CARD_BCR] = { 0x75000 },
3526 [GCC_UFS_PHY_BCR] = { 0x77000 },
3527 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3528 [GCC_USB30_SEC_BCR] = { 0x10000 },
3529 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3530 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3531 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3532 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3533 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3534 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3535 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3536 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3537 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3538 };
3539
3540 static struct gdsc *gcc_sdm845_gdscs[] = {
3541 [PCIE_0_GDSC] = &pcie_0_gdsc,
3542 [PCIE_1_GDSC] = &pcie_1_gdsc,
3543 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3544 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3545 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3546 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3547 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3548 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3549 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3550 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3551 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3552 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3553 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3554 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3555 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3556 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3557 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3558 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3559 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3560 };
3561
3562 static const struct regmap_config gcc_sdm845_regmap_config = {
3563 .reg_bits = 32,
3564 .reg_stride = 4,
3565 .val_bits = 32,
3566 .max_register = 0x182090,
3567 .fast_io = true,
3568 };
3569
3570 static const struct qcom_cc_desc gcc_sdm845_desc = {
3571 .config = &gcc_sdm845_regmap_config,
3572 .clks = gcc_sdm845_clocks,
3573 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3574 .resets = gcc_sdm845_resets,
3575 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3576 .gdscs = gcc_sdm845_gdscs,
3577 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3578 };
3579
3580 static const struct of_device_id gcc_sdm845_match_table[] = {
3581 { .compatible = "qcom,gcc-sdm845" },
3582 { }
3583 };
3584 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3585
3586 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3587 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
3588 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
3589 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
3590 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
3591 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
3592 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
3593 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
3594 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
3595 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
3596 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
3597 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
3598 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
3599 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
3600 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
3601 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
3602 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
3603 };
3604
3605 static int gcc_sdm845_probe(struct platform_device *pdev)
3606 {
3607 struct regmap *regmap;
3608 int ret;
3609
3610 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
3611 if (IS_ERR(regmap))
3612 return PTR_ERR(regmap);
3613
3614
3615 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
3616 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3617
3618 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3619 ARRAY_SIZE(gcc_dfs_clocks));
3620 if (ret)
3621 return ret;
3622
3623 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
3624 }
3625
3626 static struct platform_driver gcc_sdm845_driver = {
3627 .probe = gcc_sdm845_probe,
3628 .driver = {
3629 .name = "gcc-sdm845",
3630 .of_match_table = gcc_sdm845_match_table,
3631 },
3632 };
3633
3634 static int __init gcc_sdm845_init(void)
3635 {
3636 return platform_driver_register(&gcc_sdm845_driver);
3637 }
3638 subsys_initcall(gcc_sdm845_init);
3639
3640 static void __exit gcc_sdm845_exit(void)
3641 {
3642 platform_driver_unregister(&gcc_sdm845_driver);
3643 }
3644 module_exit(gcc_sdm845_exit);
3645
3646 MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
3647 MODULE_LICENSE("GPL v2");
3648 MODULE_ALIAS("platform:gcc-sdm845");