This source file includes following definitions.
- tegra210_xusb_pll_hw_control_enable
- tegra210_xusb_pll_hw_sequence_start
- tegra210_sata_pll_hw_control_enable
- tegra210_sata_pll_hw_sequence_start
- tegra210_set_sata_pll_seq_sw
- tegra210_generic_mbist_war
- tegra210_venc_mbist_war
- tegra210_disp_mbist_war
- tegra210_vic_mbist_war
- tegra210_ape_mbist_war
- _pll_misc_chk_default
- pllcx_check_defaults
- tegra210_pllcx_set_defaults
- _pllc_set_defaults
- _pllc2_set_defaults
- _pllc3_set_defaults
- _plla1_set_defaults
- tegra210_plla_set_defaults
- tegra210_plld_set_defaults
- plldss_defaults
- tegra210_plld2_set_defaults
- tegra210_plldp_set_defaults
- tegra210_pllc4_set_defaults
- tegra210_pllre_set_defaults
- pllx_get_dyn_steps
- pllx_check_defaults
- tegra210_pllx_set_defaults
- tegra210_pllmb_set_defaults
- pllp_check_defaults
- tegra210_pllp_set_defaults
- pllu_check_defaults
- tegra210_pllu_set_defaults
- tegra210_wait_for_mask
- tegra210_pllx_dyn_ramp
- tegra210_pll_fixed_mdiv_cfg
- tegra210_clk_pll_set_gain
- tegra210_clk_adjust_vco_min
- pll_qlin_p_to_pdiv
- pll_expo_p_to_pdiv
- tegra210_clk_handle_mbist_war
- tegra210_put_utmipll_in_iddq
- tegra210_put_utmipll_out_iddq
- tegra210_utmi_param_configure
- tegra210_enable_pllu
- tegra210_init_pllu
- tegra210_periph_clk_init
- tegra210_pll_init
- tegra210_wait_cpu_in_reset
- tegra210_disable_cpu_clock
- tegra210_cpu_clock_suspend
- tegra210_cpu_clock_resume
- tegra210_clock_apply_init_table
- tegra210_car_barrier
- tegra210_clock_assert_dfll_dvco_reset
- tegra210_clock_deassert_dfll_dvco_reset
- tegra210_reset_assert
- tegra210_reset_deassert
- tegra210_mbist_clk_init
- tegra210_clock_init
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5
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/delay.h>
13 #include <linux/export.h>
14 #include <linux/mutex.h>
15 #include <linux/clk/tegra.h>
16 #include <dt-bindings/clock/tegra210-car.h>
17 #include <dt-bindings/reset/tegra210-car.h>
18 #include <linux/iopoll.h>
19 #include <linux/sizes.h>
20 #include <soc/tegra/pmc.h>
21
22 #include "clk.h"
23 #include "clk-id.h"
24
25
26
27
28
29
30
31 #define TEGRA210_CAR_BANK_COUNT 7
32
33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_LA 0x1f8
37 #define CLK_SOURCE_SDMMC2 0x154
38 #define CLK_SOURCE_SDMMC4 0x164
39
40 #define PLLC_BASE 0x80
41 #define PLLC_OUT 0x84
42 #define PLLC_MISC0 0x88
43 #define PLLC_MISC1 0x8c
44 #define PLLC_MISC2 0x5d0
45 #define PLLC_MISC3 0x5d4
46
47 #define PLLC2_BASE 0x4e8
48 #define PLLC2_MISC0 0x4ec
49 #define PLLC2_MISC1 0x4f0
50 #define PLLC2_MISC2 0x4f4
51 #define PLLC2_MISC3 0x4f8
52
53 #define PLLC3_BASE 0x4fc
54 #define PLLC3_MISC0 0x500
55 #define PLLC3_MISC1 0x504
56 #define PLLC3_MISC2 0x508
57 #define PLLC3_MISC3 0x50c
58
59 #define PLLM_BASE 0x90
60 #define PLLM_MISC1 0x98
61 #define PLLM_MISC2 0x9c
62 #define PLLP_BASE 0xa0
63 #define PLLP_MISC0 0xac
64 #define PLLP_MISC1 0x680
65 #define PLLA_BASE 0xb0
66 #define PLLA_MISC0 0xbc
67 #define PLLA_MISC1 0xb8
68 #define PLLA_MISC2 0x5d8
69 #define PLLD_BASE 0xd0
70 #define PLLD_MISC0 0xdc
71 #define PLLD_MISC1 0xd8
72 #define PLLU_BASE 0xc0
73 #define PLLU_OUTA 0xc4
74 #define PLLU_MISC0 0xcc
75 #define PLLU_MISC1 0xc8
76 #define PLLX_BASE 0xe0
77 #define PLLX_MISC0 0xe4
78 #define PLLX_MISC1 0x510
79 #define PLLX_MISC2 0x514
80 #define PLLX_MISC3 0x518
81 #define PLLX_MISC4 0x5f0
82 #define PLLX_MISC5 0x5f4
83 #define PLLE_BASE 0xe8
84 #define PLLE_MISC0 0xec
85 #define PLLD2_BASE 0x4b8
86 #define PLLD2_MISC0 0x4bc
87 #define PLLD2_MISC1 0x570
88 #define PLLD2_MISC2 0x574
89 #define PLLD2_MISC3 0x578
90 #define PLLE_AUX 0x48c
91 #define PLLRE_BASE 0x4c4
92 #define PLLRE_MISC0 0x4c8
93 #define PLLRE_OUT1 0x4cc
94 #define PLLDP_BASE 0x590
95 #define PLLDP_MISC 0x594
96
97 #define PLLC4_BASE 0x5a4
98 #define PLLC4_MISC0 0x5a8
99 #define PLLC4_OUT 0x5e4
100 #define PLLMB_BASE 0x5e8
101 #define PLLMB_MISC1 0x5ec
102 #define PLLA1_BASE 0x6a4
103 #define PLLA1_MISC0 0x6a8
104 #define PLLA1_MISC1 0x6ac
105 #define PLLA1_MISC2 0x6b0
106 #define PLLA1_MISC3 0x6b4
107
108 #define PLLU_IDDQ_BIT 31
109 #define PLLCX_IDDQ_BIT 27
110 #define PLLRE_IDDQ_BIT 24
111 #define PLLA_IDDQ_BIT 25
112 #define PLLD_IDDQ_BIT 20
113 #define PLLSS_IDDQ_BIT 18
114 #define PLLM_IDDQ_BIT 5
115 #define PLLMB_IDDQ_BIT 17
116 #define PLLXP_IDDQ_BIT 3
117
118 #define PLLCX_RESET_BIT 30
119
120 #define PLL_BASE_LOCK BIT(27)
121 #define PLLCX_BASE_LOCK BIT(26)
122 #define PLLE_MISC_LOCK BIT(11)
123 #define PLLRE_MISC_LOCK BIT(27)
124
125 #define PLL_MISC_LOCK_ENABLE 18
126 #define PLLC_MISC_LOCK_ENABLE 24
127 #define PLLDU_MISC_LOCK_ENABLE 22
128 #define PLLU_MISC_LOCK_ENABLE 29
129 #define PLLE_MISC_LOCK_ENABLE 9
130 #define PLLRE_MISC_LOCK_ENABLE 30
131 #define PLLSS_MISC_LOCK_ENABLE 30
132 #define PLLP_MISC_LOCK_ENABLE 18
133 #define PLLM_MISC_LOCK_ENABLE 4
134 #define PLLMB_MISC_LOCK_ENABLE 16
135 #define PLLA_MISC_LOCK_ENABLE 28
136 #define PLLU_MISC_LOCK_ENABLE 29
137 #define PLLD_MISC_LOCK_ENABLE 18
138
139 #define PLLA_SDM_DIN_MASK 0xffff
140 #define PLLA_SDM_EN_MASK BIT(26)
141
142 #define PLLD_SDM_EN_MASK BIT(16)
143
144 #define PLLD2_SDM_EN_MASK BIT(31)
145 #define PLLD2_SSC_EN_MASK 0
146
147 #define PLLDP_SS_CFG 0x598
148 #define PLLDP_SDM_EN_MASK BIT(31)
149 #define PLLDP_SSC_EN_MASK BIT(30)
150 #define PLLDP_SS_CTRL1 0x59c
151 #define PLLDP_SS_CTRL2 0x5a0
152
153 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
154 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
155
156 #define UTMIP_PLL_CFG2 0x488
157 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
158 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
159 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
160 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
162 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
163 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
164 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
165 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
166 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
167
168 #define UTMIP_PLL_CFG1 0x484
169 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
170 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
171 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
172 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
173 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
174 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
175 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
176
177 #define SATA_PLL_CFG0 0x490
178 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
179 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
180 #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
181 #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
182 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
183 #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
184
185 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
186 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
187
188 #define XUSBIO_PLL_CFG0 0x51c
189 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
190 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
191 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
192 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
193 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
194
195 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
196 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
197 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
198 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
199 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
200 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
201 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
202 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
203 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
204 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
205 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
206
207 #define PLLU_HW_PWRDN_CFG0 0x530
208 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
209 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
210 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
211 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
212 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
213 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
214
215 #define XUSB_PLL_CFG0 0x534
216 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
217 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
218
219 #define SPARE_REG0 0x55c
220 #define CLK_M_DIVISOR_SHIFT 2
221 #define CLK_M_DIVISOR_MASK 0x3
222
223 #define RST_DFLL_DVCO 0x2f4
224 #define DVFS_DFLL_RESET_SHIFT 0
225
226 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
227 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
228
229 #define LVL2_CLK_GATE_OVRA 0xf8
230 #define LVL2_CLK_GATE_OVRC 0x3a0
231 #define LVL2_CLK_GATE_OVRD 0x3a4
232 #define LVL2_CLK_GATE_OVRE 0x554
233
234
235 #define TEGRA210_I2S_BASE 0x1000
236 #define TEGRA210_I2S_SIZE 0x100
237 #define TEGRA210_I2S_CTRLS 5
238 #define TEGRA210_I2S_CG 0x88
239 #define TEGRA210_I2S_CTRL 0xa0
240
241
242 #define DC_CMD_DISPLAY_COMMAND 0xc8
243 #define DC_COM_DSC_TOP_CTL 0xcf8
244
245
246 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
247
248
249 #define TEGRA210_AHUB_BASE 0x702d0000
250 #define TEGRA210_DISPA_BASE 0x54200000
251 #define TEGRA210_VIC_BASE 0x54340000
252
253
254
255
256
257
258
259
260
261 #define PLL_SDM_COEFF BIT(13)
262 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
263 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
264
265 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
266 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
267
268
269 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
270
271 #ifdef CONFIG_PM_SLEEP
272 static struct cpu_clk_suspend_context {
273 u32 clk_csite_src;
274 } tegra210_cpu_clk_sctx;
275 #endif
276
277 struct tegra210_domain_mbist_war {
278 void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);
279 const u32 lvl2_offset;
280 const u32 lvl2_mask;
281 const unsigned int num_clks;
282 const unsigned int *clk_init_data;
283 struct clk_bulk_data *clks;
284 };
285
286 static struct clk **clks;
287
288 static void __iomem *clk_base;
289 static void __iomem *pmc_base;
290 static void __iomem *ahub_base;
291 static void __iomem *dispa_base;
292 static void __iomem *vic_base;
293
294 static unsigned long osc_freq;
295 static unsigned long pll_ref_freq;
296
297 static DEFINE_SPINLOCK(pll_d_lock);
298 static DEFINE_SPINLOCK(pll_e_lock);
299 static DEFINE_SPINLOCK(pll_re_lock);
300 static DEFINE_SPINLOCK(pll_u_lock);
301 static DEFINE_SPINLOCK(sor1_lock);
302 static DEFINE_SPINLOCK(emc_lock);
303 static DEFINE_MUTEX(lvl2_ovr_lock);
304
305
306 static unsigned long tegra210_input_freq[] = {
307 [5] = 38400000,
308 [8] = 12000000,
309 };
310
311 static const char *mux_pllmcp_clkm[] = {
312 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
313 "pll_p",
314 };
315 #define mux_pllmcp_clkm_idx NULL
316
317 #define PLL_ENABLE (1 << 30)
318
319 #define PLLCX_MISC1_IDDQ (1 << 27)
320 #define PLLCX_MISC0_RESET (1 << 30)
321
322 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
323 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
324 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
325 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
326 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
327 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
328 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
329 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
330
331
332 #define PLLA_BASE_IDDQ (1 << 25)
333 #define PLLA_BASE_LOCK (1 << 27)
334
335 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
336 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
337
338 #define PLLA_MISC2_EN_SDM (1 << 26)
339 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
340
341 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
342 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
343 #define PLLA_MISC2_DEFAULT_VALUE 0x0
344 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
345
346
347 #define PLLD_BASE_CSI_CLKSOURCE (1 << 23)
348
349 #define PLLD_MISC0_EN_SDM (1 << 16)
350 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
351 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
352 #define PLLD_MISC0_IDDQ (1 << 20)
353 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
354
355 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
356 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
357 #define PLLD_MISC1_DEFAULT_VALUE 0x20
358 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
359
360
361 #define PLLDSS_BASE_LOCK (1 << 27)
362 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
363 #define PLLDSS_BASE_IDDQ (1 << 18)
364 #define PLLDSS_BASE_REF_SEL_SHIFT 25
365 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
366
367 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
368
369 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
370 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
371
372 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
373 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
374 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
375 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
376
377 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
378 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
379 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
380 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
381
382 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
383 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
384 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
385 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
386
387 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
388
389
390 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
391 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
392 #define PLLRE_MISC0_LOCK (1 << 27)
393 #define PLLRE_MISC0_IDDQ (1 << 24)
394
395 #define PLLRE_BASE_DEFAULT_VALUE 0x0
396 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
397
398 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
399 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
400
401
402 #define PLLX_USE_DYN_RAMP 1
403 #define PLLX_BASE_LOCK (1 << 27)
404
405 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
406 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
407
408 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
409 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
410 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
411 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
412 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
413 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
414 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
415 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
416 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
417
418 #define PLLX_MISC3_IDDQ (0x1 << 3)
419
420 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
421 #define PLLX_MISC0_WRITE_MASK 0x10c40000
422 #define PLLX_MISC1_DEFAULT_VALUE 0x20
423 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
424 #define PLLX_MISC2_DEFAULT_VALUE 0x0
425 #define PLLX_MISC2_WRITE_MASK 0xffffff11
426 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
427 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
428 #define PLLX_MISC4_DEFAULT_VALUE 0x0
429 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
430 #define PLLX_MISC5_DEFAULT_VALUE 0x0
431 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
432
433 #define PLLX_HW_CTRL_CFG 0x548
434 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
435
436
437 #define PLLMB_BASE_LOCK (1 << 27)
438
439 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
440 #define PLLMB_MISC1_IDDQ (1 << 17)
441 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
442
443 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
444 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
445
446
447 #define PLLP_BASE_OVERRIDE (1 << 28)
448 #define PLLP_BASE_LOCK (1 << 27)
449
450 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
451 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
452 #define PLLP_MISC0_IDDQ (1 << 3)
453
454 #define PLLP_MISC1_HSIO_EN_SHIFT 29
455 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
456 #define PLLP_MISC1_XUSB_EN_SHIFT 28
457 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
458
459 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
460 #define PLLP_MISC1_DEFAULT_VALUE 0x0
461
462 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
463 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
464
465
466 #define PLLU_BASE_LOCK (1 << 27)
467 #define PLLU_BASE_OVERRIDE (1 << 24)
468 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
469 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
470 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
471 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
472 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
473 PLLU_BASE_CLKENABLE_HSIC |\
474 PLLU_BASE_CLKENABLE_ICUSB |\
475 PLLU_BASE_CLKENABLE_48M)
476
477 #define PLLU_MISC0_IDDQ (1 << 31)
478 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
479 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
480
481 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
482 #define PLLU_MISC1_DEFAULT_VALUE 0x0
483
484 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
485 #define PLLU_MISC1_WRITE_MASK 0x00000007
486
487 void tegra210_xusb_pll_hw_control_enable(void)
488 {
489 u32 val;
490
491 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
492 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
493 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
494 val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
495 XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
496 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
497 }
498 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);
499
500 void tegra210_xusb_pll_hw_sequence_start(void)
501 {
502 u32 val;
503
504 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
505 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
506 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
507 }
508 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);
509
510 void tegra210_sata_pll_hw_control_enable(void)
511 {
512 u32 val;
513
514 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
515 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
516 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |
517 SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
518 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
519 }
520 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);
521
522 void tegra210_sata_pll_hw_sequence_start(void)
523 {
524 u32 val;
525
526 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
527 val |= SATA_PLL_CFG0_SEQ_ENABLE;
528 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
529 }
530 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
531
532 void tegra210_set_sata_pll_seq_sw(bool state)
533 {
534 u32 val;
535
536 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
537 if (state) {
538 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
539 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
540 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
541 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
542 } else {
543 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
544 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
545 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
546 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
547 }
548 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
549 }
550 EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
551
552 static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
553 {
554 u32 val;
555
556 val = readl_relaxed(clk_base + mbist->lvl2_offset);
557 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
558 fence_udelay(1, clk_base);
559 writel_relaxed(val, clk_base + mbist->lvl2_offset);
560 fence_udelay(1, clk_base);
561 }
562
563 static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)
564 {
565 u32 csi_src, ovra, ovre;
566 unsigned long flags = 0;
567
568 spin_lock_irqsave(&pll_d_lock, flags);
569
570 csi_src = readl_relaxed(clk_base + PLLD_BASE);
571 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
572 fence_udelay(1, clk_base);
573
574 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
575 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
576 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
577 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
578 fence_udelay(1, clk_base);
579
580 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
581 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
582 writel_relaxed(csi_src, clk_base + PLLD_BASE);
583 fence_udelay(1, clk_base);
584
585 spin_unlock_irqrestore(&pll_d_lock, flags);
586 }
587
588 static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)
589 {
590 u32 ovra, dsc_top_ctrl;
591
592 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
593 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
594 fence_udelay(1, clk_base);
595
596 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
597 writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
598 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
599 writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
600 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
601
602 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
603 fence_udelay(1, clk_base);
604 }
605
606 static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)
607 {
608 u32 ovre, val;
609
610 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
611 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
612 fence_udelay(1, clk_base);
613
614 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
615 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
616 vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
617 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
618
619 writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
620 readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
621
622 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
623 fence_udelay(1, clk_base);
624 }
625
626 static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)
627 {
628 void __iomem *i2s_base;
629 unsigned int i;
630 u32 ovrc, ovre;
631
632 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
633 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
634 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
635 writel_relaxed(ovre | BIT(10) | BIT(11),
636 clk_base + LVL2_CLK_GATE_OVRE);
637 fence_udelay(1, clk_base);
638
639 i2s_base = ahub_base + TEGRA210_I2S_BASE;
640
641 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {
642 u32 i2s_ctrl;
643
644 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
645 writel_relaxed(i2s_ctrl | BIT(10),
646 i2s_base + TEGRA210_I2S_CTRL);
647 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
648 readl(i2s_base + TEGRA210_I2S_CG);
649 writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
650 writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
651 readl(i2s_base + TEGRA210_I2S_CTRL);
652
653 i2s_base += TEGRA210_I2S_SIZE;
654 }
655
656 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
657 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
658 fence_udelay(1, clk_base);
659 }
660
661 static inline void _pll_misc_chk_default(void __iomem *base,
662 struct tegra_clk_pll_params *params,
663 u8 misc_num, u32 default_val, u32 mask)
664 {
665 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
666
667 boot_val &= mask;
668 default_val &= mask;
669 if (boot_val != default_val) {
670 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
671 misc_num, boot_val, default_val);
672 pr_warn(" (comparison mask = 0x%x)\n", mask);
673 params->defaults_set = false;
674 }
675 }
676
677
678
679
680
681
682 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
683 {
684 u32 default_val;
685
686 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
687 _pll_misc_chk_default(clk_base, params, 0, default_val,
688 PLLCX_MISC0_WRITE_MASK);
689
690 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
691 _pll_misc_chk_default(clk_base, params, 1, default_val,
692 PLLCX_MISC1_WRITE_MASK);
693
694 default_val = PLLCX_MISC2_DEFAULT_VALUE;
695 _pll_misc_chk_default(clk_base, params, 2, default_val,
696 PLLCX_MISC2_WRITE_MASK);
697
698 default_val = PLLCX_MISC3_DEFAULT_VALUE;
699 _pll_misc_chk_default(clk_base, params, 3, default_val,
700 PLLCX_MISC3_WRITE_MASK);
701 }
702
703 static void tegra210_pllcx_set_defaults(const char *name,
704 struct tegra_clk_pll *pllcx)
705 {
706 pllcx->params->defaults_set = true;
707
708 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
709
710 pllcx_check_defaults(pllcx->params);
711 if (!pllcx->params->defaults_set)
712 pr_warn("%s already enabled. Postponing set full defaults\n",
713 name);
714 return;
715 }
716
717
718 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
719 clk_base + pllcx->params->ext_misc_reg[0]);
720 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
721 clk_base + pllcx->params->ext_misc_reg[1]);
722 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
723 clk_base + pllcx->params->ext_misc_reg[2]);
724 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
725 clk_base + pllcx->params->ext_misc_reg[3]);
726 udelay(1);
727 }
728
729 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
730 {
731 tegra210_pllcx_set_defaults("PLL_C", pllcx);
732 }
733
734 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
735 {
736 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
737 }
738
739 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
740 {
741 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
742 }
743
744 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
745 {
746 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
747 }
748
749
750
751
752
753
754 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
755 {
756 u32 mask;
757 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
758
759 plla->params->defaults_set = true;
760
761 if (val & PLL_ENABLE) {
762
763
764
765
766 if (val & PLLA_BASE_IDDQ) {
767 pr_warn("PLL_A boot enabled with IDDQ set\n");
768 plla->params->defaults_set = false;
769 }
770
771 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
772
773 val = PLLA_MISC0_DEFAULT_VALUE;
774 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
775 _pll_misc_chk_default(clk_base, plla->params, 0, val,
776 ~mask & PLLA_MISC0_WRITE_MASK);
777
778 val = PLLA_MISC2_DEFAULT_VALUE;
779 _pll_misc_chk_default(clk_base, plla->params, 2, val,
780 PLLA_MISC2_EN_DYNRAMP);
781
782
783 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
784 val &= ~mask;
785 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
786 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
787 udelay(1);
788
789 return;
790 }
791
792
793 val |= PLLA_BASE_IDDQ;
794 writel_relaxed(val, clk_base + plla->params->base_reg);
795 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
796 clk_base + plla->params->ext_misc_reg[0]);
797 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
798 clk_base + plla->params->ext_misc_reg[2]);
799 udelay(1);
800 }
801
802
803
804
805
806 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
807 {
808 u32 val;
809 u32 mask = 0xffff;
810
811 plld->params->defaults_set = true;
812
813 if (readl_relaxed(clk_base + plld->params->base_reg) &
814 PLL_ENABLE) {
815
816
817
818
819
820 val = PLLD_MISC1_DEFAULT_VALUE;
821 _pll_misc_chk_default(clk_base, plld->params, 1,
822 val, PLLD_MISC1_WRITE_MASK);
823
824
825 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
826 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
827 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
828 _pll_misc_chk_default(clk_base, plld->params, 0, val,
829 ~mask & PLLD_MISC0_WRITE_MASK);
830
831 if (!plld->params->defaults_set)
832 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
833
834
835 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
836 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
837 val &= ~mask;
838 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
839 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
840 udelay(1);
841
842 return;
843 }
844
845 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
846 val &= PLLD_MISC0_DSI_CLKENABLE;
847 val |= PLLD_MISC0_DEFAULT_VALUE;
848
849 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
850 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
851 plld->params->ext_misc_reg[1]);
852 udelay(1);
853 }
854
855
856
857
858
859 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
860 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
861 {
862 u32 default_val;
863 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
864
865 plldss->params->defaults_set = true;
866
867 if (val & PLL_ENABLE) {
868
869
870
871
872
873 if (val & PLLDSS_BASE_IDDQ) {
874 pr_warn("plldss boot enabled with IDDQ set\n");
875 plldss->params->defaults_set = false;
876 }
877
878
879 default_val = misc0_val;
880 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
881 PLLDSS_MISC0_WRITE_MASK &
882 (~PLLDSS_MISC0_LOCK_ENABLE));
883
884
885
886
887
888
889 if (plldss->params->ssc_ctrl_en_mask) {
890 default_val = misc1_val;
891 _pll_misc_chk_default(clk_base, plldss->params, 1,
892 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
893 default_val = misc2_val;
894 _pll_misc_chk_default(clk_base, plldss->params, 2,
895 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
896 default_val = misc3_val;
897 _pll_misc_chk_default(clk_base, plldss->params, 3,
898 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
899 } else if (plldss->params->ext_misc_reg[1]) {
900 default_val = misc1_val;
901 _pll_misc_chk_default(clk_base, plldss->params, 1,
902 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
903 (~PLLDSS_MISC1_CFG_EN_SDM));
904 }
905
906 if (!plldss->params->defaults_set)
907 pr_warn("%s already enabled. Postponing set full defaults\n",
908 pll_name);
909
910
911 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
912 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
913 writel_relaxed(val, clk_base +
914 plldss->params->base_reg);
915 }
916
917 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
918 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
919 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
920 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
921 udelay(1);
922
923 return;
924 }
925
926
927 val |= PLLDSS_BASE_IDDQ;
928 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
929 writel_relaxed(val, clk_base + plldss->params->base_reg);
930
931
932 if (!plldss->params->ext_misc_reg[1]) {
933 writel_relaxed(misc0_val, clk_base +
934 plldss->params->ext_misc_reg[0]);
935 udelay(1);
936 return;
937 }
938
939 writel_relaxed(misc0_val, clk_base +
940 plldss->params->ext_misc_reg[0]);
941
942 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
943 clk_base + plldss->params->ext_misc_reg[1]);
944 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
945 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
946 udelay(1);
947 }
948
949 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
950 {
951 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
952 PLLD2_MISC1_CFG_DEFAULT_VALUE,
953 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
954 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
955 }
956
957 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
958 {
959 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
960 PLLDP_MISC1_CFG_DEFAULT_VALUE,
961 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
962 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
963 }
964
965
966
967
968
969
970 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
971 {
972 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
973 }
974
975
976
977
978
979 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
980 {
981 u32 mask;
982 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
983
984 pllre->params->defaults_set = true;
985
986 if (val & PLL_ENABLE) {
987
988
989
990
991 val &= PLLRE_BASE_DEFAULT_MASK;
992 if (val != PLLRE_BASE_DEFAULT_VALUE) {
993 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
994 val, PLLRE_BASE_DEFAULT_VALUE);
995 pr_warn("(comparison mask = 0x%x)\n",
996 PLLRE_BASE_DEFAULT_MASK);
997 pllre->params->defaults_set = false;
998 }
999
1000
1001 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
1002 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
1003 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1004 ~mask & PLLRE_MISC0_WRITE_MASK);
1005
1006
1007 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1008 if (val & PLLRE_MISC0_IDDQ)
1009 pr_warn("unexpected IDDQ bit set for enabled clock\n");
1010
1011
1012 val &= ~mask;
1013 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
1014 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1015 udelay(1);
1016
1017 if (!pllre->params->defaults_set)
1018 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
1019
1020 return;
1021 }
1022
1023
1024 val &= ~PLLRE_BASE_DEFAULT_MASK;
1025 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
1026 writel_relaxed(val, clk_base + pllre->params->base_reg);
1027 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
1028 clk_base + pllre->params->ext_misc_reg[0]);
1029 udelay(1);
1030 }
1031
1032 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
1033 {
1034 unsigned long input_rate;
1035
1036
1037 if (!IS_ERR_OR_NULL(hw->clk))
1038 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1039 else
1040 input_rate = 38400000;
1041
1042 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
1043
1044 switch (input_rate) {
1045 case 12000000:
1046 case 12800000:
1047 case 13000000:
1048 *step_a = 0x2B;
1049 *step_b = 0x0B;
1050 return;
1051 case 19200000:
1052 *step_a = 0x12;
1053 *step_b = 0x08;
1054 return;
1055 case 38400000:
1056 *step_a = 0x04;
1057 *step_b = 0x05;
1058 return;
1059 default:
1060 pr_err("%s: Unexpected reference rate %lu\n",
1061 __func__, input_rate);
1062 BUG();
1063 }
1064 }
1065
1066 static void pllx_check_defaults(struct tegra_clk_pll *pll)
1067 {
1068 u32 default_val;
1069
1070 default_val = PLLX_MISC0_DEFAULT_VALUE;
1071
1072 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1073 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
1074
1075 default_val = PLLX_MISC1_DEFAULT_VALUE;
1076 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1077 PLLX_MISC1_WRITE_MASK);
1078
1079
1080 default_val = PLLX_MISC2_DEFAULT_VALUE;
1081 _pll_misc_chk_default(clk_base, pll->params, 2,
1082 default_val, PLLX_MISC2_EN_DYNRAMP);
1083
1084 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
1085 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1086 PLLX_MISC3_WRITE_MASK);
1087
1088 default_val = PLLX_MISC4_DEFAULT_VALUE;
1089 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1090 PLLX_MISC4_WRITE_MASK);
1091
1092 default_val = PLLX_MISC5_DEFAULT_VALUE;
1093 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1094 PLLX_MISC5_WRITE_MASK);
1095 }
1096
1097 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
1098 {
1099 u32 val;
1100 u32 step_a, step_b;
1101
1102 pllx->params->defaults_set = true;
1103
1104
1105 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
1106 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
1107 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
1108 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
1109 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
1110
1111 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1112
1113
1114
1115
1116
1117 pllx_check_defaults(pllx);
1118
1119 if (!pllx->params->defaults_set)
1120 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
1121
1122 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1123
1124
1125 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1126 val &= ~PLLX_MISC0_LOCK_ENABLE;
1127 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
1128 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1129 udelay(1);
1130
1131 return;
1132 }
1133
1134
1135 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1136 pllx->params->ext_misc_reg[0]);
1137
1138
1139 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1140 pllx->params->ext_misc_reg[1]);
1141
1142
1143 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1144
1145
1146 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1147 pllx->params->ext_misc_reg[3]);
1148
1149
1150 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1151 pllx->params->ext_misc_reg[4]);
1152 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1153 pllx->params->ext_misc_reg[5]);
1154 udelay(1);
1155 }
1156
1157
1158 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
1159 {
1160 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1161
1162 pllmb->params->defaults_set = true;
1163
1164 if (val & PLL_ENABLE) {
1165
1166
1167
1168
1169
1170 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
1171 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
1172 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1173 ~mask & PLLMB_MISC1_WRITE_MASK);
1174
1175 if (!pllmb->params->defaults_set)
1176 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
1177
1178 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1179 val &= ~mask;
1180 val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
1181 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1182 udelay(1);
1183
1184 return;
1185 }
1186
1187
1188 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
1189 clk_base + pllmb->params->ext_misc_reg[0]);
1190 udelay(1);
1191 }
1192
1193
1194
1195
1196
1197
1198
1199 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
1200 {
1201 u32 val, mask;
1202
1203
1204 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
1205 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1206 if (!enabled)
1207 mask |= PLLP_MISC0_IDDQ;
1208 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1209 ~mask & PLLP_MISC0_WRITE_MASK);
1210
1211
1212 val = PLLP_MISC1_DEFAULT_VALUE;
1213 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1214 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1215 ~mask & PLLP_MISC1_WRITE_MASK);
1216 }
1217
1218 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1219 {
1220 u32 mask;
1221 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1222
1223 pllp->params->defaults_set = true;
1224
1225 if (val & PLL_ENABLE) {
1226
1227
1228
1229
1230
1231 pllp_check_defaults(pllp, true);
1232 if (!pllp->params->defaults_set)
1233 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1234
1235
1236 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1237 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1238 val &= ~mask;
1239 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
1240 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1241 udelay(1);
1242
1243 return;
1244 }
1245
1246
1247 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
1248 clk_base + pllp->params->ext_misc_reg[0]);
1249
1250
1251 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1252 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1253 val &= mask;
1254 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
1255 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1256 udelay(1);
1257 }
1258
1259
1260
1261
1262
1263
1264
1265 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1266 bool hw_control)
1267 {
1268 u32 val, mask;
1269
1270
1271 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1272 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1273 _pll_misc_chk_default(clk_base, params, 0, val,
1274 ~mask & PLLU_MISC0_WRITE_MASK);
1275
1276 val = PLLU_MISC1_DEFAULT_VALUE;
1277 mask = PLLU_MISC1_LOCK_OVERRIDE;
1278 _pll_misc_chk_default(clk_base, params, 1, val,
1279 ~mask & PLLU_MISC1_WRITE_MASK);
1280 }
1281
1282 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
1283 {
1284 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1285
1286 pllu->defaults_set = true;
1287
1288 if (val & PLL_ENABLE) {
1289
1290
1291
1292
1293
1294 pllu_check_defaults(pllu, false);
1295 if (!pllu->defaults_set)
1296 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1297
1298
1299 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1300 val &= ~PLLU_MISC0_LOCK_ENABLE;
1301 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1302 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1303
1304 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1305 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1306 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1307 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1308 udelay(1);
1309
1310 return;
1311 }
1312
1313
1314 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1315 clk_base + pllu->ext_misc_reg[0]);
1316 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1317 clk_base + pllu->ext_misc_reg[1]);
1318 udelay(1);
1319 }
1320
1321 #define mask(w) ((1 << (w)) - 1)
1322 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1323 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1324 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1325 mask(p->params->div_nmp->divp_width))
1326
1327 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1328 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1329 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1330
1331 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1332 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1333 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1334
1335 #define PLL_LOCKDET_DELAY 2
1336 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1337 u32 reg, u32 mask)
1338 {
1339 int i;
1340 u32 val = 0;
1341
1342 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1343 udelay(PLL_LOCKDET_DELAY);
1344 val = readl_relaxed(clk_base + reg);
1345 if ((val & mask) == mask) {
1346 udelay(PLL_LOCKDET_DELAY);
1347 return 0;
1348 }
1349 }
1350 return -ETIMEDOUT;
1351 }
1352
1353 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1354 struct tegra_clk_pll_freq_table *cfg)
1355 {
1356 u32 val, base, ndiv_new_mask;
1357
1358 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1359 << PLLX_MISC2_NDIV_NEW_SHIFT;
1360
1361 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1362 val &= (~ndiv_new_mask);
1363 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1364 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1365 udelay(1);
1366
1367 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1368 val |= PLLX_MISC2_EN_DYNRAMP;
1369 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1370 udelay(1);
1371
1372 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1373 PLLX_MISC2_DYNRAMP_DONE);
1374
1375 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1376 (~divn_mask_shifted(pllx));
1377 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1378 writel_relaxed(base, clk_base + pllx->params->base_reg);
1379 udelay(1);
1380
1381 val &= ~PLLX_MISC2_EN_DYNRAMP;
1382 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1383 udelay(1);
1384
1385 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1386 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1387 cfg->input_rate / cfg->m * cfg->n /
1388 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1389
1390 return 0;
1391 }
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1402 struct tegra_clk_pll_freq_table *cfg,
1403 unsigned long rate, unsigned long input_rate)
1404 {
1405 struct tegra_clk_pll *pll = to_clk_pll(hw);
1406 struct tegra_clk_pll_params *params = pll->params;
1407 int p;
1408 unsigned long cf, p_rate;
1409 u32 pdiv;
1410
1411 if (!rate)
1412 return -EINVAL;
1413
1414 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1415 p = DIV_ROUND_UP(params->vco_min, rate);
1416 p = params->round_p_to_pdiv(p, &pdiv);
1417 } else {
1418 p = rate >= params->vco_min ? 1 : -EINVAL;
1419 }
1420
1421 if (p < 0)
1422 return -EINVAL;
1423
1424 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1425 cfg->p = p;
1426
1427
1428 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1429
1430 p_rate = rate * p;
1431 if (p_rate > params->vco_max)
1432 p_rate = params->vco_max;
1433 cf = input_rate / cfg->m;
1434 cfg->n = p_rate / cf;
1435
1436 cfg->sdm_data = 0;
1437 cfg->output_rate = input_rate;
1438 if (params->sdm_ctrl_reg) {
1439 unsigned long rem = p_rate - cf * cfg->n;
1440
1441 if (rem || params->ssc_ctrl_reg) {
1442 u64 s = rem * PLL_SDM_COEFF;
1443
1444 do_div(s, cf);
1445 s -= PLL_SDM_COEFF / 2;
1446 cfg->sdm_data = sdin_din_to_data(s);
1447 }
1448 cfg->output_rate *= sdin_get_n_eff(cfg);
1449 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1450 } else {
1451 cfg->output_rate *= cfg->n;
1452 cfg->output_rate /= p * cfg->m;
1453 }
1454
1455 cfg->input_rate = input_rate;
1456
1457 return 0;
1458 }
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1472 {
1473 cfg->n = sdin_get_n_eff(cfg);
1474 cfg->m *= PLL_SDM_COEFF;
1475 }
1476
1477 static unsigned long
1478 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1479 unsigned long parent_rate)
1480 {
1481 unsigned long vco_min = params->vco_min;
1482
1483 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1484 vco_min = min(vco_min, params->vco_min);
1485
1486 return vco_min;
1487 }
1488
1489 static struct div_nmp pllx_nmp = {
1490 .divm_shift = 0,
1491 .divm_width = 8,
1492 .divn_shift = 8,
1493 .divn_width = 8,
1494 .divp_shift = 20,
1495 .divp_width = 5,
1496 };
1497
1498
1499
1500
1501 #define PLL_QLIN_PDIV_MAX 16
1502 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1503 { .pdiv = 1, .hw_val = 0 },
1504 { .pdiv = 2, .hw_val = 1 },
1505 { .pdiv = 3, .hw_val = 2 },
1506 { .pdiv = 4, .hw_val = 3 },
1507 { .pdiv = 5, .hw_val = 4 },
1508 { .pdiv = 6, .hw_val = 5 },
1509 { .pdiv = 8, .hw_val = 6 },
1510 { .pdiv = 9, .hw_val = 7 },
1511 { .pdiv = 10, .hw_val = 8 },
1512 { .pdiv = 12, .hw_val = 9 },
1513 { .pdiv = 15, .hw_val = 10 },
1514 { .pdiv = 16, .hw_val = 11 },
1515 { .pdiv = 18, .hw_val = 12 },
1516 { .pdiv = 20, .hw_val = 13 },
1517 { .pdiv = 24, .hw_val = 14 },
1518 { .pdiv = 30, .hw_val = 15 },
1519 { .pdiv = 32, .hw_val = 16 },
1520 };
1521
1522 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1523 {
1524 int i;
1525
1526 if (p) {
1527 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1528 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1529 if (pdiv)
1530 *pdiv = i;
1531 return pll_qlin_pdiv_to_hw[i].pdiv;
1532 }
1533 }
1534 }
1535
1536 return -EINVAL;
1537 }
1538
1539 #define PLL_EXPO_PDIV_MAX 7
1540 static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1541 { .pdiv = 1, .hw_val = 0 },
1542 { .pdiv = 2, .hw_val = 1 },
1543 { .pdiv = 4, .hw_val = 2 },
1544 { .pdiv = 8, .hw_val = 3 },
1545 { .pdiv = 16, .hw_val = 4 },
1546 { .pdiv = 32, .hw_val = 5 },
1547 { .pdiv = 64, .hw_val = 6 },
1548 { .pdiv = 128, .hw_val = 7 },
1549 };
1550
1551 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1552 {
1553 if (p) {
1554 u32 i = fls(p);
1555
1556 if (i == ffs(p))
1557 i--;
1558
1559 if (i <= PLL_EXPO_PDIV_MAX) {
1560 if (pdiv)
1561 *pdiv = i;
1562 return 1 << i;
1563 }
1564 }
1565 return -EINVAL;
1566 }
1567
1568 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1569
1570 { 12000000, 1000000000, 166, 1, 2, 0 },
1571 { 13000000, 1000000000, 153, 1, 2, 0 },
1572 { 38400000, 1000000000, 156, 3, 2, 0 },
1573 { 0, 0, 0, 0, 0, 0 },
1574 };
1575
1576 static struct tegra_clk_pll_params pll_x_params = {
1577 .input_min = 12000000,
1578 .input_max = 800000000,
1579 .cf_min = 12000000,
1580 .cf_max = 38400000,
1581 .vco_min = 1350000000,
1582 .vco_max = 3000000000UL,
1583 .base_reg = PLLX_BASE,
1584 .misc_reg = PLLX_MISC0,
1585 .lock_mask = PLL_BASE_LOCK,
1586 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1587 .lock_delay = 300,
1588 .ext_misc_reg[0] = PLLX_MISC0,
1589 .ext_misc_reg[1] = PLLX_MISC1,
1590 .ext_misc_reg[2] = PLLX_MISC2,
1591 .ext_misc_reg[3] = PLLX_MISC3,
1592 .ext_misc_reg[4] = PLLX_MISC4,
1593 .ext_misc_reg[5] = PLLX_MISC5,
1594 .iddq_reg = PLLX_MISC3,
1595 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1596 .max_p = PLL_QLIN_PDIV_MAX,
1597 .mdiv_default = 2,
1598 .dyn_ramp_reg = PLLX_MISC2,
1599 .stepa_shift = 16,
1600 .stepb_shift = 24,
1601 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1602 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1603 .div_nmp = &pllx_nmp,
1604 .freq_table = pll_x_freq_table,
1605 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1606 .dyn_ramp = tegra210_pllx_dyn_ramp,
1607 .set_defaults = tegra210_pllx_set_defaults,
1608 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1609 };
1610
1611 static struct div_nmp pllc_nmp = {
1612 .divm_shift = 0,
1613 .divm_width = 8,
1614 .divn_shift = 10,
1615 .divn_width = 8,
1616 .divp_shift = 20,
1617 .divp_width = 5,
1618 };
1619
1620 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1621 { 12000000, 510000000, 85, 1, 2, 0 },
1622 { 13000000, 510000000, 78, 1, 2, 0 },
1623 { 38400000, 510000000, 79, 3, 2, 0 },
1624 { 0, 0, 0, 0, 0, 0 },
1625 };
1626
1627 static struct tegra_clk_pll_params pll_c_params = {
1628 .input_min = 12000000,
1629 .input_max = 700000000,
1630 .cf_min = 12000000,
1631 .cf_max = 50000000,
1632 .vco_min = 600000000,
1633 .vco_max = 1200000000,
1634 .base_reg = PLLC_BASE,
1635 .misc_reg = PLLC_MISC0,
1636 .lock_mask = PLL_BASE_LOCK,
1637 .lock_delay = 300,
1638 .iddq_reg = PLLC_MISC1,
1639 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1640 .reset_reg = PLLC_MISC0,
1641 .reset_bit_idx = PLLCX_RESET_BIT,
1642 .max_p = PLL_QLIN_PDIV_MAX,
1643 .ext_misc_reg[0] = PLLC_MISC0,
1644 .ext_misc_reg[1] = PLLC_MISC1,
1645 .ext_misc_reg[2] = PLLC_MISC2,
1646 .ext_misc_reg[3] = PLLC_MISC3,
1647 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1648 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1649 .mdiv_default = 3,
1650 .div_nmp = &pllc_nmp,
1651 .freq_table = pll_cx_freq_table,
1652 .flags = TEGRA_PLL_USE_LOCK,
1653 .set_defaults = _pllc_set_defaults,
1654 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1655 };
1656
1657 static struct div_nmp pllcx_nmp = {
1658 .divm_shift = 0,
1659 .divm_width = 8,
1660 .divn_shift = 10,
1661 .divn_width = 8,
1662 .divp_shift = 20,
1663 .divp_width = 5,
1664 };
1665
1666 static struct tegra_clk_pll_params pll_c2_params = {
1667 .input_min = 12000000,
1668 .input_max = 700000000,
1669 .cf_min = 12000000,
1670 .cf_max = 50000000,
1671 .vco_min = 600000000,
1672 .vco_max = 1200000000,
1673 .base_reg = PLLC2_BASE,
1674 .misc_reg = PLLC2_MISC0,
1675 .iddq_reg = PLLC2_MISC1,
1676 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1677 .reset_reg = PLLC2_MISC0,
1678 .reset_bit_idx = PLLCX_RESET_BIT,
1679 .lock_mask = PLLCX_BASE_LOCK,
1680 .lock_delay = 300,
1681 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1682 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1683 .mdiv_default = 3,
1684 .div_nmp = &pllcx_nmp,
1685 .max_p = PLL_QLIN_PDIV_MAX,
1686 .ext_misc_reg[0] = PLLC2_MISC0,
1687 .ext_misc_reg[1] = PLLC2_MISC1,
1688 .ext_misc_reg[2] = PLLC2_MISC2,
1689 .ext_misc_reg[3] = PLLC2_MISC3,
1690 .freq_table = pll_cx_freq_table,
1691 .flags = TEGRA_PLL_USE_LOCK,
1692 .set_defaults = _pllc2_set_defaults,
1693 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1694 };
1695
1696 static struct tegra_clk_pll_params pll_c3_params = {
1697 .input_min = 12000000,
1698 .input_max = 700000000,
1699 .cf_min = 12000000,
1700 .cf_max = 50000000,
1701 .vco_min = 600000000,
1702 .vco_max = 1200000000,
1703 .base_reg = PLLC3_BASE,
1704 .misc_reg = PLLC3_MISC0,
1705 .lock_mask = PLLCX_BASE_LOCK,
1706 .lock_delay = 300,
1707 .iddq_reg = PLLC3_MISC1,
1708 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1709 .reset_reg = PLLC3_MISC0,
1710 .reset_bit_idx = PLLCX_RESET_BIT,
1711 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1712 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1713 .mdiv_default = 3,
1714 .div_nmp = &pllcx_nmp,
1715 .max_p = PLL_QLIN_PDIV_MAX,
1716 .ext_misc_reg[0] = PLLC3_MISC0,
1717 .ext_misc_reg[1] = PLLC3_MISC1,
1718 .ext_misc_reg[2] = PLLC3_MISC2,
1719 .ext_misc_reg[3] = PLLC3_MISC3,
1720 .freq_table = pll_cx_freq_table,
1721 .flags = TEGRA_PLL_USE_LOCK,
1722 .set_defaults = _pllc3_set_defaults,
1723 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1724 };
1725
1726 static struct div_nmp pllss_nmp = {
1727 .divm_shift = 0,
1728 .divm_width = 8,
1729 .divn_shift = 8,
1730 .divn_width = 8,
1731 .divp_shift = 19,
1732 .divp_width = 5,
1733 };
1734
1735 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1736 { 12000000, 600000000, 50, 1, 1, 0 },
1737 { 13000000, 600000000, 46, 1, 1, 0 },
1738 { 38400000, 600000000, 62, 4, 1, 0 },
1739 { 0, 0, 0, 0, 0, 0 },
1740 };
1741
1742 static const struct clk_div_table pll_vco_post_div_table[] = {
1743 { .val = 0, .div = 1 },
1744 { .val = 1, .div = 2 },
1745 { .val = 2, .div = 3 },
1746 { .val = 3, .div = 4 },
1747 { .val = 4, .div = 5 },
1748 { .val = 5, .div = 6 },
1749 { .val = 6, .div = 8 },
1750 { .val = 7, .div = 10 },
1751 { .val = 8, .div = 12 },
1752 { .val = 9, .div = 16 },
1753 { .val = 10, .div = 12 },
1754 { .val = 11, .div = 16 },
1755 { .val = 12, .div = 20 },
1756 { .val = 13, .div = 24 },
1757 { .val = 14, .div = 32 },
1758 { .val = 0, .div = 0 },
1759 };
1760
1761 static struct tegra_clk_pll_params pll_c4_vco_params = {
1762 .input_min = 9600000,
1763 .input_max = 800000000,
1764 .cf_min = 9600000,
1765 .cf_max = 19200000,
1766 .vco_min = 500000000,
1767 .vco_max = 1080000000,
1768 .base_reg = PLLC4_BASE,
1769 .misc_reg = PLLC4_MISC0,
1770 .lock_mask = PLL_BASE_LOCK,
1771 .lock_delay = 300,
1772 .max_p = PLL_QLIN_PDIV_MAX,
1773 .ext_misc_reg[0] = PLLC4_MISC0,
1774 .iddq_reg = PLLC4_BASE,
1775 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1776 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1777 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1778 .mdiv_default = 3,
1779 .div_nmp = &pllss_nmp,
1780 .freq_table = pll_c4_vco_freq_table,
1781 .set_defaults = tegra210_pllc4_set_defaults,
1782 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1783 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1784 };
1785
1786 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1787 { 12000000, 800000000, 66, 1, 1, 0 },
1788 { 13000000, 800000000, 61, 1, 1, 0 },
1789 { 38400000, 297600000, 93, 4, 3, 0 },
1790 { 38400000, 400000000, 125, 4, 3, 0 },
1791 { 38400000, 532800000, 111, 4, 2, 0 },
1792 { 38400000, 665600000, 104, 3, 2, 0 },
1793 { 38400000, 800000000, 125, 3, 2, 0 },
1794 { 38400000, 931200000, 97, 4, 1, 0 },
1795 { 38400000, 1065600000, 111, 4, 1, 0 },
1796 { 38400000, 1200000000, 125, 4, 1, 0 },
1797 { 38400000, 1331200000, 104, 3, 1, 0 },
1798 { 38400000, 1459200000, 76, 2, 1, 0 },
1799 { 38400000, 1600000000, 125, 3, 1, 0 },
1800 { 0, 0, 0, 0, 0, 0 },
1801 };
1802
1803 static struct div_nmp pllm_nmp = {
1804 .divm_shift = 0,
1805 .divm_width = 8,
1806 .override_divm_shift = 0,
1807 .divn_shift = 8,
1808 .divn_width = 8,
1809 .override_divn_shift = 8,
1810 .divp_shift = 20,
1811 .divp_width = 5,
1812 .override_divp_shift = 27,
1813 };
1814
1815 static struct tegra_clk_pll_params pll_m_params = {
1816 .input_min = 9600000,
1817 .input_max = 500000000,
1818 .cf_min = 9600000,
1819 .cf_max = 19200000,
1820 .vco_min = 800000000,
1821 .vco_max = 1866000000,
1822 .base_reg = PLLM_BASE,
1823 .misc_reg = PLLM_MISC2,
1824 .lock_mask = PLL_BASE_LOCK,
1825 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1826 .lock_delay = 300,
1827 .iddq_reg = PLLM_MISC2,
1828 .iddq_bit_idx = PLLM_IDDQ_BIT,
1829 .max_p = PLL_QLIN_PDIV_MAX,
1830 .ext_misc_reg[0] = PLLM_MISC2,
1831 .ext_misc_reg[1] = PLLM_MISC1,
1832 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1833 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1834 .div_nmp = &pllm_nmp,
1835 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1836 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1837 .freq_table = pll_m_freq_table,
1838 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1839 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1840 };
1841
1842 static struct tegra_clk_pll_params pll_mb_params = {
1843 .input_min = 9600000,
1844 .input_max = 500000000,
1845 .cf_min = 9600000,
1846 .cf_max = 19200000,
1847 .vco_min = 800000000,
1848 .vco_max = 1866000000,
1849 .base_reg = PLLMB_BASE,
1850 .misc_reg = PLLMB_MISC1,
1851 .lock_mask = PLL_BASE_LOCK,
1852 .lock_delay = 300,
1853 .iddq_reg = PLLMB_MISC1,
1854 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1855 .max_p = PLL_QLIN_PDIV_MAX,
1856 .ext_misc_reg[0] = PLLMB_MISC1,
1857 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1858 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1859 .div_nmp = &pllm_nmp,
1860 .freq_table = pll_m_freq_table,
1861 .flags = TEGRA_PLL_USE_LOCK,
1862 .set_defaults = tegra210_pllmb_set_defaults,
1863 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1864 };
1865
1866
1867 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1868
1869 { 672000000, 100000000, 125, 42, 0, 13 },
1870 { 624000000, 100000000, 125, 39, 0, 13 },
1871 { 336000000, 100000000, 125, 21, 0, 13 },
1872 { 312000000, 100000000, 200, 26, 0, 14 },
1873 { 38400000, 100000000, 125, 2, 0, 14 },
1874 { 12000000, 100000000, 200, 1, 0, 14 },
1875 { 0, 0, 0, 0, 0, 0 },
1876 };
1877
1878 static struct div_nmp plle_nmp = {
1879 .divm_shift = 0,
1880 .divm_width = 8,
1881 .divn_shift = 8,
1882 .divn_width = 8,
1883 .divp_shift = 24,
1884 .divp_width = 5,
1885 };
1886
1887 static struct tegra_clk_pll_params pll_e_params = {
1888 .input_min = 12000000,
1889 .input_max = 800000000,
1890 .cf_min = 12000000,
1891 .cf_max = 38400000,
1892 .vco_min = 1600000000,
1893 .vco_max = 2500000000U,
1894 .base_reg = PLLE_BASE,
1895 .misc_reg = PLLE_MISC0,
1896 .aux_reg = PLLE_AUX,
1897 .lock_mask = PLLE_MISC_LOCK,
1898 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1899 .lock_delay = 300,
1900 .div_nmp = &plle_nmp,
1901 .freq_table = pll_e_freq_table,
1902 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1903 TEGRA_PLL_HAS_LOCK_ENABLE,
1904 .fixed_rate = 100000000,
1905 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1906 };
1907
1908 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1909 { 12000000, 672000000, 56, 1, 1, 0 },
1910 { 13000000, 672000000, 51, 1, 1, 0 },
1911 { 38400000, 672000000, 70, 4, 1, 0 },
1912 { 0, 0, 0, 0, 0, 0 },
1913 };
1914
1915 static struct div_nmp pllre_nmp = {
1916 .divm_shift = 0,
1917 .divm_width = 8,
1918 .divn_shift = 8,
1919 .divn_width = 8,
1920 .divp_shift = 16,
1921 .divp_width = 5,
1922 };
1923
1924 static struct tegra_clk_pll_params pll_re_vco_params = {
1925 .input_min = 9600000,
1926 .input_max = 800000000,
1927 .cf_min = 9600000,
1928 .cf_max = 19200000,
1929 .vco_min = 350000000,
1930 .vco_max = 700000000,
1931 .base_reg = PLLRE_BASE,
1932 .misc_reg = PLLRE_MISC0,
1933 .lock_mask = PLLRE_MISC_LOCK,
1934 .lock_delay = 300,
1935 .max_p = PLL_QLIN_PDIV_MAX,
1936 .ext_misc_reg[0] = PLLRE_MISC0,
1937 .iddq_reg = PLLRE_MISC0,
1938 .iddq_bit_idx = PLLRE_IDDQ_BIT,
1939 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1940 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1941 .div_nmp = &pllre_nmp,
1942 .freq_table = pll_re_vco_freq_table,
1943 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
1944 .set_defaults = tegra210_pllre_set_defaults,
1945 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1946 };
1947
1948 static struct div_nmp pllp_nmp = {
1949 .divm_shift = 0,
1950 .divm_width = 8,
1951 .divn_shift = 10,
1952 .divn_width = 8,
1953 .divp_shift = 20,
1954 .divp_width = 5,
1955 };
1956
1957 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1958 { 12000000, 408000000, 34, 1, 1, 0 },
1959 { 38400000, 408000000, 85, 8, 1, 0 },
1960 { 0, 0, 0, 0, 0, 0 },
1961 };
1962
1963 static struct tegra_clk_pll_params pll_p_params = {
1964 .input_min = 9600000,
1965 .input_max = 800000000,
1966 .cf_min = 9600000,
1967 .cf_max = 19200000,
1968 .vco_min = 350000000,
1969 .vco_max = 700000000,
1970 .base_reg = PLLP_BASE,
1971 .misc_reg = PLLP_MISC0,
1972 .lock_mask = PLL_BASE_LOCK,
1973 .lock_delay = 300,
1974 .iddq_reg = PLLP_MISC0,
1975 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1976 .ext_misc_reg[0] = PLLP_MISC0,
1977 .ext_misc_reg[1] = PLLP_MISC1,
1978 .div_nmp = &pllp_nmp,
1979 .freq_table = pll_p_freq_table,
1980 .fixed_rate = 408000000,
1981 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1982 .set_defaults = tegra210_pllp_set_defaults,
1983 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1984 };
1985
1986 static struct tegra_clk_pll_params pll_a1_params = {
1987 .input_min = 12000000,
1988 .input_max = 700000000,
1989 .cf_min = 12000000,
1990 .cf_max = 50000000,
1991 .vco_min = 600000000,
1992 .vco_max = 1200000000,
1993 .base_reg = PLLA1_BASE,
1994 .misc_reg = PLLA1_MISC0,
1995 .lock_mask = PLLCX_BASE_LOCK,
1996 .lock_delay = 300,
1997 .iddq_reg = PLLA1_MISC1,
1998 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1999 .reset_reg = PLLA1_MISC0,
2000 .reset_bit_idx = PLLCX_RESET_BIT,
2001 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2002 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2003 .div_nmp = &pllc_nmp,
2004 .ext_misc_reg[0] = PLLA1_MISC0,
2005 .ext_misc_reg[1] = PLLA1_MISC1,
2006 .ext_misc_reg[2] = PLLA1_MISC2,
2007 .ext_misc_reg[3] = PLLA1_MISC3,
2008 .freq_table = pll_cx_freq_table,
2009 .flags = TEGRA_PLL_USE_LOCK,
2010 .set_defaults = _plla1_set_defaults,
2011 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2012 };
2013
2014 static struct div_nmp plla_nmp = {
2015 .divm_shift = 0,
2016 .divm_width = 8,
2017 .divn_shift = 8,
2018 .divn_width = 8,
2019 .divp_shift = 20,
2020 .divp_width = 5,
2021 };
2022
2023 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
2024 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 },
2025 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 },
2026 { 12000000, 240000000, 60, 1, 3, 1, 0 },
2027 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d },
2028 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 },
2029 { 13000000, 240000000, 55, 1, 3, 1, 0 },
2030 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 },
2031 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 },
2032 { 38400000, 240000000, 75, 3, 3, 1, 0 },
2033 { 0, 0, 0, 0, 0, 0, 0 },
2034 };
2035
2036 static struct tegra_clk_pll_params pll_a_params = {
2037 .input_min = 12000000,
2038 .input_max = 800000000,
2039 .cf_min = 12000000,
2040 .cf_max = 19200000,
2041 .vco_min = 500000000,
2042 .vco_max = 1000000000,
2043 .base_reg = PLLA_BASE,
2044 .misc_reg = PLLA_MISC0,
2045 .lock_mask = PLL_BASE_LOCK,
2046 .lock_delay = 300,
2047 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2048 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2049 .iddq_reg = PLLA_BASE,
2050 .iddq_bit_idx = PLLA_IDDQ_BIT,
2051 .div_nmp = &plla_nmp,
2052 .sdm_din_reg = PLLA_MISC1,
2053 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2054 .sdm_ctrl_reg = PLLA_MISC2,
2055 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
2056 .ext_misc_reg[0] = PLLA_MISC0,
2057 .ext_misc_reg[1] = PLLA_MISC1,
2058 .ext_misc_reg[2] = PLLA_MISC2,
2059 .freq_table = pll_a_freq_table,
2060 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
2061 .set_defaults = tegra210_plla_set_defaults,
2062 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2063 .set_gain = tegra210_clk_pll_set_gain,
2064 .adjust_vco = tegra210_clk_adjust_vco_min,
2065 };
2066
2067 static struct div_nmp plld_nmp = {
2068 .divm_shift = 0,
2069 .divm_width = 8,
2070 .divn_shift = 11,
2071 .divn_width = 8,
2072 .divp_shift = 20,
2073 .divp_width = 3,
2074 };
2075
2076 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
2077 { 12000000, 594000000, 99, 1, 2, 0, 0 },
2078 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f },
2079 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2080 { 0, 0, 0, 0, 0, 0, 0 },
2081 };
2082
2083 static struct tegra_clk_pll_params pll_d_params = {
2084 .input_min = 12000000,
2085 .input_max = 800000000,
2086 .cf_min = 12000000,
2087 .cf_max = 38400000,
2088 .vco_min = 750000000,
2089 .vco_max = 1500000000,
2090 .base_reg = PLLD_BASE,
2091 .misc_reg = PLLD_MISC0,
2092 .lock_mask = PLL_BASE_LOCK,
2093 .lock_delay = 1000,
2094 .iddq_reg = PLLD_MISC0,
2095 .iddq_bit_idx = PLLD_IDDQ_BIT,
2096 .round_p_to_pdiv = pll_expo_p_to_pdiv,
2097 .pdiv_tohw = pll_expo_pdiv_to_hw,
2098 .div_nmp = &plld_nmp,
2099 .sdm_din_reg = PLLD_MISC0,
2100 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2101 .sdm_ctrl_reg = PLLD_MISC0,
2102 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
2103 .ext_misc_reg[0] = PLLD_MISC0,
2104 .ext_misc_reg[1] = PLLD_MISC1,
2105 .freq_table = pll_d_freq_table,
2106 .flags = TEGRA_PLL_USE_LOCK,
2107 .mdiv_default = 1,
2108 .set_defaults = tegra210_plld_set_defaults,
2109 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2110 .set_gain = tegra210_clk_pll_set_gain,
2111 .adjust_vco = tegra210_clk_adjust_vco_min,
2112 };
2113
2114 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
2115 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
2116 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f },
2117 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2118 { 0, 0, 0, 0, 0, 0, 0 },
2119 };
2120
2121
2122 static struct tegra_clk_pll_params pll_d2_params = {
2123 .input_min = 12000000,
2124 .input_max = 800000000,
2125 .cf_min = 12000000,
2126 .cf_max = 38400000,
2127 .vco_min = 750000000,
2128 .vco_max = 1500000000,
2129 .base_reg = PLLD2_BASE,
2130 .misc_reg = PLLD2_MISC0,
2131 .lock_mask = PLL_BASE_LOCK,
2132 .lock_delay = 300,
2133 .iddq_reg = PLLD2_BASE,
2134 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2135 .sdm_din_reg = PLLD2_MISC3,
2136 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2137 .sdm_ctrl_reg = PLLD2_MISC1,
2138 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
2139
2140 .ssc_ctrl_reg = 0,
2141 .ssc_ctrl_en_mask = 0,
2142 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2143 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2144 .div_nmp = &pllss_nmp,
2145 .ext_misc_reg[0] = PLLD2_MISC0,
2146 .ext_misc_reg[1] = PLLD2_MISC1,
2147 .ext_misc_reg[2] = PLLD2_MISC2,
2148 .ext_misc_reg[3] = PLLD2_MISC3,
2149 .max_p = PLL_QLIN_PDIV_MAX,
2150 .mdiv_default = 1,
2151 .freq_table = tegra210_pll_d2_freq_table,
2152 .set_defaults = tegra210_plld2_set_defaults,
2153 .flags = TEGRA_PLL_USE_LOCK,
2154 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2155 .set_gain = tegra210_clk_pll_set_gain,
2156 .adjust_vco = tegra210_clk_adjust_vco_min,
2157 };
2158
2159 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
2160 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
2161 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 },
2162 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
2163 { 0, 0, 0, 0, 0, 0, 0 },
2164 };
2165
2166 static struct tegra_clk_pll_params pll_dp_params = {
2167 .input_min = 12000000,
2168 .input_max = 800000000,
2169 .cf_min = 12000000,
2170 .cf_max = 38400000,
2171 .vco_min = 750000000,
2172 .vco_max = 1500000000,
2173 .base_reg = PLLDP_BASE,
2174 .misc_reg = PLLDP_MISC,
2175 .lock_mask = PLL_BASE_LOCK,
2176 .lock_delay = 300,
2177 .iddq_reg = PLLDP_BASE,
2178 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2179 .sdm_din_reg = PLLDP_SS_CTRL2,
2180 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2181 .sdm_ctrl_reg = PLLDP_SS_CFG,
2182 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
2183 .ssc_ctrl_reg = PLLDP_SS_CFG,
2184 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
2185 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2186 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2187 .div_nmp = &pllss_nmp,
2188 .ext_misc_reg[0] = PLLDP_MISC,
2189 .ext_misc_reg[1] = PLLDP_SS_CFG,
2190 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2191 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2192 .max_p = PLL_QLIN_PDIV_MAX,
2193 .mdiv_default = 1,
2194 .freq_table = pll_dp_freq_table,
2195 .set_defaults = tegra210_plldp_set_defaults,
2196 .flags = TEGRA_PLL_USE_LOCK,
2197 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2198 .set_gain = tegra210_clk_pll_set_gain,
2199 .adjust_vco = tegra210_clk_adjust_vco_min,
2200 };
2201
2202 static struct div_nmp pllu_nmp = {
2203 .divm_shift = 0,
2204 .divm_width = 8,
2205 .divn_shift = 8,
2206 .divn_width = 8,
2207 .divp_shift = 16,
2208 .divp_width = 5,
2209 };
2210
2211 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2212 { 12000000, 480000000, 40, 1, 1, 0 },
2213 { 13000000, 480000000, 36, 1, 1, 0 },
2214 { 38400000, 480000000, 25, 2, 1, 0 },
2215 { 0, 0, 0, 0, 0, 0 },
2216 };
2217
2218 static struct tegra_clk_pll_params pll_u_vco_params = {
2219 .input_min = 9600000,
2220 .input_max = 800000000,
2221 .cf_min = 9600000,
2222 .cf_max = 19200000,
2223 .vco_min = 350000000,
2224 .vco_max = 700000000,
2225 .base_reg = PLLU_BASE,
2226 .misc_reg = PLLU_MISC0,
2227 .lock_mask = PLL_BASE_LOCK,
2228 .lock_delay = 1000,
2229 .iddq_reg = PLLU_MISC0,
2230 .iddq_bit_idx = PLLU_IDDQ_BIT,
2231 .ext_misc_reg[0] = PLLU_MISC0,
2232 .ext_misc_reg[1] = PLLU_MISC1,
2233 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2234 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2235 .div_nmp = &pllu_nmp,
2236 .freq_table = pll_u_freq_table,
2237 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2238 };
2239
2240 struct utmi_clk_param {
2241
2242 u32 osc_frequency;
2243
2244 u8 enable_delay_count;
2245
2246 u16 stable_count;
2247
2248 u8 active_delay_count;
2249
2250 u16 xtal_freq_count;
2251 };
2252
2253 static const struct utmi_clk_param utmi_parameters[] = {
2254 {
2255 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2256 .stable_count = 0x0, .active_delay_count = 0x6,
2257 .xtal_freq_count = 0x80
2258 }, {
2259 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2260 .stable_count = 0x33, .active_delay_count = 0x05,
2261 .xtal_freq_count = 0x7f
2262 }, {
2263 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2264 .stable_count = 0x4b, .active_delay_count = 0x06,
2265 .xtal_freq_count = 0xbb
2266 }, {
2267 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2268 .stable_count = 0x2f, .active_delay_count = 0x08,
2269 .xtal_freq_count = 0x76
2270 }, {
2271 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2272 .stable_count = 0x66, .active_delay_count = 0x09,
2273 .xtal_freq_count = 0xfe
2274 }, {
2275 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2276 .stable_count = 0x41, .active_delay_count = 0x0a,
2277 .xtal_freq_count = 0xa4
2278 },
2279 };
2280
2281 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2282 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2283 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2284 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2285 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2286 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2287 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2288 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2289 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2290 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2291 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2292 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2293 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2294 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2295 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2296 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2297 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2298 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2299 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2300 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2301 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2302 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2303 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2304 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2305 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2306 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2307 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },
2308 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2309 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2310 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2311 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2312 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2313 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2314 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2315 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2316 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2317 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2318 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2319 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2320 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2321 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2322 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2323 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2324 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2325 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2326 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2327 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2328 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2329 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2330 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2331 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2332 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2333 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2334 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2335 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2336 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2337 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2338 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2339 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2340 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2341 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2342 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2343 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2344 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2345 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2346 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2347 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2348 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2349 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2350 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2351 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2352 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2353 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2354 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2355 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2356 [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
2357 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2358 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2359 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2360 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2361 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2362 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2363 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2364 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2365 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2366 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2367 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2368 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
2369 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2370 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2371 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2372 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2373 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2374 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2375 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2376 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2377 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2378 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2379 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2380 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2381 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2382 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2383 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2384 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2385 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2386 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2387 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2388 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2389 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2390 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2391 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2392 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2393 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2394 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2395 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2396 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2397 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2398 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2399 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2400 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2401 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2402 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2403 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2404 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2405 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2406 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2407 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2408 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2409 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2410 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2411 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2412 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2413 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2414 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
2415 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
2416 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
2417 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
2418 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2419 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2420 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2421 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2422 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2423 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2424 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2425 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2426 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2427 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2428 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2429 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2430 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2431 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2432 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2433 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2434 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2435 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2436 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2437 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2438 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2439 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2440 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2441 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2442 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2443 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2444 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2445 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2446 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2447 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2448 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2449 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
2450 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
2451 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
2452 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2453 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2454 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2455 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2456 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2457 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2458 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2459 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2460 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2461 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2462 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2463 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2464 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2465 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2466 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2467 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2468 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2469 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
2470 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
2471 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
2472 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
2473 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2474 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2475 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2476 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2477 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2478 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2479 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2480 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2481 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2482 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2483 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2484 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2485 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2486 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2487 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2488 };
2489
2490 static struct tegra_devclk devclks[] __initdata = {
2491 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2492 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2493 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2494 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2495 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2496 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2497 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2498 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2499 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2500 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2501 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2502 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2503 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2504 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2505 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2506 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2507 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2508 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2509 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2510 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2511 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2512 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2513 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2514 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2515 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2516 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2517 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2518 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2519 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2520 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2521 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2522 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2523 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2524 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2525 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2526 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2527 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2528 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2529 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2530 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2531 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2532 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2533 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2534 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2535 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2536 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2537 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
2538 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
2539 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
2540 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
2541 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2542 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2543 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2544 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2545 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2546 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2547 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2548 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2549 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2550 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2551 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2552 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2553 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2554 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 },
2555 };
2556
2557 static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2558 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2559 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2560 };
2561
2562 static const char * const aclk_parents[] = {
2563 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
2564 "clk_m"
2565 };
2566
2567 static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };
2568 static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };
2569 static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,
2570 TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };
2571 static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,
2572 TEGRA210_CLK_HOST1X};
2573 static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2574 TEGRA210_CLK_XUSB_DEV };
2575 static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2576 TEGRA210_CLK_XUSB_SS };
2577 static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,
2578 TEGRA210_CLK_XUSB_SS };
2579 static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,
2580 TEGRA210_CLK_PLL_D };
2581 static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,
2582 TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,
2583 TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,
2584 TEGRA210_CLK_D_AUDIO };
2585 static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };
2586
2587 static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
2588 [TEGRA_POWERGATE_VENC] = {
2589 .handle_lvl2_ovr = tegra210_venc_mbist_war,
2590 .num_clks = ARRAY_SIZE(venc_slcg_clkids),
2591 .clk_init_data = venc_slcg_clkids,
2592 },
2593 [TEGRA_POWERGATE_SATA] = {
2594 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2595 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2596 .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
2597 },
2598 [TEGRA_POWERGATE_MPE] = {
2599 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2600 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2601 .lvl2_mask = BIT(29),
2602 },
2603 [TEGRA_POWERGATE_SOR] = {
2604 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2605 .num_clks = ARRAY_SIZE(sor_slcg_clkids),
2606 .clk_init_data = sor_slcg_clkids,
2607 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2608 .lvl2_mask = BIT(1) | BIT(2),
2609 },
2610 [TEGRA_POWERGATE_DIS] = {
2611 .handle_lvl2_ovr = tegra210_disp_mbist_war,
2612 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2613 .clk_init_data = disp_slcg_clkids,
2614 },
2615 [TEGRA_POWERGATE_DISB] = {
2616 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2617 .clk_init_data = disp_slcg_clkids,
2618 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2619 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2620 .lvl2_mask = BIT(2),
2621 },
2622 [TEGRA_POWERGATE_XUSBA] = {
2623 .num_clks = ARRAY_SIZE(xusba_slcg_clkids),
2624 .clk_init_data = xusba_slcg_clkids,
2625 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2626 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2627 .lvl2_mask = BIT(30) | BIT(31),
2628 },
2629 [TEGRA_POWERGATE_XUSBB] = {
2630 .num_clks = ARRAY_SIZE(xusbb_slcg_clkids),
2631 .clk_init_data = xusbb_slcg_clkids,
2632 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2633 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2634 .lvl2_mask = BIT(30) | BIT(31),
2635 },
2636 [TEGRA_POWERGATE_XUSBC] = {
2637 .num_clks = ARRAY_SIZE(xusbc_slcg_clkids),
2638 .clk_init_data = xusbc_slcg_clkids,
2639 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2640 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2641 .lvl2_mask = BIT(30) | BIT(31),
2642 },
2643 [TEGRA_POWERGATE_VIC] = {
2644 .num_clks = ARRAY_SIZE(vic_slcg_clkids),
2645 .clk_init_data = vic_slcg_clkids,
2646 .handle_lvl2_ovr = tegra210_vic_mbist_war,
2647 },
2648 [TEGRA_POWERGATE_NVDEC] = {
2649 .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
2650 .clk_init_data = nvdec_slcg_clkids,
2651 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2652 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2653 .lvl2_mask = BIT(9) | BIT(31),
2654 },
2655 [TEGRA_POWERGATE_NVJPG] = {
2656 .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
2657 .clk_init_data = nvjpg_slcg_clkids,
2658 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2659 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2660 .lvl2_mask = BIT(9) | BIT(31),
2661 },
2662 [TEGRA_POWERGATE_AUD] = {
2663 .num_clks = ARRAY_SIZE(ape_slcg_clkids),
2664 .clk_init_data = ape_slcg_clkids,
2665 .handle_lvl2_ovr = tegra210_ape_mbist_war,
2666 },
2667 [TEGRA_POWERGATE_VE2] = {
2668 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2669 .lvl2_offset = LVL2_CLK_GATE_OVRD,
2670 .lvl2_mask = BIT(22),
2671 },
2672 };
2673
2674 int tegra210_clk_handle_mbist_war(unsigned int id)
2675 {
2676 int err;
2677 struct tegra210_domain_mbist_war *mbist_war;
2678
2679 if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {
2680 WARN(1, "unknown domain id in MBIST WAR handler\n");
2681 return -EINVAL;
2682 }
2683
2684 mbist_war = &tegra210_pg_mbist_war[id];
2685 if (!mbist_war->handle_lvl2_ovr)
2686 return 0;
2687
2688 if (mbist_war->num_clks && !mbist_war->clks)
2689 return -ENODEV;
2690
2691 err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);
2692 if (err < 0)
2693 return err;
2694
2695 mutex_lock(&lvl2_ovr_lock);
2696
2697 mbist_war->handle_lvl2_ovr(mbist_war);
2698
2699 mutex_unlock(&lvl2_ovr_lock);
2700
2701 clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);
2702
2703 return 0;
2704 }
2705
2706 void tegra210_put_utmipll_in_iddq(void)
2707 {
2708 u32 reg;
2709
2710 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2711
2712 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
2713 pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
2714 return;
2715 }
2716
2717 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2718 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2719 }
2720 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
2721
2722 void tegra210_put_utmipll_out_iddq(void)
2723 {
2724 u32 reg;
2725
2726 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2727 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2728 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2729 }
2730 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
2731
2732 static void tegra210_utmi_param_configure(void)
2733 {
2734 u32 reg;
2735 int i;
2736
2737 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2738 if (osc_freq == utmi_parameters[i].osc_frequency)
2739 break;
2740 }
2741
2742 if (i >= ARRAY_SIZE(utmi_parameters)) {
2743 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2744 osc_freq);
2745 return;
2746 }
2747
2748 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2749 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2750 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2751
2752 udelay(10);
2753
2754 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2755
2756
2757
2758 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2759 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2760
2761 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2762 reg |=
2763 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
2764 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2765
2766
2767 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2768
2769 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2770 reg |=
2771 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
2772
2773 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2774 reg |=
2775 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
2776
2777 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2778 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2779
2780
2781 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2782 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2783 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2784 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2785
2786 udelay(20);
2787
2788
2789 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2790 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2791 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2792 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2793 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2794 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2795 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2796 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2797
2798
2799 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2800 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2801 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2802 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2803
2804 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2805 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2806 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2807 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2808
2809 udelay(1);
2810
2811 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2812 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2813 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2814
2815 udelay(1);
2816
2817
2818 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2819 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2820 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2821 }
2822
2823 static int tegra210_enable_pllu(void)
2824 {
2825 struct tegra_clk_pll_freq_table *fentry;
2826 struct tegra_clk_pll pllu;
2827 u32 reg;
2828
2829 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
2830 if (fentry->input_rate == pll_ref_freq)
2831 break;
2832 }
2833
2834 if (!fentry->input_rate) {
2835 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
2836 return -EINVAL;
2837 }
2838
2839
2840 pllu.params = &pll_u_vco_params;
2841 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2842 reg &= ~BIT(pllu.params->iddq_bit_idx);
2843 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2844 udelay(5);
2845
2846 reg = readl_relaxed(clk_base + PLLU_BASE);
2847 reg &= ~GENMASK(20, 0);
2848 reg |= fentry->m;
2849 reg |= fentry->n << 8;
2850 reg |= fentry->p << 16;
2851 writel(reg, clk_base + PLLU_BASE);
2852 udelay(1);
2853 reg |= PLL_ENABLE;
2854 writel(reg, clk_base + PLLU_BASE);
2855
2856 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
2857 reg & PLL_BASE_LOCK, 2, 1000);
2858 if (!(reg & PLL_BASE_LOCK)) {
2859 pr_err("Timed out waiting for PLL_U to lock\n");
2860 return -ETIMEDOUT;
2861 }
2862
2863 return 0;
2864 }
2865
2866 static int tegra210_init_pllu(void)
2867 {
2868 u32 reg;
2869 int err;
2870
2871 tegra210_pllu_set_defaults(&pll_u_vco_params);
2872
2873 reg = readl_relaxed(clk_base + PLLU_BASE);
2874 if (reg & PLLU_BASE_OVERRIDE) {
2875 if (!(reg & PLL_ENABLE)) {
2876 err = tegra210_enable_pllu();
2877 if (err < 0) {
2878 WARN_ON(1);
2879 return err;
2880 }
2881 }
2882
2883 reg = readl_relaxed(clk_base + PLLU_BASE);
2884 reg &= ~PLLU_BASE_OVERRIDE;
2885 writel(reg, clk_base + PLLU_BASE);
2886
2887 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2888 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2889 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2890 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2891 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2892 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2893 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2894
2895 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2896 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
2897 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2898 udelay(1);
2899
2900 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2901 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2902 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2903 udelay(1);
2904
2905 reg = readl_relaxed(clk_base + PLLU_BASE);
2906 reg &= ~PLLU_BASE_CLKENABLE_USB;
2907 writel_relaxed(reg, clk_base + PLLU_BASE);
2908 }
2909
2910
2911 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2912 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
2913 tegra210_utmi_param_configure();
2914
2915 return 0;
2916 }
2917
2918 static const char * const sor1_out_parents[] = {
2919
2920
2921
2922
2923
2924
2925
2926 "sor_safe", "sor1_pad_clkout", "sor1", "sor1_pad_clkout",
2927 };
2928
2929 static const char * const sor1_parents[] = {
2930 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
2931 };
2932
2933 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
2934
2935 static struct tegra_periph_init_data tegra210_periph[] = {
2936 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
2937 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
2938 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1,
2939 sor1_parents_idx, 0, &sor1_lock),
2940 };
2941
2942 static const char * const la_parents[] = {
2943 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
2944 };
2945
2946 static struct tegra_clk_periph tegra210_la =
2947 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0);
2948
2949 static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2950 void __iomem *pmc_base)
2951 {
2952 struct clk *clk;
2953 unsigned int i;
2954
2955
2956 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2957 1, 2);
2958 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2959
2960 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2961 1, 17, 222);
2962 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2963
2964 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
2965 1, 17, 181);
2966 clks[TEGRA210_CLK_DPAUX] = clk;
2967
2968 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
2969 1, 17, 207);
2970 clks[TEGRA210_CLK_DPAUX1] = clk;
2971
2972 clk = clk_register_mux_table(NULL, "sor1_out", sor1_out_parents,
2973 ARRAY_SIZE(sor1_out_parents), 0,
2974 clk_base + CLK_SOURCE_SOR1, 14, 0x3,
2975 0, NULL, &sor1_lock);
2976 clks[TEGRA210_CLK_SOR1_OUT] = clk;
2977
2978
2979 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2980 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
2981 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
2982
2983
2984 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
2985 clk_base, 0, 48,
2986 periph_clk_enb_refcnt);
2987 clks[TEGRA210_CLK_DSIA] = clk;
2988
2989
2990 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
2991 clk_base, 0, 82,
2992 periph_clk_enb_refcnt);
2993 clks[TEGRA210_CLK_DSIB] = clk;
2994
2995
2996 clk = tegra_clk_register_periph("la", la_parents,
2997 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
2998 CLK_SOURCE_LA, 0);
2999 clks[TEGRA210_CLK_LA] = clk;
3000
3001
3002 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
3003 ARRAY_SIZE(mux_pllmcp_clkm), 0,
3004 clk_base + CLK_SOURCE_EMC,
3005 29, 3, 0, &emc_lock);
3006
3007 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
3008 &emc_lock);
3009 clks[TEGRA210_CLK_MC] = clk;
3010
3011
3012 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3013 0, 0, &pll_e_lock);
3014 clk_register_clkdev(clk, "cml0", NULL);
3015 clks[TEGRA210_CLK_CML0] = clk;
3016
3017
3018 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3019 1, 0, &pll_e_lock);
3020 clk_register_clkdev(clk, "cml1", NULL);
3021 clks[TEGRA210_CLK_CML1] = clk;
3022
3023 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
3024 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3025 0, NULL);
3026 clks[TEGRA210_CLK_ACLK] = clk;
3027
3028 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3029 CLK_SOURCE_SDMMC2, 9,
3030 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3031 clks[TEGRA210_CLK_SDMMC2] = clk;
3032
3033 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3034 CLK_SOURCE_SDMMC4, 15,
3035 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3036 clks[TEGRA210_CLK_SDMMC4] = clk;
3037
3038 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
3039 struct tegra_periph_init_data *init = &tegra210_periph[i];
3040 struct clk **clkp;
3041
3042 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
3043 if (!clkp) {
3044 pr_warn("clock %u not found\n", init->clk_id);
3045 continue;
3046 }
3047
3048 clk = tegra_clk_register_periph_data(clk_base, init);
3049 *clkp = clk;
3050 }
3051
3052 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3053 }
3054
3055 static void __init tegra210_pll_init(void __iomem *clk_base,
3056 void __iomem *pmc)
3057 {
3058 struct clk *clk;
3059
3060
3061 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3062 pmc, 0, &pll_c_params, NULL);
3063 if (!WARN_ON(IS_ERR(clk)))
3064 clk_register_clkdev(clk, "pll_c", NULL);
3065 clks[TEGRA210_CLK_PLL_C] = clk;
3066
3067
3068 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
3069 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3070 8, 8, 1, NULL);
3071 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
3072 clk_base + PLLC_OUT, 1, 0,
3073 CLK_SET_RATE_PARENT, 0, NULL);
3074 clk_register_clkdev(clk, "pll_c_out1", NULL);
3075 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
3076
3077
3078 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
3079 CLK_SET_RATE_PARENT, 1, 1);
3080 clk_register_clkdev(clk, "pll_c_ud", NULL);
3081 clks[TEGRA210_CLK_PLL_C_UD] = clk;
3082
3083
3084 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3085 pmc, 0, &pll_c2_params, NULL);
3086 clk_register_clkdev(clk, "pll_c2", NULL);
3087 clks[TEGRA210_CLK_PLL_C2] = clk;
3088
3089
3090 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3091 pmc, 0, &pll_c3_params, NULL);
3092 clk_register_clkdev(clk, "pll_c3", NULL);
3093 clks[TEGRA210_CLK_PLL_C3] = clk;
3094
3095
3096 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3097 CLK_SET_RATE_GATE, &pll_m_params, NULL);
3098 clk_register_clkdev(clk, "pll_m", NULL);
3099 clks[TEGRA210_CLK_PLL_M] = clk;
3100
3101
3102 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3103 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
3104 clk_register_clkdev(clk, "pll_mb", NULL);
3105 clks[TEGRA210_CLK_PLL_MB] = clk;
3106
3107
3108 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
3109 CLK_SET_RATE_PARENT, 1, 1);
3110 clk_register_clkdev(clk, "pll_m_ud", NULL);
3111 clks[TEGRA210_CLK_PLL_M_UD] = clk;
3112
3113
3114 if (!tegra210_init_pllu()) {
3115 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
3116 480*1000*1000);
3117 clk_register_clkdev(clk, "pll_u_vco", NULL);
3118 clks[TEGRA210_CLK_PLL_U] = clk;
3119 }
3120
3121
3122 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
3123 clk_base + PLLU_BASE, 16, 4, 0,
3124 pll_vco_post_div_table, NULL);
3125 clk_register_clkdev(clk, "pll_u_out", NULL);
3126 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
3127
3128
3129 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
3130 clk_base + PLLU_OUTA, 0,
3131 TEGRA_DIVIDER_ROUND_UP,
3132 8, 8, 1, &pll_u_lock);
3133 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
3134 clk_base + PLLU_OUTA, 1, 0,
3135 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3136 clk_register_clkdev(clk, "pll_u_out1", NULL);
3137 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
3138
3139
3140 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
3141 clk_base + PLLU_OUTA, 0,
3142 TEGRA_DIVIDER_ROUND_UP,
3143 24, 8, 1, &pll_u_lock);
3144 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
3145 clk_base + PLLU_OUTA, 17, 16,
3146 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3147 clk_register_clkdev(clk, "pll_u_out2", NULL);
3148 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
3149
3150
3151 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
3152 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3153 22, 0, &pll_u_lock);
3154 clk_register_clkdev(clk, "pll_u_480M", NULL);
3155 clks[TEGRA210_CLK_PLL_U_480M] = clk;
3156
3157
3158 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
3159 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3160 23, 0, &pll_u_lock);
3161 clk_register_clkdev(clk, "pll_u_60M", NULL);
3162 clks[TEGRA210_CLK_PLL_U_60M] = clk;
3163
3164
3165 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
3166 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3167 25, 0, &pll_u_lock);
3168 clk_register_clkdev(clk, "pll_u_48M", NULL);
3169 clks[TEGRA210_CLK_PLL_U_48M] = clk;
3170
3171
3172 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3173 &pll_d_params, &pll_d_lock);
3174 clk_register_clkdev(clk, "pll_d", NULL);
3175 clks[TEGRA210_CLK_PLL_D] = clk;
3176
3177
3178 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
3179 CLK_SET_RATE_PARENT, 1, 2);
3180 clk_register_clkdev(clk, "pll_d_out0", NULL);
3181 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
3182
3183
3184 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
3185 clk_base, pmc, 0,
3186 &pll_re_vco_params,
3187 &pll_re_lock, pll_ref_freq);
3188 clk_register_clkdev(clk, "pll_re_vco", NULL);
3189 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
3190
3191 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
3192 clk_base + PLLRE_BASE, 16, 5, 0,
3193 pll_vco_post_div_table, &pll_re_lock);
3194 clk_register_clkdev(clk, "pll_re_out", NULL);
3195 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
3196
3197 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
3198 clk_base + PLLRE_OUT1, 0,
3199 TEGRA_DIVIDER_ROUND_UP,
3200 8, 8, 1, NULL);
3201 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
3202 clk_base + PLLRE_OUT1, 1, 0,
3203 CLK_SET_RATE_PARENT, 0, NULL);
3204 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
3205
3206
3207 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
3208 clk_base, 0, &pll_e_params, NULL);
3209 clk_register_clkdev(clk, "pll_e", NULL);
3210 clks[TEGRA210_CLK_PLL_E] = clk;
3211
3212
3213 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3214 0, &pll_c4_vco_params, NULL, pll_ref_freq);
3215 clk_register_clkdev(clk, "pll_c4_vco", NULL);
3216 clks[TEGRA210_CLK_PLL_C4] = clk;
3217
3218
3219 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
3220 clk_base + PLLC4_BASE, 19, 4, 0,
3221 pll_vco_post_div_table, NULL);
3222 clk_register_clkdev(clk, "pll_c4_out0", NULL);
3223 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
3224
3225
3226 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
3227 CLK_SET_RATE_PARENT, 1, 3);
3228 clk_register_clkdev(clk, "pll_c4_out1", NULL);
3229 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
3230
3231
3232 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
3233 CLK_SET_RATE_PARENT, 1, 5);
3234 clk_register_clkdev(clk, "pll_c4_out2", NULL);
3235 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
3236
3237
3238 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
3239 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3240 8, 8, 1, NULL);
3241 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
3242 clk_base + PLLC4_OUT, 1, 0,
3243 CLK_SET_RATE_PARENT, 0, NULL);
3244 clk_register_clkdev(clk, "pll_c4_out3", NULL);
3245 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
3246
3247
3248 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3249 0, &pll_dp_params, NULL);
3250 clk_register_clkdev(clk, "pll_dp", NULL);
3251 clks[TEGRA210_CLK_PLL_DP] = clk;
3252
3253
3254 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3255 0, &pll_d2_params, NULL);
3256 clk_register_clkdev(clk, "pll_d2", NULL);
3257 clks[TEGRA210_CLK_PLL_D2] = clk;
3258
3259
3260 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
3261 CLK_SET_RATE_PARENT, 1, 1);
3262 clk_register_clkdev(clk, "pll_d2_out0", NULL);
3263 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
3264
3265
3266 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
3267 CLK_SET_RATE_PARENT, 1, 2);
3268 clk_register_clkdev(clk, "pll_p_out2", NULL);
3269 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
3270
3271 }
3272
3273
3274 static void tegra210_wait_cpu_in_reset(u32 cpu)
3275 {
3276 unsigned int reg;
3277
3278 do {
3279 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3280 cpu_relax();
3281 } while (!(reg & (1 << cpu)));
3282 }
3283
3284 static void tegra210_disable_cpu_clock(u32 cpu)
3285 {
3286
3287 }
3288
3289 #ifdef CONFIG_PM_SLEEP
3290 static void tegra210_cpu_clock_suspend(void)
3291 {
3292
3293 tegra210_cpu_clk_sctx.clk_csite_src =
3294 readl(clk_base + CLK_SOURCE_CSITE);
3295 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3296 }
3297
3298 static void tegra210_cpu_clock_resume(void)
3299 {
3300 writel(tegra210_cpu_clk_sctx.clk_csite_src,
3301 clk_base + CLK_SOURCE_CSITE);
3302 }
3303 #endif
3304
3305 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
3306 .wait_for_reset = tegra210_wait_cpu_in_reset,
3307 .disable_clock = tegra210_disable_cpu_clock,
3308 #ifdef CONFIG_PM_SLEEP
3309 .suspend = tegra210_cpu_clock_suspend,
3310 .resume = tegra210_cpu_clock_resume,
3311 #endif
3312 };
3313
3314 static const struct of_device_id pmc_match[] __initconst = {
3315 { .compatible = "nvidia,tegra210-pmc" },
3316 { },
3317 };
3318
3319 static struct tegra_clk_init_table init_table[] __initdata = {
3320 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3321 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3322 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3323 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3324 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
3325 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
3326 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
3327 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
3328 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
3329 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3330 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3331 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3332 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3333 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3334 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3335 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3336 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
3337 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3338 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3339 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3340 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3341 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3342 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
3343 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
3344 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3345 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3346 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
3347 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3348 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3349 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3350 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3351 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
3352 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3353
3354 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
3355 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
3356 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3357 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3358 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3359 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3360 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3361 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3362 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3363 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3364 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3365 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
3366 { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3367 { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3368 { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3369 { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3370 { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3371 { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3372 { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3373 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3374 { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3375
3376 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3377 };
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387 static void __init tegra210_clock_apply_init_table(void)
3388 {
3389 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
3390 }
3391
3392
3393
3394
3395
3396
3397
3398 static void tegra210_car_barrier(void)
3399 {
3400 readl_relaxed(clk_base + RST_DFLL_DVCO);
3401 }
3402
3403
3404
3405
3406
3407
3408 static void tegra210_clock_assert_dfll_dvco_reset(void)
3409 {
3410 u32 v;
3411
3412 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3413 v |= (1 << DVFS_DFLL_RESET_SHIFT);
3414 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3415 tegra210_car_barrier();
3416 }
3417
3418
3419
3420
3421
3422
3423
3424 static void tegra210_clock_deassert_dfll_dvco_reset(void)
3425 {
3426 u32 v;
3427
3428 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3429 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
3430 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3431 tegra210_car_barrier();
3432 }
3433
3434 static int tegra210_reset_assert(unsigned long id)
3435 {
3436 if (id == TEGRA210_RST_DFLL_DVCO)
3437 tegra210_clock_assert_dfll_dvco_reset();
3438 else if (id == TEGRA210_RST_ADSP)
3439 writel(GENMASK(26, 21) | BIT(7),
3440 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3441 else
3442 return -EINVAL;
3443
3444 return 0;
3445 }
3446
3447 static int tegra210_reset_deassert(unsigned long id)
3448 {
3449 if (id == TEGRA210_RST_DFLL_DVCO)
3450 tegra210_clock_deassert_dfll_dvco_reset();
3451 else if (id == TEGRA210_RST_ADSP) {
3452 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3453
3454
3455
3456
3457
3458 udelay(5);
3459 writel(GENMASK(26, 22) | BIT(7),
3460 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3461 } else
3462 return -EINVAL;
3463
3464 return 0;
3465 }
3466
3467 static void tegra210_mbist_clk_init(void)
3468 {
3469 unsigned int i, j;
3470
3471 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {
3472 unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;
3473 struct clk_bulk_data *clk_data;
3474
3475 if (!num_clks)
3476 continue;
3477
3478 clk_data = kmalloc_array(num_clks, sizeof(*clk_data),
3479 GFP_KERNEL);
3480 if (WARN_ON(!clk_data))
3481 return;
3482
3483 tegra210_pg_mbist_war[i].clks = clk_data;
3484 for (j = 0; j < num_clks; j++) {
3485 int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];
3486 struct clk *clk = clks[clk_id];
3487
3488 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
3489 kfree(clk_data);
3490 tegra210_pg_mbist_war[i].clks = NULL;
3491 break;
3492 }
3493 clk_data[j].clk = clk;
3494 }
3495 }
3496 }
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507 static void __init tegra210_clock_init(struct device_node *np)
3508 {
3509 struct device_node *node;
3510 u32 value, clk_m_div;
3511
3512 clk_base = of_iomap(np, 0);
3513 if (!clk_base) {
3514 pr_err("ioremap tegra210 CAR failed\n");
3515 return;
3516 }
3517
3518 node = of_find_matching_node(NULL, pmc_match);
3519 if (!node) {
3520 pr_err("Failed to find pmc node\n");
3521 WARN_ON(1);
3522 return;
3523 }
3524
3525 pmc_base = of_iomap(node, 0);
3526 if (!pmc_base) {
3527 pr_err("Can't map pmc registers\n");
3528 WARN_ON(1);
3529 return;
3530 }
3531
3532 ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
3533 if (!ahub_base) {
3534 pr_err("ioremap tegra210 APE failed\n");
3535 return;
3536 }
3537
3538 dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);
3539 if (!dispa_base) {
3540 pr_err("ioremap tegra210 DISPA failed\n");
3541 return;
3542 }
3543
3544 vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);
3545 if (!vic_base) {
3546 pr_err("ioremap tegra210 VIC failed\n");
3547 return;
3548 }
3549
3550 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3551 TEGRA210_CAR_BANK_COUNT);
3552 if (!clks)
3553 return;
3554
3555 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3556 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
3557
3558 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3559 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
3560 &osc_freq, &pll_ref_freq) < 0)
3561 return;
3562
3563 tegra_fixed_clk_init(tegra210_clks);
3564 tegra210_pll_init(clk_base, pmc_base);
3565 tegra210_periph_clk_init(clk_base, pmc_base);
3566 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3567 tegra210_audio_plls,
3568 ARRAY_SIZE(tegra210_audio_plls), 24576000);
3569 tegra_pmc_clk_init(pmc_base, tegra210_clks);
3570
3571
3572 value = readl(clk_base + PLLD_BASE);
3573 value &= ~BIT(25);
3574 writel(value, clk_base + PLLD_BASE);
3575
3576 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
3577
3578 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
3579 &pll_x_params);
3580 tegra_init_special_resets(2, tegra210_reset_assert,
3581 tegra210_reset_deassert);
3582
3583 tegra_add_of_provider(np, of_clk_src_onecell_get);
3584 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
3585
3586 tegra210_mbist_clk_init();
3587
3588 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
3589 }
3590 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);