This source file includes following definitions.
- spear6xx_clk_init
1
2
3
4
5
6
7
8
9
10
11
12 #include <linux/clkdev.h>
13 #include <linux/io.h>
14 #include <linux/spinlock_types.h>
15 #include "clk.h"
16
17 static DEFINE_SPINLOCK(_lock);
18
19 #define PLL1_CTR (misc_base + 0x008)
20 #define PLL1_FRQ (misc_base + 0x00C)
21 #define PLL2_CTR (misc_base + 0x014)
22 #define PLL2_FRQ (misc_base + 0x018)
23 #define PLL_CLK_CFG (misc_base + 0x020)
24
25 #define MCTR_CLK_SHIFT 28
26 #define MCTR_CLK_MASK 3
27
28 #define CORE_CLK_CFG (misc_base + 0x024)
29
30 #define HCLK_RATIO_SHIFT 10
31 #define HCLK_RATIO_MASK 2
32 #define PCLK_RATIO_SHIFT 8
33 #define PCLK_RATIO_MASK 2
34
35 #define PERIP_CLK_CFG (misc_base + 0x028)
36
37 #define CLCD_CLK_SHIFT 2
38 #define CLCD_CLK_MASK 2
39 #define UART_CLK_SHIFT 4
40 #define UART_CLK_MASK 1
41 #define FIRDA_CLK_SHIFT 5
42 #define FIRDA_CLK_MASK 2
43 #define GPT0_CLK_SHIFT 8
44 #define GPT1_CLK_SHIFT 10
45 #define GPT2_CLK_SHIFT 11
46 #define GPT3_CLK_SHIFT 12
47 #define GPT_CLK_MASK 1
48
49 #define PERIP1_CLK_ENB (misc_base + 0x02C)
50
51 #define UART0_CLK_ENB 3
52 #define UART1_CLK_ENB 4
53 #define SSP0_CLK_ENB 5
54 #define SSP1_CLK_ENB 6
55 #define I2C_CLK_ENB 7
56 #define JPEG_CLK_ENB 8
57 #define FSMC_CLK_ENB 9
58 #define FIRDA_CLK_ENB 10
59 #define GPT2_CLK_ENB 11
60 #define GPT3_CLK_ENB 12
61 #define GPIO2_CLK_ENB 13
62 #define SSP2_CLK_ENB 14
63 #define ADC_CLK_ENB 15
64 #define GPT1_CLK_ENB 11
65 #define RTC_CLK_ENB 17
66 #define GPIO1_CLK_ENB 18
67 #define DMA_CLK_ENB 19
68 #define SMI_CLK_ENB 21
69 #define CLCD_CLK_ENB 22
70 #define GMAC_CLK_ENB 23
71 #define USBD_CLK_ENB 24
72 #define USBH0_CLK_ENB 25
73 #define USBH1_CLK_ENB 26
74
75 #define PRSC0_CLK_CFG (misc_base + 0x044)
76 #define PRSC1_CLK_CFG (misc_base + 0x048)
77 #define PRSC2_CLK_CFG (misc_base + 0x04C)
78
79 #define CLCD_CLK_SYNT (misc_base + 0x05C)
80 #define FIRDA_CLK_SYNT (misc_base + 0x060)
81 #define UART_CLK_SYNT (misc_base + 0x064)
82
83
84 static struct pll_rate_tbl pll_rtbl[] = {
85 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1},
86 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1},
87 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1},
88 };
89
90
91 static struct aux_rate_tbl aux_rtbl[] = {
92
93 {.xscale = 2, .yscale = 27, .eq = 0},
94 {.xscale = 2, .yscale = 8, .eq = 0},
95 {.xscale = 2, .yscale = 4, .eq = 0},
96 {.xscale = 1, .yscale = 2, .eq = 1},
97 };
98
99 static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
100 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
101 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
102 static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
103 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
104 static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
105 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
106 "pll2_clk", };
107
108
109 static struct gpt_rate_tbl gpt_rtbl[] = {
110
111 {.mscale = 4, .nscale = 0},
112 {.mscale = 2, .nscale = 0},
113 {.mscale = 1, .nscale = 0},
114 };
115
116 void __init spear6xx_clk_init(void __iomem *misc_base)
117 {
118 struct clk *clk, *clk1;
119
120 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
121 clk_register_clkdev(clk, "osc_32k_clk", NULL);
122
123 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
124 clk_register_clkdev(clk, "osc_30m_clk", NULL);
125
126
127 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
128 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
129 clk_register_clkdev(clk, NULL, "rtc-spear");
130
131
132 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
133 48000000);
134 clk_register_clkdev(clk, "pll3_clk", NULL);
135
136 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
137 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
138 &_lock, &clk1, NULL);
139 clk_register_clkdev(clk, "vco1_clk", NULL);
140 clk_register_clkdev(clk1, "pll1_clk", NULL);
141
142 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
143 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
144 &_lock, &clk1, NULL);
145 clk_register_clkdev(clk, "vco2_clk", NULL);
146 clk_register_clkdev(clk1, "pll2_clk", NULL);
147
148 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
149 1);
150 clk_register_clkdev(clk, NULL, "fc880000.wdt");
151
152
153 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
154 CLK_SET_RATE_PARENT, 1, 1);
155 clk_register_clkdev(clk, "cpu_clk", NULL);
156
157 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
158 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
159 HCLK_RATIO_MASK, 0, &_lock);
160 clk_register_clkdev(clk, "ahb_clk", NULL);
161
162 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
163 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
164 &_lock, &clk1);
165 clk_register_clkdev(clk, "uart_syn_clk", NULL);
166 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
167
168 clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
169 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
170 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
171 &_lock);
172 clk_register_clkdev(clk, "uart_mclk", NULL);
173
174 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
175 UART0_CLK_ENB, 0, &_lock);
176 clk_register_clkdev(clk, NULL, "d0000000.serial");
177
178 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
179 UART1_CLK_ENB, 0, &_lock);
180 clk_register_clkdev(clk, NULL, "d0080000.serial");
181
182 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
183 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
184 &_lock, &clk1);
185 clk_register_clkdev(clk, "firda_syn_clk", NULL);
186 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
187
188 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
189 ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
190 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
191 &_lock);
192 clk_register_clkdev(clk, "firda_mclk", NULL);
193
194 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
195 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
196 clk_register_clkdev(clk, NULL, "firda");
197
198 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
199 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
200 &_lock, &clk1);
201 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
202 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
203
204 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
205 ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
206 PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
207 &_lock);
208 clk_register_clkdev(clk, "clcd_mclk", NULL);
209
210 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
211 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
212 clk_register_clkdev(clk, NULL, "clcd");
213
214
215 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
216 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
217 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
218
219 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
220 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
221 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
222 clk_register_clkdev(clk, NULL, "gpt0");
223
224 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
225 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
226 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
227 clk_register_clkdev(clk, "gpt1_mclk", NULL);
228
229 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
230 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
231 clk_register_clkdev(clk, NULL, "gpt1");
232
233 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
234 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
235 clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
236
237 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
238 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
239 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
240 clk_register_clkdev(clk, "gpt2_mclk", NULL);
241
242 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
243 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
244 clk_register_clkdev(clk, NULL, "gpt2");
245
246 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
247 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
248 clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
249
250 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
251 ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
252 PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
253 clk_register_clkdev(clk, "gpt3_mclk", NULL);
254
255 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
256 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
257 clk_register_clkdev(clk, NULL, "gpt3");
258
259
260 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
261 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
262 clk_register_clkdev(clk, NULL, "e1800000.ehci");
263 clk_register_clkdev(clk, NULL, "e1900000.ohci");
264
265 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
266 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
267 clk_register_clkdev(clk, NULL, "e2000000.ehci");
268 clk_register_clkdev(clk, NULL, "e2100000.ohci");
269
270 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
271 USBD_CLK_ENB, 0, &_lock);
272 clk_register_clkdev(clk, NULL, "designware_udc");
273
274
275 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
276 1);
277 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
278
279 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
280 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
281 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
282 clk_register_clkdev(clk, "ddr_clk", NULL);
283
284 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
285 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
286 PCLK_RATIO_MASK, 0, &_lock);
287 clk_register_clkdev(clk, "apb_clk", NULL);
288
289 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
290 DMA_CLK_ENB, 0, &_lock);
291 clk_register_clkdev(clk, NULL, "fc400000.dma");
292
293 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
294 FSMC_CLK_ENB, 0, &_lock);
295 clk_register_clkdev(clk, NULL, "d1800000.flash");
296
297 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
298 GMAC_CLK_ENB, 0, &_lock);
299 clk_register_clkdev(clk, NULL, "e0800000.ethernet");
300
301 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
302 I2C_CLK_ENB, 0, &_lock);
303 clk_register_clkdev(clk, NULL, "d0200000.i2c");
304
305 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
306 JPEG_CLK_ENB, 0, &_lock);
307 clk_register_clkdev(clk, NULL, "jpeg");
308
309 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
310 SMI_CLK_ENB, 0, &_lock);
311 clk_register_clkdev(clk, NULL, "fc000000.flash");
312
313
314 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
315 ADC_CLK_ENB, 0, &_lock);
316 clk_register_clkdev(clk, NULL, "d820b000.adc");
317
318 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
319 clk_register_clkdev(clk, NULL, "f0100000.gpio");
320
321 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
322 GPIO1_CLK_ENB, 0, &_lock);
323 clk_register_clkdev(clk, NULL, "fc980000.gpio");
324
325 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
326 GPIO2_CLK_ENB, 0, &_lock);
327 clk_register_clkdev(clk, NULL, "d8100000.gpio");
328
329 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
330 SSP0_CLK_ENB, 0, &_lock);
331 clk_register_clkdev(clk, NULL, "ssp-pl022.0");
332
333 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
334 SSP1_CLK_ENB, 0, &_lock);
335 clk_register_clkdev(clk, NULL, "ssp-pl022.1");
336
337 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
338 SSP2_CLK_ENB, 0, &_lock);
339 clk_register_clkdev(clk, NULL, "ssp-pl022.2");
340 }