drivers/clk/spear/spear1340

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This source file includes following definitions.
spear1340_clk_init
   1 /*
   2  * arch/arm/mach-spear13xx/spear1340_clock.c
   3  *
   4  * SPEAr1340 machine clock framework source file
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Viresh Kumar <vireshk@kernel.org>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13 
  14 #include <linux/clkdev.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/spinlock_types.h>
  19 #include "clk.h"
  20 
  21 /* Clock Configuration Registers */
  22 #define SPEAR1340_SYS_CLK_CTRL                  (misc_base + 0x200)
  23         #define SPEAR1340_HCLK_SRC_SEL_SHIFT    27
  24         #define SPEAR1340_HCLK_SRC_SEL_MASK     1
  25         #define SPEAR1340_SCLK_SRC_SEL_SHIFT    23
  26         #define SPEAR1340_SCLK_SRC_SEL_MASK     3
  27 
  28 /* PLL related registers and bit values */
  29 #define SPEAR1340_PLL_CFG                       (misc_base + 0x210)
  30         /* PLL_CFG bit values */
  31         #define SPEAR1340_CLCD_SYNT_CLK_MASK            1
  32         #define SPEAR1340_CLCD_SYNT_CLK_SHIFT           31
  33         #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT         29
  34         #define SPEAR1340_GEN_SYNT_CLK_MASK             2
  35         #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT         27
  36         #define SPEAR1340_PLL_CLK_MASK                  2
  37         #define SPEAR1340_PLL3_CLK_SHIFT                24
  38         #define SPEAR1340_PLL2_CLK_SHIFT                22
  39         #define SPEAR1340_PLL1_CLK_SHIFT                20
  40 
  41 #define SPEAR1340_PLL1_CTR                      (misc_base + 0x214)
  42 #define SPEAR1340_PLL1_FRQ                      (misc_base + 0x218)
  43 #define SPEAR1340_PLL2_CTR                      (misc_base + 0x220)
  44 #define SPEAR1340_PLL2_FRQ                      (misc_base + 0x224)
  45 #define SPEAR1340_PLL3_CTR                      (misc_base + 0x22C)
  46 #define SPEAR1340_PLL3_FRQ                      (misc_base + 0x230)
  47 #define SPEAR1340_PLL4_CTR                      (misc_base + 0x238)
  48 #define SPEAR1340_PLL4_FRQ                      (misc_base + 0x23C)
  49 #define SPEAR1340_PERIP_CLK_CFG                 (misc_base + 0x244)
  50         /* PERIP_CLK_CFG bit values */
  51         #define SPEAR1340_SPDIF_CLK_MASK                1
  52         #define SPEAR1340_SPDIF_OUT_CLK_SHIFT           15
  53         #define SPEAR1340_SPDIF_IN_CLK_SHIFT            14
  54         #define SPEAR1340_GPT3_CLK_SHIFT                13
  55         #define SPEAR1340_GPT2_CLK_SHIFT                12
  56         #define SPEAR1340_GPT_CLK_MASK                  1
  57         #define SPEAR1340_GPT1_CLK_SHIFT                9
  58         #define SPEAR1340_GPT0_CLK_SHIFT                8
  59         #define SPEAR1340_UART_CLK_MASK                 2
  60         #define SPEAR1340_UART1_CLK_SHIFT               6
  61         #define SPEAR1340_UART0_CLK_SHIFT               4
  62         #define SPEAR1340_CLCD_CLK_MASK                 2
  63         #define SPEAR1340_CLCD_CLK_SHIFT                2
  64         #define SPEAR1340_C3_CLK_MASK                   1
  65         #define SPEAR1340_C3_CLK_SHIFT                  1
  66 
  67 #define SPEAR1340_GMAC_CLK_CFG                  (misc_base + 0x248)
  68         #define SPEAR1340_GMAC_PHY_CLK_MASK             1
  69         #define SPEAR1340_GMAC_PHY_CLK_SHIFT            2
  70         #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK       2
  71         #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT      0
  72 
  73 #define SPEAR1340_I2S_CLK_CFG                   (misc_base + 0x24C)
  74         /* I2S_CLK_CFG register mask */
  75         #define SPEAR1340_I2S_SCLK_X_MASK               0x1F
  76         #define SPEAR1340_I2S_SCLK_X_SHIFT              27
  77         #define SPEAR1340_I2S_SCLK_Y_MASK               0x1F
  78         #define SPEAR1340_I2S_SCLK_Y_SHIFT              22
  79         #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT         21
  80         #define SPEAR1340_I2S_SCLK_SYNTH_ENB            20
  81         #define SPEAR1340_I2S_PRS1_CLK_X_MASK           0xFF
  82         #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT          12
  83         #define SPEAR1340_I2S_PRS1_CLK_Y_MASK           0xFF
  84         #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT          4
  85         #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT         3
  86         #define SPEAR1340_I2S_REF_SEL_MASK              1
  87         #define SPEAR1340_I2S_REF_SHIFT                 2
  88         #define SPEAR1340_I2S_SRC_CLK_MASK              2
  89         #define SPEAR1340_I2S_SRC_CLK_SHIFT             0
  90 
  91 #define SPEAR1340_C3_CLK_SYNT                   (misc_base + 0x250)
  92 #define SPEAR1340_UART0_CLK_SYNT                (misc_base + 0x254)
  93 #define SPEAR1340_UART1_CLK_SYNT                (misc_base + 0x258)
  94 #define SPEAR1340_GMAC_CLK_SYNT                 (misc_base + 0x25C)
  95 #define SPEAR1340_SDHCI_CLK_SYNT                (misc_base + 0x260)
  96 #define SPEAR1340_CFXD_CLK_SYNT                 (misc_base + 0x264)
  97 #define SPEAR1340_ADC_CLK_SYNT                  (misc_base + 0x270)
  98 #define SPEAR1340_AMBA_CLK_SYNT                 (misc_base + 0x274)
  99 #define SPEAR1340_CLCD_CLK_SYNT                 (misc_base + 0x27C)
 100 #define SPEAR1340_SYS_CLK_SYNT                  (misc_base + 0x284)
 101 #define SPEAR1340_GEN_CLK_SYNT0                 (misc_base + 0x28C)
 102 #define SPEAR1340_GEN_CLK_SYNT1                 (misc_base + 0x294)
 103 #define SPEAR1340_GEN_CLK_SYNT2                 (misc_base + 0x29C)
 104 #define SPEAR1340_GEN_CLK_SYNT3                 (misc_base + 0x304)
 105 #define SPEAR1340_PERIP1_CLK_ENB                (misc_base + 0x30C)
 106         #define SPEAR1340_RTC_CLK_ENB                   31
 107         #define SPEAR1340_ADC_CLK_ENB                   30
 108         #define SPEAR1340_C3_CLK_ENB                    29
 109         #define SPEAR1340_CLCD_CLK_ENB                  27
 110         #define SPEAR1340_DMA_CLK_ENB                   25
 111         #define SPEAR1340_GPIO1_CLK_ENB                 24
 112         #define SPEAR1340_GPIO0_CLK_ENB                 23
 113         #define SPEAR1340_GPT1_CLK_ENB                  22
 114         #define SPEAR1340_GPT0_CLK_ENB                  21
 115         #define SPEAR1340_I2S_PLAY_CLK_ENB              20
 116         #define SPEAR1340_I2S_REC_CLK_ENB               19
 117         #define SPEAR1340_I2C0_CLK_ENB                  18
 118         #define SPEAR1340_SSP_CLK_ENB                   17
 119         #define SPEAR1340_UART0_CLK_ENB                 15
 120         #define SPEAR1340_PCIE_SATA_CLK_ENB             12
 121         #define SPEAR1340_UOC_CLK_ENB                   11
 122         #define SPEAR1340_UHC1_CLK_ENB                  10
 123         #define SPEAR1340_UHC0_CLK_ENB                  9
 124         #define SPEAR1340_GMAC_CLK_ENB                  8
 125         #define SPEAR1340_CFXD_CLK_ENB                  7
 126         #define SPEAR1340_SDHCI_CLK_ENB                 6
 127         #define SPEAR1340_SMI_CLK_ENB                   5
 128         #define SPEAR1340_FSMC_CLK_ENB                  4
 129         #define SPEAR1340_SYSRAM0_CLK_ENB               3
 130         #define SPEAR1340_SYSRAM1_CLK_ENB               2
 131         #define SPEAR1340_SYSROM_CLK_ENB                1
 132         #define SPEAR1340_BUS_CLK_ENB                   0
 133 
 134 #define SPEAR1340_PERIP2_CLK_ENB                (misc_base + 0x310)
 135         #define SPEAR1340_THSENS_CLK_ENB                8
 136         #define SPEAR1340_I2S_REF_PAD_CLK_ENB           7
 137         #define SPEAR1340_ACP_CLK_ENB                   6
 138         #define SPEAR1340_GPT3_CLK_ENB                  5
 139         #define SPEAR1340_GPT2_CLK_ENB                  4
 140         #define SPEAR1340_KBD_CLK_ENB                   3
 141         #define SPEAR1340_CPU_DBG_CLK_ENB               2
 142         #define SPEAR1340_DDR_CORE_CLK_ENB              1
 143         #define SPEAR1340_DDR_CTRL_CLK_ENB              0
 144 
 145 #define SPEAR1340_PERIP3_CLK_ENB                (misc_base + 0x314)
 146         #define SPEAR1340_PLGPIO_CLK_ENB                18
 147         #define SPEAR1340_VIDEO_DEC_CLK_ENB             16
 148         #define SPEAR1340_VIDEO_ENC_CLK_ENB             15
 149         #define SPEAR1340_SPDIF_OUT_CLK_ENB             13
 150         #define SPEAR1340_SPDIF_IN_CLK_ENB              12
 151         #define SPEAR1340_VIDEO_IN_CLK_ENB              11
 152         #define SPEAR1340_CAM0_CLK_ENB                  10
 153         #define SPEAR1340_CAM1_CLK_ENB                  9
 154         #define SPEAR1340_CAM2_CLK_ENB                  8
 155         #define SPEAR1340_CAM3_CLK_ENB                  7
 156         #define SPEAR1340_MALI_CLK_ENB                  6
 157         #define SPEAR1340_CEC0_CLK_ENB                  5
 158         #define SPEAR1340_CEC1_CLK_ENB                  4
 159         #define SPEAR1340_PWM_CLK_ENB                   3
 160         #define SPEAR1340_I2C1_CLK_ENB                  2
 161         #define SPEAR1340_UART1_CLK_ENB                 1
 162 
 163 static DEFINE_SPINLOCK(_lock);
 164 
 165 /* pll rate configuration table, in ascending order of rates */
 166 static struct pll_rate_tbl pll_rtbl[] = {
 167         /* PCLK 24MHz */
 168         {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
 169         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
 170         {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
 171         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
 172         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
 173         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
 174         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 175         {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
 176 };
 177 
 178 /* vco-pll4 rate configuration table, in ascending order of rates */
 179 static struct pll_rate_tbl pll4_rtbl[] = {
 180         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
 181         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
 182         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
 183         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 184 };
 185 
 186 /*
 187  * All below entries generate 166 MHz for
 188  * different values of vco1div2
 189  */
 190 static struct frac_rate_tbl amba_synth_rtbl[] = {
 191         {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
 192         {.div = 0x06062}, /* for vco1div2 = 500 MHz */
 193         {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
 194         {.div = 0x04000}, /* for vco1div2 = 332 MHz */
 195         {.div = 0x03031}, /* for vco1div2 = 250 MHz */
 196         {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
 197 };
 198 
 199 /*
 200  * Synthesizer Clock derived from vcodiv2. This clock is one of the
 201  * possible clocks to feed cpu directly.
 202  * We can program this synthesizer to make cpu run on different clock
 203  * frequencies.
 204  * Following table provides configuration values to let cpu run on 200,
 205  * 250, 332, 400 or 500 MHz considering different possibilites of input
 206  * (vco1div2) clock.
 207  *
 208  * --------------------------------------------------------------------
 209  * vco1div2(Mhz)        fout(Mhz)       cpuclk = fout/2         div
 210  * --------------------------------------------------------------------
 211  * 400                  200             100                     0x04000
 212  * 400                  250             125                     0x03333
 213  * 400                  332             166                     0x0268D
 214  * 400                  400             200                     0x02000
 215  * --------------------------------------------------------------------
 216  * 500                  200             100                     0x05000
 217  * 500                  250             125                     0x04000
 218  * 500                  332             166                     0x03031
 219  * 500                  400             200                     0x02800
 220  * 500                  500             250                     0x02000
 221  * --------------------------------------------------------------------
 222  * 600                  200             100                     0x06000
 223  * 600                  250             125                     0x04CCE
 224  * 600                  332             166                     0x039D5
 225  * 600                  400             200                     0x03000
 226  * 600                  500             250                     0x02666
 227  * --------------------------------------------------------------------
 228  * 664                  200             100                     0x06a38
 229  * 664                  250             125                     0x054FD
 230  * 664                  332             166                     0x04000
 231  * 664                  400             200                     0x0351E
 232  * 664                  500             250                     0x02A7E
 233  * --------------------------------------------------------------------
 234  * 800                  200             100                     0x08000
 235  * 800                  250             125                     0x06666
 236  * 800                  332             166                     0x04D18
 237  * 800                  400             200                     0x04000
 238  * 800                  500             250                     0x03333
 239  * --------------------------------------------------------------------
 240  * sys rate configuration table is in descending order of divisor.
 241  */
 242 static struct frac_rate_tbl sys_synth_rtbl[] = {
 243         {.div = 0x08000},
 244         {.div = 0x06a38},
 245         {.div = 0x06666},
 246         {.div = 0x06000},
 247         {.div = 0x054FD},
 248         {.div = 0x05000},
 249         {.div = 0x04D18},
 250         {.div = 0x04CCE},
 251         {.div = 0x04000},
 252         {.div = 0x039D5},
 253         {.div = 0x0351E},
 254         {.div = 0x03333},
 255         {.div = 0x03031},
 256         {.div = 0x03000},
 257         {.div = 0x02A7E},
 258         {.div = 0x02800},
 259         {.div = 0x0268D},
 260         {.div = 0x02666},
 261         {.div = 0x02000},
 262 };
 263 
 264 /* aux rate configuration table, in ascending order of rates */
 265 static struct aux_rate_tbl aux_rtbl[] = {
 266         /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */
 267         {.xscale = 5, .yscale = 122, .eq = 0},
 268         /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */
 269         {.xscale = 10, .yscale = 204, .eq = 0},
 270         /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */
 271         {.xscale = 4, .yscale = 25, .eq = 0},
 272         /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */
 273         {.xscale = 4, .yscale = 21, .eq = 0},
 274         /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */
 275         {.xscale = 5, .yscale = 18, .eq = 0},
 276         /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */
 277         {.xscale = 2, .yscale = 6, .eq = 0},
 278         /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */
 279         {.xscale = 5, .yscale = 12, .eq = 0},
 280         /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */
 281         {.xscale = 2, .yscale = 4, .eq = 0},
 282         /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */
 283         {.xscale = 5, .yscale = 18, .eq = 1},
 284         /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */
 285         {.xscale = 1, .yscale = 3, .eq = 1},
 286         /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */
 287         {.xscale = 5, .yscale = 12, .eq = 1},
 288         /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */
 289         {.xscale = 1, .yscale = 2, .eq = 1},
 290 };
 291 
 292 /* gmac rate configuration table, in ascending order of rates */
 293 static struct aux_rate_tbl gmac_rtbl[] = {
 294         /* For gmac phy input clk */
 295         {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
 296         {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
 297         {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
 298         {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
 299 };
 300 
 301 /* clcd rate configuration table, in ascending order of rates */
 302 static struct frac_rate_tbl clcd_rtbl[] = {
 303         {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
 304         {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
 305         {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
 306         {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
 307         {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
 308         {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
 309         {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
 310         {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
 311         {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
 312         {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
 313         {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
 314         {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
 315         {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
 316         {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
 317         {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
 318         {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
 319         {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
 320         {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
 321         {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
 322         {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
 323 };
 324 
 325 /* i2s prescaler1 masks */
 326 static const struct aux_clk_masks i2s_prs1_masks = {
 327         .eq_sel_mask = AUX_EQ_SEL_MASK,
 328         .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
 329         .eq1_mask = AUX_EQ1_SEL,
 330         .eq2_mask = AUX_EQ2_SEL,
 331         .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
 332         .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
 333         .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
 334         .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
 335 };
 336 
 337 /* i2s sclk (bit clock) syynthesizers masks */
 338 static const struct aux_clk_masks i2s_sclk_masks = {
 339         .eq_sel_mask = AUX_EQ_SEL_MASK,
 340         .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
 341         .eq1_mask = AUX_EQ1_SEL,
 342         .eq2_mask = AUX_EQ2_SEL,
 343         .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
 344         .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
 345         .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
 346         .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
 347         .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
 348 };
 349 
 350 /* i2s prs1 aux rate configuration table, in ascending order of rates */
 351 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
 352         /* For parent clk = 49.152 MHz */
 353         {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
 354         {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
 355         {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
 356         {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
 357 
 358         /*
 359          * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
 360          * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
 361          */
 362         {.xscale = 1, .yscale = 3, .eq = 0},
 363 
 364         /* For parent clk = 49.152 MHz */
 365         {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
 366         {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
 367 };
 368 
 369 /* i2s sclk aux rate configuration table, in ascending order of rates */
 370 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
 371         /* For sclk = ref_clk * x/2/y */
 372         {.xscale = 1, .yscale = 4, .eq = 0},
 373         {.xscale = 1, .yscale = 2, .eq = 0},
 374 };
 375 
 376 /* adc rate configuration table, in ascending order of rates */
 377 /* possible adc range is 2.5 MHz to 20 MHz. */
 378 static struct aux_rate_tbl adc_rtbl[] = {
 379         /* For ahb = 166.67 MHz */
 380         {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
 381         {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
 382         {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
 383         {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
 384 };
 385 
 386 /* General synth rate configuration table, in ascending order of rates */
 387 static struct frac_rate_tbl gen_rtbl[] = {
 388         {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
 389         {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
 390         {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
 391         {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
 392         {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
 393         {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
 394         {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
 395         {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
 396         {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
 397         {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
 398         {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
 399         {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
 400         {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
 401         {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
 402         {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
 403         {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
 404         {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
 405         {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
 406         {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
 407         {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
 408         {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
 409         {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
 410         {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
 411         {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
 412         {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
 413 };
 414 
 415 /* clock parents */
 416 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
 417 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
 418         "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
 419 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
 420 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 421 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
 422         "uart0_syn_gclk", };
 423 static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
 424         "uart1_syn_gclk", };
 425 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
 426 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
 427         "osc_25m_clk", };
 428 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
 429 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
 430 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
 431 static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
 432         "i2s_src_pad_clk", };
 433 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
 434 static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
 435 static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
 436 
 437 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 438         "pll3_clk", };
 439 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
 440         "pll2_clk", };
 441 
 442 void __init spear1340_clk_init(void __iomem *misc_base)
 443 {
 444         struct clk *clk, *clk1;
 445 
 446         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
 447         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 448 
 449         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
 450         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 451 
 452         clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
 453         clk_register_clkdev(clk, "osc_25m_clk", NULL);
 454 
 455         clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
 456         clk_register_clkdev(clk, "gmii_pad_clk", NULL);
 457 
 458         clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
 459                                       12288000);
 460         clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
 461 
 462         /* clock derived from 32 KHz osc clk */
 463         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 464                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
 465                         &_lock);
 466         clk_register_clkdev(clk, NULL, "e0580000.rtc");
 467 
 468         /* clock derived from 24 or 25 MHz osc clk */
 469         /* vco-pll */
 470         clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
 471                         ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
 472                         SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
 473                         SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 474         clk_register_clkdev(clk, "vco1_mclk", NULL);
 475         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
 476                         SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
 477                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 478         clk_register_clkdev(clk, "vco1_clk", NULL);
 479         clk_register_clkdev(clk1, "pll1_clk", NULL);
 480 
 481         clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
 482                         ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
 483                         SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
 484                         SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 485         clk_register_clkdev(clk, "vco2_mclk", NULL);
 486         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
 487                         SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
 488                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 489         clk_register_clkdev(clk, "vco2_clk", NULL);
 490         clk_register_clkdev(clk1, "pll2_clk", NULL);
 491 
 492         clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
 493                         ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
 494                         SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
 495                         SPEAR1340_PLL_CLK_MASK, 0, &_lock);
 496         clk_register_clkdev(clk, "vco3_mclk", NULL);
 497         clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
 498                         SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
 499                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 500         clk_register_clkdev(clk, "vco3_clk", NULL);
 501         clk_register_clkdev(clk1, "pll3_clk", NULL);
 502 
 503         clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
 504                         0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
 505                         ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
 506         clk_register_clkdev(clk, "vco4_clk", NULL);
 507         clk_register_clkdev(clk1, "pll4_clk", NULL);
 508 
 509         clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
 510                         48000000);
 511         clk_register_clkdev(clk, "pll5_clk", NULL);
 512 
 513         clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
 514                         25000000);
 515         clk_register_clkdev(clk, "pll6_clk", NULL);
 516 
 517         /* vco div n clocks */
 518         clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
 519                         2);
 520         clk_register_clkdev(clk, "vco1div2_clk", NULL);
 521 
 522         clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
 523                         4);
 524         clk_register_clkdev(clk, "vco1div4_clk", NULL);
 525 
 526         clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
 527                         2);
 528         clk_register_clkdev(clk, "vco2div2_clk", NULL);
 529 
 530         clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
 531                         2);
 532         clk_register_clkdev(clk, "vco3div2_clk", NULL);
 533 
 534         /* peripherals */
 535         clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
 536                         128);
 537         clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
 538                         SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
 539                         &_lock);
 540         clk_register_clkdev(clk, NULL, "e07008c4.thermal");
 541 
 542         /* clock derived from pll4 clk */
 543         clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
 544                         1);
 545         clk_register_clkdev(clk, "ddr_clk", NULL);
 546 
 547         /* clock derived from pll1 clk */
 548         clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
 549                         SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
 550                         ARRAY_SIZE(sys_synth_rtbl), &_lock);
 551         clk_register_clkdev(clk, "sys_syn_clk", NULL);
 552 
 553         clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
 554                         SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
 555                         ARRAY_SIZE(amba_synth_rtbl), &_lock);
 556         clk_register_clkdev(clk, "amba_syn_clk", NULL);
 557 
 558         clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
 559                         ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
 560                         SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
 561                         SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
 562         clk_register_clkdev(clk, "sys_mclk", NULL);
 563 
 564         clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
 565                         2);
 566         clk_register_clkdev(clk, "cpu_clk", NULL);
 567 
 568         clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
 569                         3);
 570         clk_register_clkdev(clk, "cpu_div3_clk", NULL);
 571 
 572         clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
 573                         2);
 574         clk_register_clkdev(clk, NULL, "ec800620.wdt");
 575 
 576         clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
 577                         2);
 578         clk_register_clkdev(clk, NULL, "smp_twd");
 579 
 580         clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
 581                         ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
 582                         SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
 583                         SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
 584         clk_register_clkdev(clk, "ahb_clk", NULL);
 585 
 586         clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
 587                         2);
 588         clk_register_clkdev(clk, "apb_clk", NULL);
 589 
 590         /* gpt clocks */
 591         clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
 592                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 593                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
 594                         SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 595         clk_register_clkdev(clk, "gpt0_mclk", NULL);
 596         clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 597                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
 598                         &_lock);
 599         clk_register_clkdev(clk, NULL, "gpt0");
 600 
 601         clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
 602                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 603                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
 604                         SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 605         clk_register_clkdev(clk, "gpt1_mclk", NULL);
 606         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 607                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
 608                         &_lock);
 609         clk_register_clkdev(clk, NULL, "gpt1");
 610 
 611         clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
 612                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 613                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
 614                         SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 615         clk_register_clkdev(clk, "gpt2_mclk", NULL);
 616         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 617                         SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
 618                         &_lock);
 619         clk_register_clkdev(clk, NULL, "gpt2");
 620 
 621         clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
 622                         ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
 623                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
 624                         SPEAR1340_GPT_CLK_MASK, 0, &_lock);
 625         clk_register_clkdev(clk, "gpt3_mclk", NULL);
 626         clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 627                         SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
 628                         &_lock);
 629         clk_register_clkdev(clk, NULL, "gpt3");
 630 
 631         /* others */
 632         clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
 633                         "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
 634                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 635         clk_register_clkdev(clk, "uart0_syn_clk", NULL);
 636         clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
 637 
 638         clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
 639                         ARRAY_SIZE(uart0_parents),
 640                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 641                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
 642                         SPEAR1340_UART_CLK_MASK, 0, &_lock);
 643         clk_register_clkdev(clk, "uart0_mclk", NULL);
 644 
 645         clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
 646                         CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
 647                         SPEAR1340_UART0_CLK_ENB, 0, &_lock);
 648         clk_register_clkdev(clk, NULL, "e0000000.serial");
 649 
 650         clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
 651                         "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
 652                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 653         clk_register_clkdev(clk, "uart1_syn_clk", NULL);
 654         clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
 655 
 656         clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
 657                         ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
 658                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
 659                         SPEAR1340_UART_CLK_MASK, 0, &_lock);
 660         clk_register_clkdev(clk, "uart1_mclk", NULL);
 661 
 662         clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
 663                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
 664                         &_lock);
 665         clk_register_clkdev(clk, NULL, "b4100000.serial");
 666 
 667         clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
 668                         "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
 669                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 670         clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
 671         clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
 672 
 673         clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
 674                         CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
 675                         SPEAR1340_SDHCI_CLK_ENB, 0, &_lock);
 676         clk_register_clkdev(clk, NULL, "b3000000.sdhci");
 677 
 678         clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
 679                         0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl,
 680                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 681         clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
 682         clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
 683 
 684         clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
 685                         CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
 686                         SPEAR1340_CFXD_CLK_ENB, 0, &_lock);
 687         clk_register_clkdev(clk, NULL, "b2800000.cf");
 688         clk_register_clkdev(clk, NULL, "arasan_xd");
 689 
 690         clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
 691                         SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl,
 692                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 693         clk_register_clkdev(clk, "c3_syn_clk", NULL);
 694         clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 695 
 696         clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
 697                         ARRAY_SIZE(c3_parents),
 698                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 699                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
 700                         SPEAR1340_C3_CLK_MASK, 0, &_lock);
 701         clk_register_clkdev(clk, "c3_mclk", NULL);
 702 
 703         clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT,
 704                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
 705                         &_lock);
 706         clk_register_clkdev(clk, NULL, "e1800000.c3");
 707 
 708         /* gmac */
 709         clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
 710                         ARRAY_SIZE(gmac_phy_input_parents),
 711                         CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
 712                         SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
 713                         SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 714         clk_register_clkdev(clk, "phy_input_mclk", NULL);
 715 
 716         clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
 717                         0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl,
 718                         ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
 719         clk_register_clkdev(clk, "phy_syn_clk", NULL);
 720         clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 721 
 722         clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
 723                         ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
 724                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
 725                         SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
 726         clk_register_clkdev(clk, "stmmacphy.0", NULL);
 727 
 728         /* clcd */
 729         clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
 730                         ARRAY_SIZE(clcd_synth_parents),
 731                         CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
 732                         SPEAR1340_CLCD_SYNT_CLK_SHIFT,
 733                         SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
 734         clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 735 
 736         clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
 737                         SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
 738                         ARRAY_SIZE(clcd_rtbl), &_lock);
 739         clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 740 
 741         clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
 742                         ARRAY_SIZE(clcd_pixel_parents),
 743                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 744                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
 745                         SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
 746         clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
 747 
 748         clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 749                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
 750                         &_lock);
 751         clk_register_clkdev(clk, NULL, "e1000000.clcd");
 752 
 753         /* i2s */
 754         clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
 755                         ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
 756                         SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
 757                         SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
 758         clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 759 
 760         clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
 761                         CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG,
 762                         &i2s_prs1_masks, i2s_prs1_rtbl,
 763                         ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
 764         clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 765 
 766         clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
 767                         ARRAY_SIZE(i2s_ref_parents),
 768                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 769                         SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
 770                         SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
 771         clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
 772 
 773         clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
 774                         SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
 775                         0, &_lock);
 776         clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
 777 
 778         clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
 779                         0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks,
 780                         i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock,
 781                         &clk1);
 782         clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
 783         clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
 784 
 785         /* clock derived from ahb clk */
 786         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
 787                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
 788                         &_lock);
 789         clk_register_clkdev(clk, NULL, "e0280000.i2c");
 790 
 791         clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
 792                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
 793                         &_lock);
 794         clk_register_clkdev(clk, NULL, "b4000000.i2c");
 795 
 796         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
 797                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
 798                         &_lock);
 799         clk_register_clkdev(clk, NULL, "ea800000.dma");
 800         clk_register_clkdev(clk, NULL, "eb000000.dma");
 801 
 802         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
 803                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
 804                         &_lock);
 805         clk_register_clkdev(clk, NULL, "e2000000.eth");
 806 
 807         clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
 808                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
 809                         &_lock);
 810         clk_register_clkdev(clk, NULL, "b0000000.flash");
 811 
 812         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
 813                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
 814                         &_lock);
 815         clk_register_clkdev(clk, NULL, "ea000000.flash");
 816 
 817         clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
 818                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
 819                         &_lock);
 820         clk_register_clkdev(clk, NULL, "e4000000.ohci");
 821         clk_register_clkdev(clk, NULL, "e4800000.ehci");
 822 
 823         clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
 824                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
 825                         &_lock);
 826         clk_register_clkdev(clk, NULL, "e5000000.ohci");
 827         clk_register_clkdev(clk, NULL, "e5800000.ehci");
 828 
 829         clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
 830                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
 831                         &_lock);
 832         clk_register_clkdev(clk, NULL, "e3800000.otg");
 833 
 834         clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
 835                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
 836                         0, &_lock);
 837         clk_register_clkdev(clk, NULL, "b1000000.pcie");
 838         clk_register_clkdev(clk, NULL, "b1000000.ahci");
 839 
 840         clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
 841                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
 842                         &_lock);
 843         clk_register_clkdev(clk, "sysram0_clk", NULL);
 844 
 845         clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
 846                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
 847                         &_lock);
 848         clk_register_clkdev(clk, "sysram1_clk", NULL);
 849 
 850         clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
 851                         0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
 852                         ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
 853         clk_register_clkdev(clk, "adc_syn_clk", NULL);
 854         clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
 855 
 856         clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
 857                         CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
 858                         SPEAR1340_ADC_CLK_ENB, 0, &_lock);
 859         clk_register_clkdev(clk, NULL, "e0080000.adc");
 860 
 861         /* clock derived from apb clk */
 862         clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
 863                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
 864                         &_lock);
 865         clk_register_clkdev(clk, NULL, "e0100000.spi");
 866 
 867         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
 868                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
 869                         &_lock);
 870         clk_register_clkdev(clk, NULL, "e0600000.gpio");
 871 
 872         clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
 873                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
 874                         &_lock);
 875         clk_register_clkdev(clk, NULL, "e0680000.gpio");
 876 
 877         clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
 878                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
 879                         &_lock);
 880         clk_register_clkdev(clk, NULL, "b2400000.i2s-play");
 881 
 882         clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
 883                         SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
 884                         &_lock);
 885         clk_register_clkdev(clk, NULL, "b2000000.i2s-rec");
 886 
 887         clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
 888                         SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
 889                         &_lock);
 890         clk_register_clkdev(clk, NULL, "e0300000.kbd");
 891 
 892         /* RAS clks */
 893         clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
 894                         ARRAY_SIZE(gen_synth0_1_parents),
 895                         CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
 896                         SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
 897                         SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
 898         clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
 899 
 900         clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
 901                         ARRAY_SIZE(gen_synth2_3_parents),
 902                         CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
 903                         SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
 904                         SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
 905         clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
 906 
 907         clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
 908                         SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 909                         &_lock);
 910         clk_register_clkdev(clk, "gen_syn0_clk", NULL);
 911 
 912         clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
 913                         SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 914                         &_lock);
 915         clk_register_clkdev(clk, "gen_syn1_clk", NULL);
 916 
 917         clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
 918                         SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 919                         &_lock);
 920         clk_register_clkdev(clk, "gen_syn2_clk", NULL);
 921 
 922         clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
 923                         SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 924                         &_lock);
 925         clk_register_clkdev(clk, "gen_syn3_clk", NULL);
 926 
 927         clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk",
 928                         CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
 929                         SPEAR1340_MALI_CLK_ENB, 0, &_lock);
 930         clk_register_clkdev(clk, NULL, "mali");
 931 
 932         clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
 933                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
 934                         &_lock);
 935         clk_register_clkdev(clk, NULL, "spear_cec.0");
 936 
 937         clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
 938                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
 939                         &_lock);
 940         clk_register_clkdev(clk, NULL, "spear_cec.1");
 941 
 942         clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
 943                         ARRAY_SIZE(spdif_out_parents),
 944                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 945                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
 946                         SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
 947         clk_register_clkdev(clk, "spdif_out_mclk", NULL);
 948 
 949         clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk",
 950                         CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
 951                         SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock);
 952         clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
 953 
 954         clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
 955                         ARRAY_SIZE(spdif_in_parents),
 956                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 957                         SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
 958                         SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
 959         clk_register_clkdev(clk, "spdif_in_mclk", NULL);
 960 
 961         clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk",
 962                         CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
 963                         SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
 964         clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
 965 
 966         clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
 967                         SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
 968                         &_lock);
 969         clk_register_clkdev(clk, NULL, "acp_clk");
 970 
 971         clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
 972                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
 973                         &_lock);
 974         clk_register_clkdev(clk, NULL, "e2800000.gpio");
 975 
 976         clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
 977                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
 978                         0, &_lock);
 979         clk_register_clkdev(clk, NULL, "video_dec");
 980 
 981         clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
 982                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
 983                         0, &_lock);
 984         clk_register_clkdev(clk, NULL, "video_enc");
 985 
 986         clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
 987                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
 988                         &_lock);
 989         clk_register_clkdev(clk, NULL, "spear_vip");
 990 
 991         clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
 992                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
 993                         &_lock);
 994         clk_register_clkdev(clk, NULL, "d0200000.cam0");
 995 
 996         clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
 997                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
 998                         &_lock);
 999         clk_register_clkdev(clk, NULL, "d0300000.cam1");
1000 
1001         clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
1002                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
1003                         &_lock);
1004         clk_register_clkdev(clk, NULL, "d0400000.cam2");
1005 
1006         clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
1007                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
1008                         &_lock);
1009         clk_register_clkdev(clk, NULL, "d0500000.cam3");
1010 
1011         clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
1012                         SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
1013                         &_lock);
1014         clk_register_clkdev(clk, NULL, "e0180000.pwm");
1015 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/clk/spear/spear1340_clock.c

DEFINITIONS
