This source file includes following definitions.
- clk_mt6797_venc_probe
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7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
9
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12
13 #include <dt-bindings/clock/mt6797-clk.h>
14
15 static const struct mtk_gate_regs venc_cg_regs = {
16 .set_ofs = 0x0004,
17 .clr_ofs = 0x0008,
18 .sta_ofs = 0x0000,
19 };
20
21 #define GATE_VENC(_id, _name, _parent, _shift) { \
22 .id = _id, \
23 .name = _name, \
24 .parent_name = _parent, \
25 .regs = &venc_cg_regs, \
26 .shift = _shift, \
27 .ops = &mtk_clk_gate_ops_setclr_inv, \
28 }
29
30 static const struct mtk_gate venc_clks[] = {
31 GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0),
32 GATE_VENC(CLK_VENC_1, "venc_1", "venc_sel", 4),
33 GATE_VENC(CLK_VENC_2, "venc_2", "venc_sel", 8),
34 GATE_VENC(CLK_VENC_3, "venc_3", "venc_sel", 12),
35 };
36
37 static const struct of_device_id of_match_clk_mt6797_venc[] = {
38 { .compatible = "mediatek,mt6797-vencsys", },
39 {}
40 };
41
42 static int clk_mt6797_venc_probe(struct platform_device *pdev)
43 {
44 struct clk_onecell_data *clk_data;
45 int r;
46 struct device_node *node = pdev->dev.of_node;
47
48 clk_data = mtk_alloc_clk_data(CLK_VENC_NR);
49
50 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
51 clk_data);
52
53 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
54 if (r)
55 dev_err(&pdev->dev,
56 "could not register clock provider: %s: %d\n",
57 pdev->name, r);
58
59 return r;
60 }
61
62 static struct platform_driver clk_mt6797_venc_drv = {
63 .probe = clk_mt6797_venc_probe,
64 .driver = {
65 .name = "clk-mt6797-venc",
66 .of_match_table = of_match_clk_mt6797_venc,
67 },
68 };
69
70 builtin_platform_driver(clk_mt6797_venc_drv);