This source file includes following definitions.
- clk_mt6797_img_probe
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6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
8 #include <dt-bindings/clock/mt6797-clk.h>
9
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
12
13 static const struct mtk_gate_regs img_cg_regs = {
14 .set_ofs = 0x0004,
15 .clr_ofs = 0x0008,
16 .sta_ofs = 0x0000,
17 };
18
19 #define GATE_IMG(_id, _name, _parent, _shift) { \
20 .id = _id, \
21 .name = _name, \
22 .parent_name = _parent, \
23 .regs = &img_cg_regs, \
24 .shift = _shift, \
25 .ops = &mtk_clk_gate_ops_setclr, \
26 }
27
28 static const struct mtk_gate img_clks[] = {
29 GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
30 GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
31 GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
32 GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
33 };
34
35 static const struct of_device_id of_match_clk_mt6797_img[] = {
36 { .compatible = "mediatek,mt6797-imgsys", },
37 {}
38 };
39
40 static int clk_mt6797_img_probe(struct platform_device *pdev)
41 {
42 struct clk_onecell_data *clk_data;
43 int r;
44 struct device_node *node = pdev->dev.of_node;
45
46 clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
47
48 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
49 clk_data);
50
51 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
52 if (r)
53 dev_err(&pdev->dev,
54 "could not register clock provider: %s: %d\n",
55 pdev->name, r);
56
57 return r;
58 }
59
60 static struct platform_driver clk_mt6797_img_drv = {
61 .probe = clk_mt6797_img_probe,
62 .driver = {
63 .name = "clk-mt6797-img",
64 .of_match_table = of_match_clk_mt6797_img,
65 },
66 };
67
68 builtin_platform_driver(clk_mt6797_img_drv);