root/drivers/clk/meson/gxbb.c

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   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016 AmLogic, Inc.
   4  * Michael Turquette <mturquette@baylibre.com>
   5  */
   6 
   7 #include <linux/clk-provider.h>
   8 #include <linux/init.h>
   9 #include <linux/of_device.h>
  10 #include <linux/platform_device.h>
  11 
  12 #include "gxbb.h"
  13 #include "clk-regmap.h"
  14 #include "clk-pll.h"
  15 #include "clk-mpll.h"
  16 #include "meson-eeclk.h"
  17 #include "vid-pll-div.h"
  18 
  19 static DEFINE_SPINLOCK(meson_clk_lock);
  20 
  21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
  22         PLL_PARAMS(32, 1),
  23         PLL_PARAMS(33, 1),
  24         PLL_PARAMS(34, 1),
  25         PLL_PARAMS(35, 1),
  26         PLL_PARAMS(36, 1),
  27         PLL_PARAMS(37, 1),
  28         PLL_PARAMS(38, 1),
  29         PLL_PARAMS(39, 1),
  30         PLL_PARAMS(40, 1),
  31         PLL_PARAMS(41, 1),
  32         PLL_PARAMS(42, 1),
  33         PLL_PARAMS(43, 1),
  34         PLL_PARAMS(44, 1),
  35         PLL_PARAMS(45, 1),
  36         PLL_PARAMS(46, 1),
  37         PLL_PARAMS(47, 1),
  38         PLL_PARAMS(48, 1),
  39         PLL_PARAMS(49, 1),
  40         PLL_PARAMS(50, 1),
  41         PLL_PARAMS(51, 1),
  42         PLL_PARAMS(52, 1),
  43         PLL_PARAMS(53, 1),
  44         PLL_PARAMS(54, 1),
  45         PLL_PARAMS(55, 1),
  46         PLL_PARAMS(56, 1),
  47         PLL_PARAMS(57, 1),
  48         PLL_PARAMS(58, 1),
  49         PLL_PARAMS(59, 1),
  50         PLL_PARAMS(60, 1),
  51         PLL_PARAMS(61, 1),
  52         PLL_PARAMS(62, 1),
  53         { /* sentinel */ },
  54 };
  55 
  56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
  57         PLL_PARAMS(42, 1),
  58         PLL_PARAMS(43, 1),
  59         PLL_PARAMS(44, 1),
  60         PLL_PARAMS(45, 1),
  61         PLL_PARAMS(46, 1),
  62         PLL_PARAMS(47, 1),
  63         PLL_PARAMS(48, 1),
  64         PLL_PARAMS(49, 1),
  65         PLL_PARAMS(50, 1),
  66         PLL_PARAMS(51, 1),
  67         PLL_PARAMS(52, 1),
  68         PLL_PARAMS(53, 1),
  69         PLL_PARAMS(54, 1),
  70         PLL_PARAMS(55, 1),
  71         PLL_PARAMS(56, 1),
  72         PLL_PARAMS(57, 1),
  73         PLL_PARAMS(58, 1),
  74         PLL_PARAMS(59, 1),
  75         PLL_PARAMS(60, 1),
  76         PLL_PARAMS(61, 1),
  77         PLL_PARAMS(62, 1),
  78         PLL_PARAMS(63, 1),
  79         PLL_PARAMS(64, 1),
  80         PLL_PARAMS(65, 1),
  81         PLL_PARAMS(66, 1),
  82         { /* sentinel */ },
  83 };
  84 
  85 static struct clk_regmap gxbb_fixed_pll_dco = {
  86         .data = &(struct meson_clk_pll_data){
  87                 .en = {
  88                         .reg_off = HHI_MPLL_CNTL,
  89                         .shift   = 30,
  90                         .width   = 1,
  91                 },
  92                 .m = {
  93                         .reg_off = HHI_MPLL_CNTL,
  94                         .shift   = 0,
  95                         .width   = 9,
  96                 },
  97                 .n = {
  98                         .reg_off = HHI_MPLL_CNTL,
  99                         .shift   = 9,
 100                         .width   = 5,
 101                 },
 102                 .frac = {
 103                         .reg_off = HHI_MPLL_CNTL2,
 104                         .shift   = 0,
 105                         .width   = 12,
 106                 },
 107                 .l = {
 108                         .reg_off = HHI_MPLL_CNTL,
 109                         .shift   = 31,
 110                         .width   = 1,
 111                 },
 112                 .rst = {
 113                         .reg_off = HHI_MPLL_CNTL,
 114                         .shift   = 29,
 115                         .width   = 1,
 116                 },
 117         },
 118         .hw.init = &(struct clk_init_data){
 119                 .name = "fixed_pll_dco",
 120                 .ops = &meson_clk_pll_ro_ops,
 121                 .parent_data = &(const struct clk_parent_data) {
 122                         .fw_name = "xtal",
 123                 },
 124                 .num_parents = 1,
 125         },
 126 };
 127 
 128 static struct clk_regmap gxbb_fixed_pll = {
 129         .data = &(struct clk_regmap_div_data){
 130                 .offset = HHI_MPLL_CNTL,
 131                 .shift = 16,
 132                 .width = 2,
 133                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 134         },
 135         .hw.init = &(struct clk_init_data){
 136                 .name = "fixed_pll",
 137                 .ops = &clk_regmap_divider_ro_ops,
 138                 .parent_hws = (const struct clk_hw *[]) {
 139                         &gxbb_fixed_pll_dco.hw
 140                 },
 141                 .num_parents = 1,
 142                 /*
 143                  * This clock won't ever change at runtime so
 144                  * CLK_SET_RATE_PARENT is not required
 145                  */
 146         },
 147 };
 148 
 149 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
 150         .mult = 2,
 151         .div = 1,
 152         .hw.init = &(struct clk_init_data){
 153                 .name = "hdmi_pll_pre_mult",
 154                 .ops = &clk_fixed_factor_ops,
 155                 .parent_data = &(const struct clk_parent_data) {
 156                         .fw_name = "xtal",
 157                 },
 158                 .num_parents = 1,
 159         },
 160 };
 161 
 162 static struct clk_regmap gxbb_hdmi_pll_dco = {
 163         .data = &(struct meson_clk_pll_data){
 164                 .en = {
 165                         .reg_off = HHI_HDMI_PLL_CNTL,
 166                         .shift   = 30,
 167                         .width   = 1,
 168                 },
 169                 .m = {
 170                         .reg_off = HHI_HDMI_PLL_CNTL,
 171                         .shift   = 0,
 172                         .width   = 9,
 173                 },
 174                 .n = {
 175                         .reg_off = HHI_HDMI_PLL_CNTL,
 176                         .shift   = 9,
 177                         .width   = 5,
 178                 },
 179                 .frac = {
 180                         .reg_off = HHI_HDMI_PLL_CNTL2,
 181                         .shift   = 0,
 182                         .width   = 12,
 183                 },
 184                 .l = {
 185                         .reg_off = HHI_HDMI_PLL_CNTL,
 186                         .shift   = 31,
 187                         .width   = 1,
 188                 },
 189                 .rst = {
 190                         .reg_off = HHI_HDMI_PLL_CNTL,
 191                         .shift   = 28,
 192                         .width   = 1,
 193                 },
 194         },
 195         .hw.init = &(struct clk_init_data){
 196                 .name = "hdmi_pll_dco",
 197                 .ops = &meson_clk_pll_ro_ops,
 198                 .parent_hws = (const struct clk_hw *[]) {
 199                         &gxbb_hdmi_pll_pre_mult.hw
 200                 },
 201                 .num_parents = 1,
 202                 /*
 203                  * Display directly handle hdmi pll registers ATM, we need
 204                  * NOCACHE to keep our view of the clock as accurate as possible
 205                  */
 206                 .flags = CLK_GET_RATE_NOCACHE,
 207         },
 208 };
 209 
 210 static struct clk_regmap gxl_hdmi_pll_dco = {
 211         .data = &(struct meson_clk_pll_data){
 212                 .en = {
 213                         .reg_off = HHI_HDMI_PLL_CNTL,
 214                         .shift   = 30,
 215                         .width   = 1,
 216                 },
 217                 .m = {
 218                         .reg_off = HHI_HDMI_PLL_CNTL,
 219                         .shift   = 0,
 220                         .width   = 9,
 221                 },
 222                 .n = {
 223                         .reg_off = HHI_HDMI_PLL_CNTL,
 224                         .shift   = 9,
 225                         .width   = 5,
 226                 },
 227                 /*
 228                  * On gxl, there is a register shift due to
 229                  * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
 230                  * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
 231                  * instead which is defined at the same offset.
 232                  */
 233                 .frac = {
 234                         .reg_off = HHI_HDMI_PLL_CNTL2,
 235                         .shift   = 0,
 236                         .width   = 10,
 237                 },
 238                 .l = {
 239                         .reg_off = HHI_HDMI_PLL_CNTL,
 240                         .shift   = 31,
 241                         .width   = 1,
 242                 },
 243                 .rst = {
 244                         .reg_off = HHI_HDMI_PLL_CNTL,
 245                         .shift   = 28,
 246                         .width   = 1,
 247                 },
 248         },
 249         .hw.init = &(struct clk_init_data){
 250                 .name = "hdmi_pll_dco",
 251                 .ops = &meson_clk_pll_ro_ops,
 252                 .parent_data = &(const struct clk_parent_data) {
 253                         .fw_name = "xtal",
 254                 },
 255                 .num_parents = 1,
 256                 /*
 257                  * Display directly handle hdmi pll registers ATM, we need
 258                  * NOCACHE to keep our view of the clock as accurate as possible
 259                  */
 260                 .flags = CLK_GET_RATE_NOCACHE,
 261         },
 262 };
 263 
 264 static struct clk_regmap gxbb_hdmi_pll_od = {
 265         .data = &(struct clk_regmap_div_data){
 266                 .offset = HHI_HDMI_PLL_CNTL2,
 267                 .shift = 16,
 268                 .width = 2,
 269                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 270         },
 271         .hw.init = &(struct clk_init_data){
 272                 .name = "hdmi_pll_od",
 273                 .ops = &clk_regmap_divider_ro_ops,
 274                 .parent_hws = (const struct clk_hw *[]) {
 275                         &gxbb_hdmi_pll_dco.hw
 276                 },
 277                 .num_parents = 1,
 278                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 279         },
 280 };
 281 
 282 static struct clk_regmap gxbb_hdmi_pll_od2 = {
 283         .data = &(struct clk_regmap_div_data){
 284                 .offset = HHI_HDMI_PLL_CNTL2,
 285                 .shift = 22,
 286                 .width = 2,
 287                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 288         },
 289         .hw.init = &(struct clk_init_data){
 290                 .name = "hdmi_pll_od2",
 291                 .ops = &clk_regmap_divider_ro_ops,
 292                 .parent_hws = (const struct clk_hw *[]) {
 293                         &gxbb_hdmi_pll_od.hw
 294                 },
 295                 .num_parents = 1,
 296                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 297         },
 298 };
 299 
 300 static struct clk_regmap gxbb_hdmi_pll = {
 301         .data = &(struct clk_regmap_div_data){
 302                 .offset = HHI_HDMI_PLL_CNTL2,
 303                 .shift = 18,
 304                 .width = 2,
 305                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 306         },
 307         .hw.init = &(struct clk_init_data){
 308                 .name = "hdmi_pll",
 309                 .ops = &clk_regmap_divider_ro_ops,
 310                 .parent_hws = (const struct clk_hw *[]) {
 311                         &gxbb_hdmi_pll_od2.hw
 312                 },
 313                 .num_parents = 1,
 314                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 315         },
 316 };
 317 
 318 static struct clk_regmap gxl_hdmi_pll_od = {
 319         .data = &(struct clk_regmap_div_data){
 320                 .offset = HHI_HDMI_PLL_CNTL + 8,
 321                 .shift = 21,
 322                 .width = 2,
 323                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 324         },
 325         .hw.init = &(struct clk_init_data){
 326                 .name = "hdmi_pll_od",
 327                 .ops = &clk_regmap_divider_ro_ops,
 328                 .parent_hws = (const struct clk_hw *[]) {
 329                         &gxl_hdmi_pll_dco.hw
 330                 },
 331                 .num_parents = 1,
 332                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 333         },
 334 };
 335 
 336 static struct clk_regmap gxl_hdmi_pll_od2 = {
 337         .data = &(struct clk_regmap_div_data){
 338                 .offset = HHI_HDMI_PLL_CNTL + 8,
 339                 .shift = 23,
 340                 .width = 2,
 341                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 342         },
 343         .hw.init = &(struct clk_init_data){
 344                 .name = "hdmi_pll_od2",
 345                 .ops = &clk_regmap_divider_ro_ops,
 346                 .parent_hws = (const struct clk_hw *[]) {
 347                         &gxl_hdmi_pll_od.hw
 348                 },
 349                 .num_parents = 1,
 350                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 351         },
 352 };
 353 
 354 static struct clk_regmap gxl_hdmi_pll = {
 355         .data = &(struct clk_regmap_div_data){
 356                 .offset = HHI_HDMI_PLL_CNTL + 8,
 357                 .shift = 19,
 358                 .width = 2,
 359                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 360         },
 361         .hw.init = &(struct clk_init_data){
 362                 .name = "hdmi_pll",
 363                 .ops = &clk_regmap_divider_ro_ops,
 364                 .parent_hws = (const struct clk_hw *[]) {
 365                         &gxl_hdmi_pll_od2.hw
 366                 },
 367                 .num_parents = 1,
 368                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 369         },
 370 };
 371 
 372 static struct clk_regmap gxbb_sys_pll_dco = {
 373         .data = &(struct meson_clk_pll_data){
 374                 .en = {
 375                         .reg_off = HHI_SYS_PLL_CNTL,
 376                         .shift   = 30,
 377                         .width   = 1,
 378                 },
 379                 .m = {
 380                         .reg_off = HHI_SYS_PLL_CNTL,
 381                         .shift   = 0,
 382                         .width   = 9,
 383                 },
 384                 .n = {
 385                         .reg_off = HHI_SYS_PLL_CNTL,
 386                         .shift   = 9,
 387                         .width   = 5,
 388                 },
 389                 .l = {
 390                         .reg_off = HHI_SYS_PLL_CNTL,
 391                         .shift   = 31,
 392                         .width   = 1,
 393                 },
 394                 .rst = {
 395                         .reg_off = HHI_SYS_PLL_CNTL,
 396                         .shift   = 29,
 397                         .width   = 1,
 398                 },
 399         },
 400         .hw.init = &(struct clk_init_data){
 401                 .name = "sys_pll_dco",
 402                 .ops = &meson_clk_pll_ro_ops,
 403                 .parent_data = &(const struct clk_parent_data) {
 404                         .fw_name = "xtal",
 405                 },
 406                 .num_parents = 1,
 407         },
 408 };
 409 
 410 static struct clk_regmap gxbb_sys_pll = {
 411         .data = &(struct clk_regmap_div_data){
 412                 .offset = HHI_SYS_PLL_CNTL,
 413                 .shift = 10,
 414                 .width = 2,
 415                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 416         },
 417         .hw.init = &(struct clk_init_data){
 418                 .name = "sys_pll",
 419                 .ops = &clk_regmap_divider_ro_ops,
 420                 .parent_hws = (const struct clk_hw *[]) {
 421                         &gxbb_sys_pll_dco.hw
 422                 },
 423                 .num_parents = 1,
 424                 .flags = CLK_SET_RATE_PARENT,
 425         },
 426 };
 427 
 428 static const struct reg_sequence gxbb_gp0_init_regs[] = {
 429         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
 430         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
 431         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
 432 };
 433 
 434 static struct clk_regmap gxbb_gp0_pll_dco = {
 435         .data = &(struct meson_clk_pll_data){
 436                 .en = {
 437                         .reg_off = HHI_GP0_PLL_CNTL,
 438                         .shift   = 30,
 439                         .width   = 1,
 440                 },
 441                 .m = {
 442                         .reg_off = HHI_GP0_PLL_CNTL,
 443                         .shift   = 0,
 444                         .width   = 9,
 445                 },
 446                 .n = {
 447                         .reg_off = HHI_GP0_PLL_CNTL,
 448                         .shift   = 9,
 449                         .width   = 5,
 450                 },
 451                 .l = {
 452                         .reg_off = HHI_GP0_PLL_CNTL,
 453                         .shift   = 31,
 454                         .width   = 1,
 455                 },
 456                 .rst = {
 457                         .reg_off = HHI_GP0_PLL_CNTL,
 458                         .shift   = 29,
 459                         .width   = 1,
 460                 },
 461                 .table = gxbb_gp0_pll_params_table,
 462                 .init_regs = gxbb_gp0_init_regs,
 463                 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
 464         },
 465         .hw.init = &(struct clk_init_data){
 466                 .name = "gp0_pll_dco",
 467                 .ops = &meson_clk_pll_ops,
 468                 .parent_data = &(const struct clk_parent_data) {
 469                         .fw_name = "xtal",
 470                 },
 471                 .num_parents = 1,
 472         },
 473 };
 474 
 475 static const struct reg_sequence gxl_gp0_init_regs[] = {
 476         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 477         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 478         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 479         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 480         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 481 };
 482 
 483 static struct clk_regmap gxl_gp0_pll_dco = {
 484         .data = &(struct meson_clk_pll_data){
 485                 .en = {
 486                         .reg_off = HHI_GP0_PLL_CNTL,
 487                         .shift   = 30,
 488                         .width   = 1,
 489                 },
 490                 .m = {
 491                         .reg_off = HHI_GP0_PLL_CNTL,
 492                         .shift   = 0,
 493                         .width   = 9,
 494                 },
 495                 .n = {
 496                         .reg_off = HHI_GP0_PLL_CNTL,
 497                         .shift   = 9,
 498                         .width   = 5,
 499                 },
 500                 .frac = {
 501                         .reg_off = HHI_GP0_PLL_CNTL1,
 502                         .shift   = 0,
 503                         .width   = 10,
 504                 },
 505                 .l = {
 506                         .reg_off = HHI_GP0_PLL_CNTL,
 507                         .shift   = 31,
 508                         .width   = 1,
 509                 },
 510                 .rst = {
 511                         .reg_off = HHI_GP0_PLL_CNTL,
 512                         .shift   = 29,
 513                         .width   = 1,
 514                 },
 515                 .table = gxl_gp0_pll_params_table,
 516                 .init_regs = gxl_gp0_init_regs,
 517                 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
 518         },
 519         .hw.init = &(struct clk_init_data){
 520                 .name = "gp0_pll_dco",
 521                 .ops = &meson_clk_pll_ops,
 522                 .parent_data = &(const struct clk_parent_data) {
 523                         .fw_name = "xtal",
 524                 },
 525                 .num_parents = 1,
 526         },
 527 };
 528 
 529 static struct clk_regmap gxbb_gp0_pll = {
 530         .data = &(struct clk_regmap_div_data){
 531                 .offset = HHI_GP0_PLL_CNTL,
 532                 .shift = 16,
 533                 .width = 2,
 534                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 535         },
 536         .hw.init = &(struct clk_init_data){
 537                 .name = "gp0_pll",
 538                 .ops = &clk_regmap_divider_ops,
 539                 .parent_data = &(const struct clk_parent_data) {
 540                         /*
 541                          * Note:
 542                          * GXL and GXBB have different gp0_pll_dco (with
 543                          * different struct clk_hw). We fallback to the global
 544                          * naming string mechanism so gp0_pll picks up the
 545                          * appropriate one.
 546                          */
 547                         .name = "gp0_pll_dco",
 548                         .index = -1,
 549                 },
 550                 .num_parents = 1,
 551                 .flags = CLK_SET_RATE_PARENT,
 552         },
 553 };
 554 
 555 static struct clk_fixed_factor gxbb_fclk_div2_div = {
 556         .mult = 1,
 557         .div = 2,
 558         .hw.init = &(struct clk_init_data){
 559                 .name = "fclk_div2_div",
 560                 .ops = &clk_fixed_factor_ops,
 561                 .parent_hws = (const struct clk_hw *[]) {
 562                         &gxbb_fixed_pll.hw
 563                 },
 564                 .num_parents = 1,
 565         },
 566 };
 567 
 568 static struct clk_regmap gxbb_fclk_div2 = {
 569         .data = &(struct clk_regmap_gate_data){
 570                 .offset = HHI_MPLL_CNTL6,
 571                 .bit_idx = 27,
 572         },
 573         .hw.init = &(struct clk_init_data){
 574                 .name = "fclk_div2",
 575                 .ops = &clk_regmap_gate_ops,
 576                 .parent_hws = (const struct clk_hw *[]) {
 577                         &gxbb_fclk_div2_div.hw
 578                 },
 579                 .num_parents = 1,
 580                 .flags = CLK_IS_CRITICAL,
 581         },
 582 };
 583 
 584 static struct clk_fixed_factor gxbb_fclk_div3_div = {
 585         .mult = 1,
 586         .div = 3,
 587         .hw.init = &(struct clk_init_data){
 588                 .name = "fclk_div3_div",
 589                 .ops = &clk_fixed_factor_ops,
 590                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 591                 .num_parents = 1,
 592         },
 593 };
 594 
 595 static struct clk_regmap gxbb_fclk_div3 = {
 596         .data = &(struct clk_regmap_gate_data){
 597                 .offset = HHI_MPLL_CNTL6,
 598                 .bit_idx = 28,
 599         },
 600         .hw.init = &(struct clk_init_data){
 601                 .name = "fclk_div3",
 602                 .ops = &clk_regmap_gate_ops,
 603                 .parent_hws = (const struct clk_hw *[]) {
 604                         &gxbb_fclk_div3_div.hw
 605                 },
 606                 .num_parents = 1,
 607                 /*
 608                  * FIXME:
 609                  * This clock, as fdiv2, is used by the SCPI FW and is required
 610                  * by the platform to operate correctly.
 611                  * Until the following condition are met, we need this clock to
 612                  * be marked as critical:
 613                  * a) The SCPI generic driver claims and enable all the clocks
 614                  *    it needs
 615                  * b) CCF has a clock hand-off mechanism to make the sure the
 616                  *    clock stays on until the proper driver comes along
 617                  */
 618                 .flags = CLK_IS_CRITICAL,
 619         },
 620 };
 621 
 622 static struct clk_fixed_factor gxbb_fclk_div4_div = {
 623         .mult = 1,
 624         .div = 4,
 625         .hw.init = &(struct clk_init_data){
 626                 .name = "fclk_div4_div",
 627                 .ops = &clk_fixed_factor_ops,
 628                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 629                 .num_parents = 1,
 630         },
 631 };
 632 
 633 static struct clk_regmap gxbb_fclk_div4 = {
 634         .data = &(struct clk_regmap_gate_data){
 635                 .offset = HHI_MPLL_CNTL6,
 636                 .bit_idx = 29,
 637         },
 638         .hw.init = &(struct clk_init_data){
 639                 .name = "fclk_div4",
 640                 .ops = &clk_regmap_gate_ops,
 641                 .parent_hws = (const struct clk_hw *[]) {
 642                         &gxbb_fclk_div4_div.hw
 643                 },
 644                 .num_parents = 1,
 645         },
 646 };
 647 
 648 static struct clk_fixed_factor gxbb_fclk_div5_div = {
 649         .mult = 1,
 650         .div = 5,
 651         .hw.init = &(struct clk_init_data){
 652                 .name = "fclk_div5_div",
 653                 .ops = &clk_fixed_factor_ops,
 654                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 655                 .num_parents = 1,
 656         },
 657 };
 658 
 659 static struct clk_regmap gxbb_fclk_div5 = {
 660         .data = &(struct clk_regmap_gate_data){
 661                 .offset = HHI_MPLL_CNTL6,
 662                 .bit_idx = 30,
 663         },
 664         .hw.init = &(struct clk_init_data){
 665                 .name = "fclk_div5",
 666                 .ops = &clk_regmap_gate_ops,
 667                 .parent_hws = (const struct clk_hw *[]) {
 668                         &gxbb_fclk_div5_div.hw
 669                 },
 670                 .num_parents = 1,
 671         },
 672 };
 673 
 674 static struct clk_fixed_factor gxbb_fclk_div7_div = {
 675         .mult = 1,
 676         .div = 7,
 677         .hw.init = &(struct clk_init_data){
 678                 .name = "fclk_div7_div",
 679                 .ops = &clk_fixed_factor_ops,
 680                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 681                 .num_parents = 1,
 682         },
 683 };
 684 
 685 static struct clk_regmap gxbb_fclk_div7 = {
 686         .data = &(struct clk_regmap_gate_data){
 687                 .offset = HHI_MPLL_CNTL6,
 688                 .bit_idx = 31,
 689         },
 690         .hw.init = &(struct clk_init_data){
 691                 .name = "fclk_div7",
 692                 .ops = &clk_regmap_gate_ops,
 693                 .parent_hws = (const struct clk_hw *[]) {
 694                         &gxbb_fclk_div7_div.hw
 695                 },
 696                 .num_parents = 1,
 697         },
 698 };
 699 
 700 static struct clk_regmap gxbb_mpll_prediv = {
 701         .data = &(struct clk_regmap_div_data){
 702                 .offset = HHI_MPLL_CNTL5,
 703                 .shift = 12,
 704                 .width = 1,
 705         },
 706         .hw.init = &(struct clk_init_data){
 707                 .name = "mpll_prediv",
 708                 .ops = &clk_regmap_divider_ro_ops,
 709                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 710                 .num_parents = 1,
 711         },
 712 };
 713 
 714 static struct clk_regmap gxbb_mpll0_div = {
 715         .data = &(struct meson_clk_mpll_data){
 716                 .sdm = {
 717                         .reg_off = HHI_MPLL_CNTL7,
 718                         .shift   = 0,
 719                         .width   = 14,
 720                 },
 721                 .sdm_en = {
 722                         .reg_off = HHI_MPLL_CNTL7,
 723                         .shift   = 15,
 724                         .width   = 1,
 725                 },
 726                 .n2 = {
 727                         .reg_off = HHI_MPLL_CNTL7,
 728                         .shift   = 16,
 729                         .width   = 9,
 730                 },
 731                 .lock = &meson_clk_lock,
 732         },
 733         .hw.init = &(struct clk_init_data){
 734                 .name = "mpll0_div",
 735                 .ops = &meson_clk_mpll_ops,
 736                 .parent_hws = (const struct clk_hw *[]) {
 737                         &gxbb_mpll_prediv.hw
 738                 },
 739                 .num_parents = 1,
 740         },
 741 };
 742 
 743 static struct clk_regmap gxbb_mpll0 = {
 744         .data = &(struct clk_regmap_gate_data){
 745                 .offset = HHI_MPLL_CNTL7,
 746                 .bit_idx = 14,
 747         },
 748         .hw.init = &(struct clk_init_data){
 749                 .name = "mpll0",
 750                 .ops = &clk_regmap_gate_ops,
 751                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
 752                 .num_parents = 1,
 753                 .flags = CLK_SET_RATE_PARENT,
 754         },
 755 };
 756 
 757 static struct clk_regmap gxbb_mpll1_div = {
 758         .data = &(struct meson_clk_mpll_data){
 759                 .sdm = {
 760                         .reg_off = HHI_MPLL_CNTL8,
 761                         .shift   = 0,
 762                         .width   = 14,
 763                 },
 764                 .sdm_en = {
 765                         .reg_off = HHI_MPLL_CNTL8,
 766                         .shift   = 15,
 767                         .width   = 1,
 768                 },
 769                 .n2 = {
 770                         .reg_off = HHI_MPLL_CNTL8,
 771                         .shift   = 16,
 772                         .width   = 9,
 773                 },
 774                 .lock = &meson_clk_lock,
 775         },
 776         .hw.init = &(struct clk_init_data){
 777                 .name = "mpll1_div",
 778                 .ops = &meson_clk_mpll_ops,
 779                 .parent_hws = (const struct clk_hw *[]) {
 780                         &gxbb_mpll_prediv.hw
 781                 },
 782                 .num_parents = 1,
 783         },
 784 };
 785 
 786 static struct clk_regmap gxbb_mpll1 = {
 787         .data = &(struct clk_regmap_gate_data){
 788                 .offset = HHI_MPLL_CNTL8,
 789                 .bit_idx = 14,
 790         },
 791         .hw.init = &(struct clk_init_data){
 792                 .name = "mpll1",
 793                 .ops = &clk_regmap_gate_ops,
 794                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
 795                 .num_parents = 1,
 796                 .flags = CLK_SET_RATE_PARENT,
 797         },
 798 };
 799 
 800 static struct clk_regmap gxbb_mpll2_div = {
 801         .data = &(struct meson_clk_mpll_data){
 802                 .sdm = {
 803                         .reg_off = HHI_MPLL_CNTL9,
 804                         .shift   = 0,
 805                         .width   = 14,
 806                 },
 807                 .sdm_en = {
 808                         .reg_off = HHI_MPLL_CNTL9,
 809                         .shift   = 15,
 810                         .width   = 1,
 811                 },
 812                 .n2 = {
 813                         .reg_off = HHI_MPLL_CNTL9,
 814                         .shift   = 16,
 815                         .width   = 9,
 816                 },
 817                 .lock = &meson_clk_lock,
 818         },
 819         .hw.init = &(struct clk_init_data){
 820                 .name = "mpll2_div",
 821                 .ops = &meson_clk_mpll_ops,
 822                 .parent_hws = (const struct clk_hw *[]) {
 823                         &gxbb_mpll_prediv.hw
 824                 },
 825                 .num_parents = 1,
 826         },
 827 };
 828 
 829 static struct clk_regmap gxbb_mpll2 = {
 830         .data = &(struct clk_regmap_gate_data){
 831                 .offset = HHI_MPLL_CNTL9,
 832                 .bit_idx = 14,
 833         },
 834         .hw.init = &(struct clk_init_data){
 835                 .name = "mpll2",
 836                 .ops = &clk_regmap_gate_ops,
 837                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
 838                 .num_parents = 1,
 839                 .flags = CLK_SET_RATE_PARENT,
 840         },
 841 };
 842 
 843 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 844 static const struct clk_parent_data clk81_parent_data[] = {
 845         { .fw_name = "xtal", },
 846         { .hw = &gxbb_fclk_div7.hw },
 847         { .hw = &gxbb_mpll1.hw },
 848         { .hw = &gxbb_mpll2.hw },
 849         { .hw = &gxbb_fclk_div4.hw },
 850         { .hw = &gxbb_fclk_div3.hw },
 851         { .hw = &gxbb_fclk_div5.hw },
 852 };
 853 
 854 static struct clk_regmap gxbb_mpeg_clk_sel = {
 855         .data = &(struct clk_regmap_mux_data){
 856                 .offset = HHI_MPEG_CLK_CNTL,
 857                 .mask = 0x7,
 858                 .shift = 12,
 859                 .table = mux_table_clk81,
 860         },
 861         .hw.init = &(struct clk_init_data){
 862                 .name = "mpeg_clk_sel",
 863                 .ops = &clk_regmap_mux_ro_ops,
 864                 /*
 865                  * bits 14:12 selects from 8 possible parents:
 866                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 867                  * fclk_div4, fclk_div3, fclk_div5
 868                  */
 869                 .parent_data = clk81_parent_data,
 870                 .num_parents = ARRAY_SIZE(clk81_parent_data),
 871         },
 872 };
 873 
 874 static struct clk_regmap gxbb_mpeg_clk_div = {
 875         .data = &(struct clk_regmap_div_data){
 876                 .offset = HHI_MPEG_CLK_CNTL,
 877                 .shift = 0,
 878                 .width = 7,
 879         },
 880         .hw.init = &(struct clk_init_data){
 881                 .name = "mpeg_clk_div",
 882                 .ops = &clk_regmap_divider_ro_ops,
 883                 .parent_hws = (const struct clk_hw *[]) {
 884                         &gxbb_mpeg_clk_sel.hw
 885                 },
 886                 .num_parents = 1,
 887         },
 888 };
 889 
 890 /* the mother of dragons gates */
 891 static struct clk_regmap gxbb_clk81 = {
 892         .data = &(struct clk_regmap_gate_data){
 893                 .offset = HHI_MPEG_CLK_CNTL,
 894                 .bit_idx = 7,
 895         },
 896         .hw.init = &(struct clk_init_data){
 897                 .name = "clk81",
 898                 .ops = &clk_regmap_gate_ops,
 899                 .parent_hws = (const struct clk_hw *[]) {
 900                         &gxbb_mpeg_clk_div.hw
 901                 },
 902                 .num_parents = 1,
 903                 .flags = CLK_IS_CRITICAL,
 904         },
 905 };
 906 
 907 static struct clk_regmap gxbb_sar_adc_clk_sel = {
 908         .data = &(struct clk_regmap_mux_data){
 909                 .offset = HHI_SAR_CLK_CNTL,
 910                 .mask = 0x3,
 911                 .shift = 9,
 912         },
 913         .hw.init = &(struct clk_init_data){
 914                 .name = "sar_adc_clk_sel",
 915                 .ops = &clk_regmap_mux_ops,
 916                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
 917                 .parent_data = (const struct clk_parent_data []) {
 918                         { .fw_name = "xtal", },
 919                         { .hw = &gxbb_clk81.hw },
 920                 },
 921                 .num_parents = 2,
 922         },
 923 };
 924 
 925 static struct clk_regmap gxbb_sar_adc_clk_div = {
 926         .data = &(struct clk_regmap_div_data){
 927                 .offset = HHI_SAR_CLK_CNTL,
 928                 .shift = 0,
 929                 .width = 8,
 930         },
 931         .hw.init = &(struct clk_init_data){
 932                 .name = "sar_adc_clk_div",
 933                 .ops = &clk_regmap_divider_ops,
 934                 .parent_hws = (const struct clk_hw *[]) {
 935                         &gxbb_sar_adc_clk_sel.hw
 936                 },
 937                 .num_parents = 1,
 938                 .flags = CLK_SET_RATE_PARENT,
 939         },
 940 };
 941 
 942 static struct clk_regmap gxbb_sar_adc_clk = {
 943         .data = &(struct clk_regmap_gate_data){
 944                 .offset = HHI_SAR_CLK_CNTL,
 945                 .bit_idx = 8,
 946         },
 947         .hw.init = &(struct clk_init_data){
 948                 .name = "sar_adc_clk",
 949                 .ops = &clk_regmap_gate_ops,
 950                 .parent_hws = (const struct clk_hw *[]) {
 951                         &gxbb_sar_adc_clk_div.hw
 952                 },
 953                 .num_parents = 1,
 954                 .flags = CLK_SET_RATE_PARENT,
 955         },
 956 };
 957 
 958 /*
 959  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
 960  * muxed by a glitch-free switch.
 961  */
 962 
 963 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
 964         { .fw_name = "xtal", },
 965         { .hw = &gxbb_gp0_pll.hw },
 966         { .hw = &gxbb_mpll2.hw },
 967         { .hw = &gxbb_mpll1.hw },
 968         { .hw = &gxbb_fclk_div7.hw },
 969         { .hw = &gxbb_fclk_div4.hw },
 970         { .hw = &gxbb_fclk_div3.hw },
 971         { .hw = &gxbb_fclk_div5.hw },
 972 };
 973 
 974 static struct clk_regmap gxbb_mali_0_sel = {
 975         .data = &(struct clk_regmap_mux_data){
 976                 .offset = HHI_MALI_CLK_CNTL,
 977                 .mask = 0x7,
 978                 .shift = 9,
 979         },
 980         .hw.init = &(struct clk_init_data){
 981                 .name = "mali_0_sel",
 982                 .ops = &clk_regmap_mux_ops,
 983                 /*
 984                  * bits 10:9 selects from 8 possible parents:
 985                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
 986                  * fclk_div4, fclk_div3, fclk_div5
 987                  */
 988                 .parent_data = gxbb_mali_0_1_parent_data,
 989                 .num_parents = 8,
 990                 .flags = CLK_SET_RATE_NO_REPARENT,
 991         },
 992 };
 993 
 994 static struct clk_regmap gxbb_mali_0_div = {
 995         .data = &(struct clk_regmap_div_data){
 996                 .offset = HHI_MALI_CLK_CNTL,
 997                 .shift = 0,
 998                 .width = 7,
 999         },
1000         .hw.init = &(struct clk_init_data){
1001                 .name = "mali_0_div",
1002                 .ops = &clk_regmap_divider_ops,
1003                 .parent_hws = (const struct clk_hw *[]) {
1004                         &gxbb_mali_0_sel.hw
1005                 },
1006                 .num_parents = 1,
1007                 .flags = CLK_SET_RATE_NO_REPARENT,
1008         },
1009 };
1010 
1011 static struct clk_regmap gxbb_mali_0 = {
1012         .data = &(struct clk_regmap_gate_data){
1013                 .offset = HHI_MALI_CLK_CNTL,
1014                 .bit_idx = 8,
1015         },
1016         .hw.init = &(struct clk_init_data){
1017                 .name = "mali_0",
1018                 .ops = &clk_regmap_gate_ops,
1019                 .parent_hws = (const struct clk_hw *[]) {
1020                         &gxbb_mali_0_div.hw
1021                 },
1022                 .num_parents = 1,
1023                 .flags = CLK_SET_RATE_PARENT,
1024         },
1025 };
1026 
1027 static struct clk_regmap gxbb_mali_1_sel = {
1028         .data = &(struct clk_regmap_mux_data){
1029                 .offset = HHI_MALI_CLK_CNTL,
1030                 .mask = 0x7,
1031                 .shift = 25,
1032         },
1033         .hw.init = &(struct clk_init_data){
1034                 .name = "mali_1_sel",
1035                 .ops = &clk_regmap_mux_ops,
1036                 /*
1037                  * bits 10:9 selects from 8 possible parents:
1038                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
1039                  * fclk_div4, fclk_div3, fclk_div5
1040                  */
1041                 .parent_data = gxbb_mali_0_1_parent_data,
1042                 .num_parents = 8,
1043                 .flags = CLK_SET_RATE_NO_REPARENT,
1044         },
1045 };
1046 
1047 static struct clk_regmap gxbb_mali_1_div = {
1048         .data = &(struct clk_regmap_div_data){
1049                 .offset = HHI_MALI_CLK_CNTL,
1050                 .shift = 16,
1051                 .width = 7,
1052         },
1053         .hw.init = &(struct clk_init_data){
1054                 .name = "mali_1_div",
1055                 .ops = &clk_regmap_divider_ops,
1056                 .parent_hws = (const struct clk_hw *[]) {
1057                         &gxbb_mali_1_sel.hw
1058                 },
1059                 .num_parents = 1,
1060                 .flags = CLK_SET_RATE_NO_REPARENT,
1061         },
1062 };
1063 
1064 static struct clk_regmap gxbb_mali_1 = {
1065         .data = &(struct clk_regmap_gate_data){
1066                 .offset = HHI_MALI_CLK_CNTL,
1067                 .bit_idx = 24,
1068         },
1069         .hw.init = &(struct clk_init_data){
1070                 .name = "mali_1",
1071                 .ops = &clk_regmap_gate_ops,
1072                 .parent_hws = (const struct clk_hw *[]) {
1073                         &gxbb_mali_1_div.hw
1074                 },
1075                 .num_parents = 1,
1076                 .flags = CLK_SET_RATE_PARENT,
1077         },
1078 };
1079 
1080 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1081         &gxbb_mali_0.hw,
1082         &gxbb_mali_1.hw,
1083 };
1084 
1085 static struct clk_regmap gxbb_mali = {
1086         .data = &(struct clk_regmap_mux_data){
1087                 .offset = HHI_MALI_CLK_CNTL,
1088                 .mask = 1,
1089                 .shift = 31,
1090         },
1091         .hw.init = &(struct clk_init_data){
1092                 .name = "mali",
1093                 .ops = &clk_regmap_mux_ops,
1094                 .parent_hws = gxbb_mali_parent_hws,
1095                 .num_parents = 2,
1096                 .flags = CLK_SET_RATE_NO_REPARENT,
1097         },
1098 };
1099 
1100 static struct clk_regmap gxbb_cts_amclk_sel = {
1101         .data = &(struct clk_regmap_mux_data){
1102                 .offset = HHI_AUD_CLK_CNTL,
1103                 .mask = 0x3,
1104                 .shift = 9,
1105                 .table = (u32[]){ 1, 2, 3 },
1106                 .flags = CLK_MUX_ROUND_CLOSEST,
1107         },
1108         .hw.init = &(struct clk_init_data){
1109                 .name = "cts_amclk_sel",
1110                 .ops = &clk_regmap_mux_ops,
1111                 .parent_hws = (const struct clk_hw *[]) {
1112                         &gxbb_mpll0.hw,
1113                         &gxbb_mpll1.hw,
1114                         &gxbb_mpll2.hw,
1115                 },
1116                 .num_parents = 3,
1117         },
1118 };
1119 
1120 static struct clk_regmap gxbb_cts_amclk_div = {
1121         .data = &(struct clk_regmap_div_data) {
1122                 .offset = HHI_AUD_CLK_CNTL,
1123                 .shift = 0,
1124                 .width = 8,
1125                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1126         },
1127         .hw.init = &(struct clk_init_data){
1128                 .name = "cts_amclk_div",
1129                 .ops = &clk_regmap_divider_ops,
1130                 .parent_hws = (const struct clk_hw *[]) {
1131                         &gxbb_cts_amclk_sel.hw
1132                 },
1133                 .num_parents = 1,
1134                 .flags = CLK_SET_RATE_PARENT,
1135         },
1136 };
1137 
1138 static struct clk_regmap gxbb_cts_amclk = {
1139         .data = &(struct clk_regmap_gate_data){
1140                 .offset = HHI_AUD_CLK_CNTL,
1141                 .bit_idx = 8,
1142         },
1143         .hw.init = &(struct clk_init_data){
1144                 .name = "cts_amclk",
1145                 .ops = &clk_regmap_gate_ops,
1146                 .parent_hws = (const struct clk_hw *[]) {
1147                         &gxbb_cts_amclk_div.hw
1148                 },
1149                 .num_parents = 1,
1150                 .flags = CLK_SET_RATE_PARENT,
1151         },
1152 };
1153 
1154 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1155         .data = &(struct clk_regmap_mux_data){
1156                 .offset = HHI_AUD_CLK_CNTL2,
1157                 .mask = 0x3,
1158                 .shift = 25,
1159                 .table = (u32[]){ 1, 2, 3 },
1160                 .flags = CLK_MUX_ROUND_CLOSEST,
1161         },
1162         .hw.init = &(struct clk_init_data) {
1163                 .name = "cts_mclk_i958_sel",
1164                 .ops = &clk_regmap_mux_ops,
1165                 .parent_hws = (const struct clk_hw *[]) {
1166                         &gxbb_mpll0.hw,
1167                         &gxbb_mpll1.hw,
1168                         &gxbb_mpll2.hw,
1169                 },
1170                 .num_parents = 3,
1171         },
1172 };
1173 
1174 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1175         .data = &(struct clk_regmap_div_data){
1176                 .offset = HHI_AUD_CLK_CNTL2,
1177                 .shift = 16,
1178                 .width = 8,
1179                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1180         },
1181         .hw.init = &(struct clk_init_data) {
1182                 .name = "cts_mclk_i958_div",
1183                 .ops = &clk_regmap_divider_ops,
1184                 .parent_hws = (const struct clk_hw *[]) {
1185                         &gxbb_cts_mclk_i958_sel.hw
1186                 },
1187                 .num_parents = 1,
1188                 .flags = CLK_SET_RATE_PARENT,
1189         },
1190 };
1191 
1192 static struct clk_regmap gxbb_cts_mclk_i958 = {
1193         .data = &(struct clk_regmap_gate_data){
1194                 .offset = HHI_AUD_CLK_CNTL2,
1195                 .bit_idx = 24,
1196         },
1197         .hw.init = &(struct clk_init_data){
1198                 .name = "cts_mclk_i958",
1199                 .ops = &clk_regmap_gate_ops,
1200                 .parent_hws = (const struct clk_hw *[]) {
1201                         &gxbb_cts_mclk_i958_div.hw
1202                 },
1203                 .num_parents = 1,
1204                 .flags = CLK_SET_RATE_PARENT,
1205         },
1206 };
1207 
1208 static struct clk_regmap gxbb_cts_i958 = {
1209         .data = &(struct clk_regmap_mux_data){
1210                 .offset = HHI_AUD_CLK_CNTL2,
1211                 .mask = 0x1,
1212                 .shift = 27,
1213                 },
1214         .hw.init = &(struct clk_init_data){
1215                 .name = "cts_i958",
1216                 .ops = &clk_regmap_mux_ops,
1217                 .parent_hws = (const struct clk_hw *[]) {
1218                         &gxbb_cts_amclk.hw,
1219                         &gxbb_cts_mclk_i958.hw
1220                 },
1221                 .num_parents = 2,
1222                 /*
1223                  *The parent is specific to origin of the audio data. Let the
1224                  * consumer choose the appropriate parent
1225                  */
1226                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1227         },
1228 };
1229 
1230 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1231         { .fw_name = "xtal", },
1232         /*
1233          * FIXME: This clock is provided by the ao clock controller but the
1234          * clock is not yet part of the binding of this controller, so string
1235          * name must be use to set this parent.
1236          */
1237         { .name = "cts_slow_oscin", .index = -1 },
1238         { .hw = &gxbb_fclk_div3.hw },
1239         { .hw = &gxbb_fclk_div5.hw },
1240 };
1241 
1242 static struct clk_regmap gxbb_32k_clk_sel = {
1243         .data = &(struct clk_regmap_mux_data){
1244                 .offset = HHI_32K_CLK_CNTL,
1245                 .mask = 0x3,
1246                 .shift = 16,
1247                 },
1248         .hw.init = &(struct clk_init_data){
1249                 .name = "32k_clk_sel",
1250                 .ops = &clk_regmap_mux_ops,
1251                 .parent_data = gxbb_32k_clk_parent_data,
1252                 .num_parents = 4,
1253                 .flags = CLK_SET_RATE_PARENT,
1254         },
1255 };
1256 
1257 static struct clk_regmap gxbb_32k_clk_div = {
1258         .data = &(struct clk_regmap_div_data){
1259                 .offset = HHI_32K_CLK_CNTL,
1260                 .shift = 0,
1261                 .width = 14,
1262         },
1263         .hw.init = &(struct clk_init_data){
1264                 .name = "32k_clk_div",
1265                 .ops = &clk_regmap_divider_ops,
1266                 .parent_hws = (const struct clk_hw *[]) {
1267                         &gxbb_32k_clk_sel.hw
1268                 },
1269                 .num_parents = 1,
1270                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1271         },
1272 };
1273 
1274 static struct clk_regmap gxbb_32k_clk = {
1275         .data = &(struct clk_regmap_gate_data){
1276                 .offset = HHI_32K_CLK_CNTL,
1277                 .bit_idx = 15,
1278         },
1279         .hw.init = &(struct clk_init_data){
1280                 .name = "32k_clk",
1281                 .ops = &clk_regmap_gate_ops,
1282                 .parent_hws = (const struct clk_hw *[]) {
1283                         &gxbb_32k_clk_div.hw
1284                 },
1285                 .num_parents = 1,
1286                 .flags = CLK_SET_RATE_PARENT,
1287         },
1288 };
1289 
1290 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1291         { .fw_name = "xtal", },
1292         { .hw = &gxbb_fclk_div2.hw },
1293         { .hw = &gxbb_fclk_div3.hw },
1294         { .hw = &gxbb_fclk_div5.hw },
1295         { .hw = &gxbb_fclk_div7.hw },
1296         /*
1297          * Following these parent clocks, we should also have had mpll2, mpll3
1298          * and gp0_pll but these clocks are too precious to be used here. All
1299          * the necessary rates for MMC and NAND operation can be acheived using
1300          * xtal or fclk_div clocks
1301          */
1302 };
1303 
1304 /* SDIO clock */
1305 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1306         .data = &(struct clk_regmap_mux_data){
1307                 .offset = HHI_SD_EMMC_CLK_CNTL,
1308                 .mask = 0x7,
1309                 .shift = 9,
1310         },
1311         .hw.init = &(struct clk_init_data) {
1312                 .name = "sd_emmc_a_clk0_sel",
1313                 .ops = &clk_regmap_mux_ops,
1314                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1315                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1316                 .flags = CLK_SET_RATE_PARENT,
1317         },
1318 };
1319 
1320 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1321         .data = &(struct clk_regmap_div_data){
1322                 .offset = HHI_SD_EMMC_CLK_CNTL,
1323                 .shift = 0,
1324                 .width = 7,
1325                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1326         },
1327         .hw.init = &(struct clk_init_data) {
1328                 .name = "sd_emmc_a_clk0_div",
1329                 .ops = &clk_regmap_divider_ops,
1330                 .parent_hws = (const struct clk_hw *[]) {
1331                         &gxbb_sd_emmc_a_clk0_sel.hw
1332                 },
1333                 .num_parents = 1,
1334                 .flags = CLK_SET_RATE_PARENT,
1335         },
1336 };
1337 
1338 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1339         .data = &(struct clk_regmap_gate_data){
1340                 .offset = HHI_SD_EMMC_CLK_CNTL,
1341                 .bit_idx = 7,
1342         },
1343         .hw.init = &(struct clk_init_data){
1344                 .name = "sd_emmc_a_clk0",
1345                 .ops = &clk_regmap_gate_ops,
1346                 .parent_hws = (const struct clk_hw *[]) {
1347                         &gxbb_sd_emmc_a_clk0_div.hw
1348                 },
1349                 .num_parents = 1,
1350                 .flags = CLK_SET_RATE_PARENT,
1351         },
1352 };
1353 
1354 /* SDcard clock */
1355 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1356         .data = &(struct clk_regmap_mux_data){
1357                 .offset = HHI_SD_EMMC_CLK_CNTL,
1358                 .mask = 0x7,
1359                 .shift = 25,
1360         },
1361         .hw.init = &(struct clk_init_data) {
1362                 .name = "sd_emmc_b_clk0_sel",
1363                 .ops = &clk_regmap_mux_ops,
1364                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1365                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1366                 .flags = CLK_SET_RATE_PARENT,
1367         },
1368 };
1369 
1370 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1371         .data = &(struct clk_regmap_div_data){
1372                 .offset = HHI_SD_EMMC_CLK_CNTL,
1373                 .shift = 16,
1374                 .width = 7,
1375                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1376         },
1377         .hw.init = &(struct clk_init_data) {
1378                 .name = "sd_emmc_b_clk0_div",
1379                 .ops = &clk_regmap_divider_ops,
1380                 .parent_hws = (const struct clk_hw *[]) {
1381                         &gxbb_sd_emmc_b_clk0_sel.hw
1382                 },
1383                 .num_parents = 1,
1384                 .flags = CLK_SET_RATE_PARENT,
1385         },
1386 };
1387 
1388 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1389         .data = &(struct clk_regmap_gate_data){
1390                 .offset = HHI_SD_EMMC_CLK_CNTL,
1391                 .bit_idx = 23,
1392         },
1393         .hw.init = &(struct clk_init_data){
1394                 .name = "sd_emmc_b_clk0",
1395                 .ops = &clk_regmap_gate_ops,
1396                 .parent_hws = (const struct clk_hw *[]) {
1397                         &gxbb_sd_emmc_b_clk0_div.hw
1398                 },
1399                 .num_parents = 1,
1400                 .flags = CLK_SET_RATE_PARENT,
1401         },
1402 };
1403 
1404 /* EMMC/NAND clock */
1405 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1406         .data = &(struct clk_regmap_mux_data){
1407                 .offset = HHI_NAND_CLK_CNTL,
1408                 .mask = 0x7,
1409                 .shift = 9,
1410         },
1411         .hw.init = &(struct clk_init_data) {
1412                 .name = "sd_emmc_c_clk0_sel",
1413                 .ops = &clk_regmap_mux_ops,
1414                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1415                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1416                 .flags = CLK_SET_RATE_PARENT,
1417         },
1418 };
1419 
1420 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1421         .data = &(struct clk_regmap_div_data){
1422                 .offset = HHI_NAND_CLK_CNTL,
1423                 .shift = 0,
1424                 .width = 7,
1425                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1426         },
1427         .hw.init = &(struct clk_init_data) {
1428                 .name = "sd_emmc_c_clk0_div",
1429                 .ops = &clk_regmap_divider_ops,
1430                 .parent_hws = (const struct clk_hw *[]) {
1431                         &gxbb_sd_emmc_c_clk0_sel.hw
1432                 },
1433                 .num_parents = 1,
1434                 .flags = CLK_SET_RATE_PARENT,
1435         },
1436 };
1437 
1438 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1439         .data = &(struct clk_regmap_gate_data){
1440                 .offset = HHI_NAND_CLK_CNTL,
1441                 .bit_idx = 7,
1442         },
1443         .hw.init = &(struct clk_init_data){
1444                 .name = "sd_emmc_c_clk0",
1445                 .ops = &clk_regmap_gate_ops,
1446                 .parent_hws = (const struct clk_hw *[]) {
1447                         &gxbb_sd_emmc_c_clk0_div.hw
1448                 },
1449                 .num_parents = 1,
1450                 .flags = CLK_SET_RATE_PARENT,
1451         },
1452 };
1453 
1454 /* VPU Clock */
1455 
1456 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1457         &gxbb_fclk_div4.hw,
1458         &gxbb_fclk_div3.hw,
1459         &gxbb_fclk_div5.hw,
1460         &gxbb_fclk_div7.hw,
1461 };
1462 
1463 static struct clk_regmap gxbb_vpu_0_sel = {
1464         .data = &(struct clk_regmap_mux_data){
1465                 .offset = HHI_VPU_CLK_CNTL,
1466                 .mask = 0x3,
1467                 .shift = 9,
1468         },
1469         .hw.init = &(struct clk_init_data){
1470                 .name = "vpu_0_sel",
1471                 .ops = &clk_regmap_mux_ops,
1472                 /*
1473                  * bits 9:10 selects from 4 possible parents:
1474                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1475                  */
1476                 .parent_hws = gxbb_vpu_parent_hws,
1477                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1478                 .flags = CLK_SET_RATE_NO_REPARENT,
1479         },
1480 };
1481 
1482 static struct clk_regmap gxbb_vpu_0_div = {
1483         .data = &(struct clk_regmap_div_data){
1484                 .offset = HHI_VPU_CLK_CNTL,
1485                 .shift = 0,
1486                 .width = 7,
1487         },
1488         .hw.init = &(struct clk_init_data){
1489                 .name = "vpu_0_div",
1490                 .ops = &clk_regmap_divider_ops,
1491                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1492                 .num_parents = 1,
1493                 .flags = CLK_SET_RATE_PARENT,
1494         },
1495 };
1496 
1497 static struct clk_regmap gxbb_vpu_0 = {
1498         .data = &(struct clk_regmap_gate_data){
1499                 .offset = HHI_VPU_CLK_CNTL,
1500                 .bit_idx = 8,
1501         },
1502         .hw.init = &(struct clk_init_data) {
1503                 .name = "vpu_0",
1504                 .ops = &clk_regmap_gate_ops,
1505                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1506                 .num_parents = 1,
1507                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1508         },
1509 };
1510 
1511 static struct clk_regmap gxbb_vpu_1_sel = {
1512         .data = &(struct clk_regmap_mux_data){
1513                 .offset = HHI_VPU_CLK_CNTL,
1514                 .mask = 0x3,
1515                 .shift = 25,
1516         },
1517         .hw.init = &(struct clk_init_data){
1518                 .name = "vpu_1_sel",
1519                 .ops = &clk_regmap_mux_ops,
1520                 /*
1521                  * bits 25:26 selects from 4 possible parents:
1522                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1523                  */
1524                 .parent_hws = gxbb_vpu_parent_hws,
1525                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1526                 .flags = CLK_SET_RATE_NO_REPARENT,
1527         },
1528 };
1529 
1530 static struct clk_regmap gxbb_vpu_1_div = {
1531         .data = &(struct clk_regmap_div_data){
1532                 .offset = HHI_VPU_CLK_CNTL,
1533                 .shift = 16,
1534                 .width = 7,
1535         },
1536         .hw.init = &(struct clk_init_data){
1537                 .name = "vpu_1_div",
1538                 .ops = &clk_regmap_divider_ops,
1539                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1540                 .num_parents = 1,
1541                 .flags = CLK_SET_RATE_PARENT,
1542         },
1543 };
1544 
1545 static struct clk_regmap gxbb_vpu_1 = {
1546         .data = &(struct clk_regmap_gate_data){
1547                 .offset = HHI_VPU_CLK_CNTL,
1548                 .bit_idx = 24,
1549         },
1550         .hw.init = &(struct clk_init_data) {
1551                 .name = "vpu_1",
1552                 .ops = &clk_regmap_gate_ops,
1553                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1554                 .num_parents = 1,
1555                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1556         },
1557 };
1558 
1559 static struct clk_regmap gxbb_vpu = {
1560         .data = &(struct clk_regmap_mux_data){
1561                 .offset = HHI_VPU_CLK_CNTL,
1562                 .mask = 1,
1563                 .shift = 31,
1564         },
1565         .hw.init = &(struct clk_init_data){
1566                 .name = "vpu",
1567                 .ops = &clk_regmap_mux_ops,
1568                 /*
1569                  * bit 31 selects from 2 possible parents:
1570                  * vpu_0 or vpu_1
1571                  */
1572                 .parent_hws = (const struct clk_hw *[]) {
1573                         &gxbb_vpu_0.hw,
1574                         &gxbb_vpu_1.hw
1575                 },
1576                 .num_parents = 2,
1577                 .flags = CLK_SET_RATE_NO_REPARENT,
1578         },
1579 };
1580 
1581 /* VAPB Clock */
1582 
1583 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1584         &gxbb_fclk_div4.hw,
1585         &gxbb_fclk_div3.hw,
1586         &gxbb_fclk_div5.hw,
1587         &gxbb_fclk_div7.hw,
1588 };
1589 
1590 static struct clk_regmap gxbb_vapb_0_sel = {
1591         .data = &(struct clk_regmap_mux_data){
1592                 .offset = HHI_VAPBCLK_CNTL,
1593                 .mask = 0x3,
1594                 .shift = 9,
1595         },
1596         .hw.init = &(struct clk_init_data){
1597                 .name = "vapb_0_sel",
1598                 .ops = &clk_regmap_mux_ops,
1599                 /*
1600                  * bits 9:10 selects from 4 possible parents:
1601                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1602                  */
1603                 .parent_hws = gxbb_vapb_parent_hws,
1604                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1605                 .flags = CLK_SET_RATE_NO_REPARENT,
1606         },
1607 };
1608 
1609 static struct clk_regmap gxbb_vapb_0_div = {
1610         .data = &(struct clk_regmap_div_data){
1611                 .offset = HHI_VAPBCLK_CNTL,
1612                 .shift = 0,
1613                 .width = 7,
1614         },
1615         .hw.init = &(struct clk_init_data){
1616                 .name = "vapb_0_div",
1617                 .ops = &clk_regmap_divider_ops,
1618                 .parent_hws = (const struct clk_hw *[]) {
1619                         &gxbb_vapb_0_sel.hw
1620                 },
1621                 .num_parents = 1,
1622                 .flags = CLK_SET_RATE_PARENT,
1623         },
1624 };
1625 
1626 static struct clk_regmap gxbb_vapb_0 = {
1627         .data = &(struct clk_regmap_gate_data){
1628                 .offset = HHI_VAPBCLK_CNTL,
1629                 .bit_idx = 8,
1630         },
1631         .hw.init = &(struct clk_init_data) {
1632                 .name = "vapb_0",
1633                 .ops = &clk_regmap_gate_ops,
1634                 .parent_hws = (const struct clk_hw *[]) {
1635                         &gxbb_vapb_0_div.hw
1636                 },
1637                 .num_parents = 1,
1638                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1639         },
1640 };
1641 
1642 static struct clk_regmap gxbb_vapb_1_sel = {
1643         .data = &(struct clk_regmap_mux_data){
1644                 .offset = HHI_VAPBCLK_CNTL,
1645                 .mask = 0x3,
1646                 .shift = 25,
1647         },
1648         .hw.init = &(struct clk_init_data){
1649                 .name = "vapb_1_sel",
1650                 .ops = &clk_regmap_mux_ops,
1651                 /*
1652                  * bits 25:26 selects from 4 possible parents:
1653                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1654                  */
1655                 .parent_hws = gxbb_vapb_parent_hws,
1656                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1657                 .flags = CLK_SET_RATE_NO_REPARENT,
1658         },
1659 };
1660 
1661 static struct clk_regmap gxbb_vapb_1_div = {
1662         .data = &(struct clk_regmap_div_data){
1663                 .offset = HHI_VAPBCLK_CNTL,
1664                 .shift = 16,
1665                 .width = 7,
1666         },
1667         .hw.init = &(struct clk_init_data){
1668                 .name = "vapb_1_div",
1669                 .ops = &clk_regmap_divider_ops,
1670                 .parent_hws = (const struct clk_hw *[]) {
1671                         &gxbb_vapb_1_sel.hw
1672                 },
1673                 .num_parents = 1,
1674                 .flags = CLK_SET_RATE_PARENT,
1675         },
1676 };
1677 
1678 static struct clk_regmap gxbb_vapb_1 = {
1679         .data = &(struct clk_regmap_gate_data){
1680                 .offset = HHI_VAPBCLK_CNTL,
1681                 .bit_idx = 24,
1682         },
1683         .hw.init = &(struct clk_init_data) {
1684                 .name = "vapb_1",
1685                 .ops = &clk_regmap_gate_ops,
1686                 .parent_hws = (const struct clk_hw *[]) {
1687                         &gxbb_vapb_1_div.hw
1688                 },
1689                 .num_parents = 1,
1690                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1691         },
1692 };
1693 
1694 static struct clk_regmap gxbb_vapb_sel = {
1695         .data = &(struct clk_regmap_mux_data){
1696                 .offset = HHI_VAPBCLK_CNTL,
1697                 .mask = 1,
1698                 .shift = 31,
1699         },
1700         .hw.init = &(struct clk_init_data){
1701                 .name = "vapb_sel",
1702                 .ops = &clk_regmap_mux_ops,
1703                 /*
1704                  * bit 31 selects from 2 possible parents:
1705                  * vapb_0 or vapb_1
1706                  */
1707                 .parent_hws = (const struct clk_hw *[]) {
1708                         &gxbb_vapb_0.hw,
1709                         &gxbb_vapb_1.hw
1710                 },
1711                 .num_parents = 2,
1712                 .flags = CLK_SET_RATE_NO_REPARENT,
1713         },
1714 };
1715 
1716 static struct clk_regmap gxbb_vapb = {
1717         .data = &(struct clk_regmap_gate_data){
1718                 .offset = HHI_VAPBCLK_CNTL,
1719                 .bit_idx = 30,
1720         },
1721         .hw.init = &(struct clk_init_data) {
1722                 .name = "vapb",
1723                 .ops = &clk_regmap_gate_ops,
1724                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1725                 .num_parents = 1,
1726                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1727         },
1728 };
1729 
1730 /* Video Clocks */
1731 
1732 static struct clk_regmap gxbb_vid_pll_div = {
1733         .data = &(struct meson_vid_pll_div_data){
1734                 .val = {
1735                         .reg_off = HHI_VID_PLL_CLK_DIV,
1736                         .shift   = 0,
1737                         .width   = 15,
1738                 },
1739                 .sel = {
1740                         .reg_off = HHI_VID_PLL_CLK_DIV,
1741                         .shift   = 16,
1742                         .width   = 2,
1743                 },
1744         },
1745         .hw.init = &(struct clk_init_data) {
1746                 .name = "vid_pll_div",
1747                 .ops = &meson_vid_pll_div_ro_ops,
1748                 .parent_data = &(const struct clk_parent_data) {
1749                         /*
1750                          * Note:
1751                          * GXL and GXBB have different hdmi_plls (with
1752                          * different struct clk_hw). We fallback to the global
1753                          * naming string mechanism so vid_pll_div picks up the
1754                          * appropriate one.
1755                          */
1756                         .name = "hdmi_pll",
1757                         .index = -1,
1758                 },
1759                 .num_parents = 1,
1760                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1761         },
1762 };
1763 
1764 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1765         { .hw = &gxbb_vid_pll_div.hw },
1766         /*
1767          * Note:
1768          * GXL and GXBB have different hdmi_plls (with
1769          * different struct clk_hw). We fallback to the global
1770          * naming string mechanism so vid_pll_div picks up the
1771          * appropriate one.
1772          */
1773         { .name = "hdmi_pll", .index = -1 },
1774 };
1775 
1776 static struct clk_regmap gxbb_vid_pll_sel = {
1777         .data = &(struct clk_regmap_mux_data){
1778                 .offset = HHI_VID_PLL_CLK_DIV,
1779                 .mask = 0x1,
1780                 .shift = 18,
1781         },
1782         .hw.init = &(struct clk_init_data){
1783                 .name = "vid_pll_sel",
1784                 .ops = &clk_regmap_mux_ops,
1785                 /*
1786                  * bit 18 selects from 2 possible parents:
1787                  * vid_pll_div or hdmi_pll
1788                  */
1789                 .parent_data = gxbb_vid_pll_parent_data,
1790                 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1791                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1792         },
1793 };
1794 
1795 static struct clk_regmap gxbb_vid_pll = {
1796         .data = &(struct clk_regmap_gate_data){
1797                 .offset = HHI_VID_PLL_CLK_DIV,
1798                 .bit_idx = 19,
1799         },
1800         .hw.init = &(struct clk_init_data) {
1801                 .name = "vid_pll",
1802                 .ops = &clk_regmap_gate_ops,
1803                 .parent_hws = (const struct clk_hw *[]) {
1804                         &gxbb_vid_pll_sel.hw
1805                 },
1806                 .num_parents = 1,
1807                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1808         },
1809 };
1810 
1811 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1812         &gxbb_vid_pll.hw,
1813         &gxbb_fclk_div4.hw,
1814         &gxbb_fclk_div3.hw,
1815         &gxbb_fclk_div5.hw,
1816         &gxbb_vid_pll.hw,
1817         &gxbb_fclk_div7.hw,
1818         &gxbb_mpll1.hw,
1819 };
1820 
1821 static struct clk_regmap gxbb_vclk_sel = {
1822         .data = &(struct clk_regmap_mux_data){
1823                 .offset = HHI_VID_CLK_CNTL,
1824                 .mask = 0x7,
1825                 .shift = 16,
1826         },
1827         .hw.init = &(struct clk_init_data){
1828                 .name = "vclk_sel",
1829                 .ops = &clk_regmap_mux_ops,
1830                 /*
1831                  * bits 16:18 selects from 8 possible parents:
1832                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1833                  * vid_pll, fclk_div7, mp1
1834                  */
1835                 .parent_hws = gxbb_vclk_parent_hws,
1836                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1837                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1838         },
1839 };
1840 
1841 static struct clk_regmap gxbb_vclk2_sel = {
1842         .data = &(struct clk_regmap_mux_data){
1843                 .offset = HHI_VIID_CLK_CNTL,
1844                 .mask = 0x7,
1845                 .shift = 16,
1846         },
1847         .hw.init = &(struct clk_init_data){
1848                 .name = "vclk2_sel",
1849                 .ops = &clk_regmap_mux_ops,
1850                 /*
1851                  * bits 16:18 selects from 8 possible parents:
1852                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1853                  * vid_pll, fclk_div7, mp1
1854                  */
1855                 .parent_hws = gxbb_vclk_parent_hws,
1856                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1857                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1858         },
1859 };
1860 
1861 static struct clk_regmap gxbb_vclk_input = {
1862         .data = &(struct clk_regmap_gate_data){
1863                 .offset = HHI_VID_CLK_DIV,
1864                 .bit_idx = 16,
1865         },
1866         .hw.init = &(struct clk_init_data) {
1867                 .name = "vclk_input",
1868                 .ops = &clk_regmap_gate_ops,
1869                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1870                 .num_parents = 1,
1871                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1872         },
1873 };
1874 
1875 static struct clk_regmap gxbb_vclk2_input = {
1876         .data = &(struct clk_regmap_gate_data){
1877                 .offset = HHI_VIID_CLK_DIV,
1878                 .bit_idx = 16,
1879         },
1880         .hw.init = &(struct clk_init_data) {
1881                 .name = "vclk2_input",
1882                 .ops = &clk_regmap_gate_ops,
1883                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1884                 .num_parents = 1,
1885                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1886         },
1887 };
1888 
1889 static struct clk_regmap gxbb_vclk_div = {
1890         .data = &(struct clk_regmap_div_data){
1891                 .offset = HHI_VID_CLK_DIV,
1892                 .shift = 0,
1893                 .width = 8,
1894         },
1895         .hw.init = &(struct clk_init_data){
1896                 .name = "vclk_div",
1897                 .ops = &clk_regmap_divider_ops,
1898                 .parent_hws = (const struct clk_hw *[]) {
1899                         &gxbb_vclk_input.hw
1900                 },
1901                 .num_parents = 1,
1902                 .flags = CLK_GET_RATE_NOCACHE,
1903         },
1904 };
1905 
1906 static struct clk_regmap gxbb_vclk2_div = {
1907         .data = &(struct clk_regmap_div_data){
1908                 .offset = HHI_VIID_CLK_DIV,
1909                 .shift = 0,
1910                 .width = 8,
1911         },
1912         .hw.init = &(struct clk_init_data){
1913                 .name = "vclk2_div",
1914                 .ops = &clk_regmap_divider_ops,
1915                 .parent_hws = (const struct clk_hw *[]) {
1916                         &gxbb_vclk2_input.hw
1917                 },
1918                 .num_parents = 1,
1919                 .flags = CLK_GET_RATE_NOCACHE,
1920         },
1921 };
1922 
1923 static struct clk_regmap gxbb_vclk = {
1924         .data = &(struct clk_regmap_gate_data){
1925                 .offset = HHI_VID_CLK_CNTL,
1926                 .bit_idx = 19,
1927         },
1928         .hw.init = &(struct clk_init_data) {
1929                 .name = "vclk",
1930                 .ops = &clk_regmap_gate_ops,
1931                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1932                 .num_parents = 1,
1933                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1934         },
1935 };
1936 
1937 static struct clk_regmap gxbb_vclk2 = {
1938         .data = &(struct clk_regmap_gate_data){
1939                 .offset = HHI_VIID_CLK_CNTL,
1940                 .bit_idx = 19,
1941         },
1942         .hw.init = &(struct clk_init_data) {
1943                 .name = "vclk2",
1944                 .ops = &clk_regmap_gate_ops,
1945                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1946                 .num_parents = 1,
1947                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1948         },
1949 };
1950 
1951 static struct clk_regmap gxbb_vclk_div1 = {
1952         .data = &(struct clk_regmap_gate_data){
1953                 .offset = HHI_VID_CLK_CNTL,
1954                 .bit_idx = 0,
1955         },
1956         .hw.init = &(struct clk_init_data) {
1957                 .name = "vclk_div1",
1958                 .ops = &clk_regmap_gate_ops,
1959                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1960                 .num_parents = 1,
1961                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1962         },
1963 };
1964 
1965 static struct clk_regmap gxbb_vclk_div2_en = {
1966         .data = &(struct clk_regmap_gate_data){
1967                 .offset = HHI_VID_CLK_CNTL,
1968                 .bit_idx = 1,
1969         },
1970         .hw.init = &(struct clk_init_data) {
1971                 .name = "vclk_div2_en",
1972                 .ops = &clk_regmap_gate_ops,
1973                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1974                 .num_parents = 1,
1975                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1976         },
1977 };
1978 
1979 static struct clk_regmap gxbb_vclk_div4_en = {
1980         .data = &(struct clk_regmap_gate_data){
1981                 .offset = HHI_VID_CLK_CNTL,
1982                 .bit_idx = 2,
1983         },
1984         .hw.init = &(struct clk_init_data) {
1985                 .name = "vclk_div4_en",
1986                 .ops = &clk_regmap_gate_ops,
1987                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1988                 .num_parents = 1,
1989                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1990         },
1991 };
1992 
1993 static struct clk_regmap gxbb_vclk_div6_en = {
1994         .data = &(struct clk_regmap_gate_data){
1995                 .offset = HHI_VID_CLK_CNTL,
1996                 .bit_idx = 3,
1997         },
1998         .hw.init = &(struct clk_init_data) {
1999                 .name = "vclk_div6_en",
2000                 .ops = &clk_regmap_gate_ops,
2001                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2002                 .num_parents = 1,
2003                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2004         },
2005 };
2006 
2007 static struct clk_regmap gxbb_vclk_div12_en = {
2008         .data = &(struct clk_regmap_gate_data){
2009                 .offset = HHI_VID_CLK_CNTL,
2010                 .bit_idx = 4,
2011         },
2012         .hw.init = &(struct clk_init_data) {
2013                 .name = "vclk_div12_en",
2014                 .ops = &clk_regmap_gate_ops,
2015                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2016                 .num_parents = 1,
2017                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2018         },
2019 };
2020 
2021 static struct clk_regmap gxbb_vclk2_div1 = {
2022         .data = &(struct clk_regmap_gate_data){
2023                 .offset = HHI_VIID_CLK_CNTL,
2024                 .bit_idx = 0,
2025         },
2026         .hw.init = &(struct clk_init_data) {
2027                 .name = "vclk2_div1",
2028                 .ops = &clk_regmap_gate_ops,
2029                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2030                 .num_parents = 1,
2031                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2032         },
2033 };
2034 
2035 static struct clk_regmap gxbb_vclk2_div2_en = {
2036         .data = &(struct clk_regmap_gate_data){
2037                 .offset = HHI_VIID_CLK_CNTL,
2038                 .bit_idx = 1,
2039         },
2040         .hw.init = &(struct clk_init_data) {
2041                 .name = "vclk2_div2_en",
2042                 .ops = &clk_regmap_gate_ops,
2043                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2044                 .num_parents = 1,
2045                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2046         },
2047 };
2048 
2049 static struct clk_regmap gxbb_vclk2_div4_en = {
2050         .data = &(struct clk_regmap_gate_data){
2051                 .offset = HHI_VIID_CLK_CNTL,
2052                 .bit_idx = 2,
2053         },
2054         .hw.init = &(struct clk_init_data) {
2055                 .name = "vclk2_div4_en",
2056                 .ops = &clk_regmap_gate_ops,
2057                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2058                 .num_parents = 1,
2059                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2060         },
2061 };
2062 
2063 static struct clk_regmap gxbb_vclk2_div6_en = {
2064         .data = &(struct clk_regmap_gate_data){
2065                 .offset = HHI_VIID_CLK_CNTL,
2066                 .bit_idx = 3,
2067         },
2068         .hw.init = &(struct clk_init_data) {
2069                 .name = "vclk2_div6_en",
2070                 .ops = &clk_regmap_gate_ops,
2071                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2072                 .num_parents = 1,
2073                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2074         },
2075 };
2076 
2077 static struct clk_regmap gxbb_vclk2_div12_en = {
2078         .data = &(struct clk_regmap_gate_data){
2079                 .offset = HHI_VIID_CLK_CNTL,
2080                 .bit_idx = 4,
2081         },
2082         .hw.init = &(struct clk_init_data) {
2083                 .name = "vclk2_div12_en",
2084                 .ops = &clk_regmap_gate_ops,
2085                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2086                 .num_parents = 1,
2087                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2088         },
2089 };
2090 
2091 static struct clk_fixed_factor gxbb_vclk_div2 = {
2092         .mult = 1,
2093         .div = 2,
2094         .hw.init = &(struct clk_init_data){
2095                 .name = "vclk_div2",
2096                 .ops = &clk_fixed_factor_ops,
2097                 .parent_hws = (const struct clk_hw *[]) {
2098                         &gxbb_vclk_div2_en.hw
2099                 },
2100                 .num_parents = 1,
2101         },
2102 };
2103 
2104 static struct clk_fixed_factor gxbb_vclk_div4 = {
2105         .mult = 1,
2106         .div = 4,
2107         .hw.init = &(struct clk_init_data){
2108                 .name = "vclk_div4",
2109                 .ops = &clk_fixed_factor_ops,
2110                 .parent_hws = (const struct clk_hw *[]) {
2111                         &gxbb_vclk_div4_en.hw
2112                 },
2113                 .num_parents = 1,
2114         },
2115 };
2116 
2117 static struct clk_fixed_factor gxbb_vclk_div6 = {
2118         .mult = 1,
2119         .div = 6,
2120         .hw.init = &(struct clk_init_data){
2121                 .name = "vclk_div6",
2122                 .ops = &clk_fixed_factor_ops,
2123                 .parent_hws = (const struct clk_hw *[]) {
2124                         &gxbb_vclk_div6_en.hw
2125                 },
2126                 .num_parents = 1,
2127         },
2128 };
2129 
2130 static struct clk_fixed_factor gxbb_vclk_div12 = {
2131         .mult = 1,
2132         .div = 12,
2133         .hw.init = &(struct clk_init_data){
2134                 .name = "vclk_div12",
2135                 .ops = &clk_fixed_factor_ops,
2136                 .parent_hws = (const struct clk_hw *[]) {
2137                         &gxbb_vclk_div12_en.hw
2138                 },
2139                 .num_parents = 1,
2140         },
2141 };
2142 
2143 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2144         .mult = 1,
2145         .div = 2,
2146         .hw.init = &(struct clk_init_data){
2147                 .name = "vclk2_div2",
2148                 .ops = &clk_fixed_factor_ops,
2149                 .parent_hws = (const struct clk_hw *[]) {
2150                         &gxbb_vclk2_div2_en.hw
2151                 },
2152                 .num_parents = 1,
2153         },
2154 };
2155 
2156 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2157         .mult = 1,
2158         .div = 4,
2159         .hw.init = &(struct clk_init_data){
2160                 .name = "vclk2_div4",
2161                 .ops = &clk_fixed_factor_ops,
2162                 .parent_hws = (const struct clk_hw *[]) {
2163                         &gxbb_vclk2_div4_en.hw
2164                 },
2165                 .num_parents = 1,
2166         },
2167 };
2168 
2169 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2170         .mult = 1,
2171         .div = 6,
2172         .hw.init = &(struct clk_init_data){
2173                 .name = "vclk2_div6",
2174                 .ops = &clk_fixed_factor_ops,
2175                 .parent_hws = (const struct clk_hw *[]) {
2176                         &gxbb_vclk2_div6_en.hw
2177                 },
2178                 .num_parents = 1,
2179         },
2180 };
2181 
2182 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2183         .mult = 1,
2184         .div = 12,
2185         .hw.init = &(struct clk_init_data){
2186                 .name = "vclk2_div12",
2187                 .ops = &clk_fixed_factor_ops,
2188                 .parent_hws = (const struct clk_hw *[]) {
2189                         &gxbb_vclk2_div12_en.hw
2190                 },
2191                 .num_parents = 1,
2192         },
2193 };
2194 
2195 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2196 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2197         &gxbb_vclk_div1.hw,
2198         &gxbb_vclk_div2.hw,
2199         &gxbb_vclk_div4.hw,
2200         &gxbb_vclk_div6.hw,
2201         &gxbb_vclk_div12.hw,
2202         &gxbb_vclk2_div1.hw,
2203         &gxbb_vclk2_div2.hw,
2204         &gxbb_vclk2_div4.hw,
2205         &gxbb_vclk2_div6.hw,
2206         &gxbb_vclk2_div12.hw,
2207 };
2208 
2209 static struct clk_regmap gxbb_cts_enci_sel = {
2210         .data = &(struct clk_regmap_mux_data){
2211                 .offset = HHI_VID_CLK_DIV,
2212                 .mask = 0xf,
2213                 .shift = 28,
2214                 .table = mux_table_cts_sel,
2215         },
2216         .hw.init = &(struct clk_init_data){
2217                 .name = "cts_enci_sel",
2218                 .ops = &clk_regmap_mux_ops,
2219                 .parent_hws = gxbb_cts_parent_hws,
2220                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2221                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2222         },
2223 };
2224 
2225 static struct clk_regmap gxbb_cts_encp_sel = {
2226         .data = &(struct clk_regmap_mux_data){
2227                 .offset = HHI_VID_CLK_DIV,
2228                 .mask = 0xf,
2229                 .shift = 20,
2230                 .table = mux_table_cts_sel,
2231         },
2232         .hw.init = &(struct clk_init_data){
2233                 .name = "cts_encp_sel",
2234                 .ops = &clk_regmap_mux_ops,
2235                 .parent_hws = gxbb_cts_parent_hws,
2236                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2237                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2238         },
2239 };
2240 
2241 static struct clk_regmap gxbb_cts_vdac_sel = {
2242         .data = &(struct clk_regmap_mux_data){
2243                 .offset = HHI_VIID_CLK_DIV,
2244                 .mask = 0xf,
2245                 .shift = 28,
2246                 .table = mux_table_cts_sel,
2247         },
2248         .hw.init = &(struct clk_init_data){
2249                 .name = "cts_vdac_sel",
2250                 .ops = &clk_regmap_mux_ops,
2251                 .parent_hws = gxbb_cts_parent_hws,
2252                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2253                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2254         },
2255 };
2256 
2257 /* TOFIX: add support for cts_tcon */
2258 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2259 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2260         &gxbb_vclk_div1.hw,
2261         &gxbb_vclk_div2.hw,
2262         &gxbb_vclk_div4.hw,
2263         &gxbb_vclk_div6.hw,
2264         &gxbb_vclk_div12.hw,
2265         &gxbb_vclk2_div1.hw,
2266         &gxbb_vclk2_div2.hw,
2267         &gxbb_vclk2_div4.hw,
2268         &gxbb_vclk2_div6.hw,
2269         &gxbb_vclk2_div12.hw,
2270 };
2271 
2272 static struct clk_regmap gxbb_hdmi_tx_sel = {
2273         .data = &(struct clk_regmap_mux_data){
2274                 .offset = HHI_HDMI_CLK_CNTL,
2275                 .mask = 0xf,
2276                 .shift = 16,
2277                 .table = mux_table_hdmi_tx_sel,
2278         },
2279         .hw.init = &(struct clk_init_data){
2280                 .name = "hdmi_tx_sel",
2281                 .ops = &clk_regmap_mux_ops,
2282                 /*
2283                  * bits 31:28 selects from 12 possible parents:
2284                  * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2285                  * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2286                  * cts_tcon
2287                  */
2288                 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2289                 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2290                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2291         },
2292 };
2293 
2294 static struct clk_regmap gxbb_cts_enci = {
2295         .data = &(struct clk_regmap_gate_data){
2296                 .offset = HHI_VID_CLK_CNTL2,
2297                 .bit_idx = 0,
2298         },
2299         .hw.init = &(struct clk_init_data) {
2300                 .name = "cts_enci",
2301                 .ops = &clk_regmap_gate_ops,
2302                 .parent_hws = (const struct clk_hw *[]) {
2303                         &gxbb_cts_enci_sel.hw
2304                 },
2305                 .num_parents = 1,
2306                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2307         },
2308 };
2309 
2310 static struct clk_regmap gxbb_cts_encp = {
2311         .data = &(struct clk_regmap_gate_data){
2312                 .offset = HHI_VID_CLK_CNTL2,
2313                 .bit_idx = 2,
2314         },
2315         .hw.init = &(struct clk_init_data) {
2316                 .name = "cts_encp",
2317                 .ops = &clk_regmap_gate_ops,
2318                 .parent_hws = (const struct clk_hw *[]) {
2319                         &gxbb_cts_encp_sel.hw
2320                 },
2321                 .num_parents = 1,
2322                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2323         },
2324 };
2325 
2326 static struct clk_regmap gxbb_cts_vdac = {
2327         .data = &(struct clk_regmap_gate_data){
2328                 .offset = HHI_VID_CLK_CNTL2,
2329                 .bit_idx = 4,
2330         },
2331         .hw.init = &(struct clk_init_data) {
2332                 .name = "cts_vdac",
2333                 .ops = &clk_regmap_gate_ops,
2334                 .parent_hws = (const struct clk_hw *[]) {
2335                         &gxbb_cts_vdac_sel.hw
2336                 },
2337                 .num_parents = 1,
2338                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2339         },
2340 };
2341 
2342 static struct clk_regmap gxbb_hdmi_tx = {
2343         .data = &(struct clk_regmap_gate_data){
2344                 .offset = HHI_VID_CLK_CNTL2,
2345                 .bit_idx = 5,
2346         },
2347         .hw.init = &(struct clk_init_data) {
2348                 .name = "hdmi_tx",
2349                 .ops = &clk_regmap_gate_ops,
2350                 .parent_hws = (const struct clk_hw *[]) {
2351                         &gxbb_hdmi_tx_sel.hw
2352                 },
2353                 .num_parents = 1,
2354                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2355         },
2356 };
2357 
2358 /* HDMI Clocks */
2359 
2360 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2361         { .fw_name = "xtal", },
2362         { .hw = &gxbb_fclk_div4.hw },
2363         { .hw = &gxbb_fclk_div3.hw },
2364         { .hw = &gxbb_fclk_div5.hw },
2365 };
2366 
2367 static struct clk_regmap gxbb_hdmi_sel = {
2368         .data = &(struct clk_regmap_mux_data){
2369                 .offset = HHI_HDMI_CLK_CNTL,
2370                 .mask = 0x3,
2371                 .shift = 9,
2372                 .flags = CLK_MUX_ROUND_CLOSEST,
2373         },
2374         .hw.init = &(struct clk_init_data){
2375                 .name = "hdmi_sel",
2376                 .ops = &clk_regmap_mux_ops,
2377                 .parent_data = gxbb_hdmi_parent_data,
2378                 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2379                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2380         },
2381 };
2382 
2383 static struct clk_regmap gxbb_hdmi_div = {
2384         .data = &(struct clk_regmap_div_data){
2385                 .offset = HHI_HDMI_CLK_CNTL,
2386                 .shift = 0,
2387                 .width = 7,
2388         },
2389         .hw.init = &(struct clk_init_data){
2390                 .name = "hdmi_div",
2391                 .ops = &clk_regmap_divider_ops,
2392                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2393                 .num_parents = 1,
2394                 .flags = CLK_GET_RATE_NOCACHE,
2395         },
2396 };
2397 
2398 static struct clk_regmap gxbb_hdmi = {
2399         .data = &(struct clk_regmap_gate_data){
2400                 .offset = HHI_HDMI_CLK_CNTL,
2401                 .bit_idx = 8,
2402         },
2403         .hw.init = &(struct clk_init_data) {
2404                 .name = "hdmi",
2405                 .ops = &clk_regmap_gate_ops,
2406                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2407                 .num_parents = 1,
2408                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2409         },
2410 };
2411 
2412 /* VDEC clocks */
2413 
2414 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2415         &gxbb_fclk_div4.hw,
2416         &gxbb_fclk_div3.hw,
2417         &gxbb_fclk_div5.hw,
2418         &gxbb_fclk_div7.hw,
2419 };
2420 
2421 static struct clk_regmap gxbb_vdec_1_sel = {
2422         .data = &(struct clk_regmap_mux_data){
2423                 .offset = HHI_VDEC_CLK_CNTL,
2424                 .mask = 0x3,
2425                 .shift = 9,
2426                 .flags = CLK_MUX_ROUND_CLOSEST,
2427         },
2428         .hw.init = &(struct clk_init_data){
2429                 .name = "vdec_1_sel",
2430                 .ops = &clk_regmap_mux_ops,
2431                 .parent_hws = gxbb_vdec_parent_hws,
2432                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2433                 .flags = CLK_SET_RATE_PARENT,
2434         },
2435 };
2436 
2437 static struct clk_regmap gxbb_vdec_1_div = {
2438         .data = &(struct clk_regmap_div_data){
2439                 .offset = HHI_VDEC_CLK_CNTL,
2440                 .shift = 0,
2441                 .width = 7,
2442                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2443         },
2444         .hw.init = &(struct clk_init_data){
2445                 .name = "vdec_1_div",
2446                 .ops = &clk_regmap_divider_ops,
2447                 .parent_hws = (const struct clk_hw *[]) {
2448                         &gxbb_vdec_1_sel.hw
2449                 },
2450                 .num_parents = 1,
2451                 .flags = CLK_SET_RATE_PARENT,
2452         },
2453 };
2454 
2455 static struct clk_regmap gxbb_vdec_1 = {
2456         .data = &(struct clk_regmap_gate_data){
2457                 .offset = HHI_VDEC_CLK_CNTL,
2458                 .bit_idx = 8,
2459         },
2460         .hw.init = &(struct clk_init_data) {
2461                 .name = "vdec_1",
2462                 .ops = &clk_regmap_gate_ops,
2463                 .parent_hws = (const struct clk_hw *[]) {
2464                         &gxbb_vdec_1_div.hw
2465                 },
2466                 .num_parents = 1,
2467                 .flags = CLK_SET_RATE_PARENT,
2468         },
2469 };
2470 
2471 static struct clk_regmap gxbb_vdec_hevc_sel = {
2472         .data = &(struct clk_regmap_mux_data){
2473                 .offset = HHI_VDEC2_CLK_CNTL,
2474                 .mask = 0x3,
2475                 .shift = 25,
2476                 .flags = CLK_MUX_ROUND_CLOSEST,
2477         },
2478         .hw.init = &(struct clk_init_data){
2479                 .name = "vdec_hevc_sel",
2480                 .ops = &clk_regmap_mux_ops,
2481                 .parent_hws = gxbb_vdec_parent_hws,
2482                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2483                 .flags = CLK_SET_RATE_PARENT,
2484         },
2485 };
2486 
2487 static struct clk_regmap gxbb_vdec_hevc_div = {
2488         .data = &(struct clk_regmap_div_data){
2489                 .offset = HHI_VDEC2_CLK_CNTL,
2490                 .shift = 16,
2491                 .width = 7,
2492                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2493         },
2494         .hw.init = &(struct clk_init_data){
2495                 .name = "vdec_hevc_div",
2496                 .ops = &clk_regmap_divider_ops,
2497                 .parent_hws = (const struct clk_hw *[]) {
2498                         &gxbb_vdec_hevc_sel.hw
2499                 },
2500                 .num_parents = 1,
2501                 .flags = CLK_SET_RATE_PARENT,
2502         },
2503 };
2504 
2505 static struct clk_regmap gxbb_vdec_hevc = {
2506         .data = &(struct clk_regmap_gate_data){
2507                 .offset = HHI_VDEC2_CLK_CNTL,
2508                 .bit_idx = 24,
2509         },
2510         .hw.init = &(struct clk_init_data) {
2511                 .name = "vdec_hevc",
2512                 .ops = &clk_regmap_gate_ops,
2513                 .parent_hws = (const struct clk_hw *[]) {
2514                         &gxbb_vdec_hevc_div.hw
2515                 },
2516                 .num_parents = 1,
2517                 .flags = CLK_SET_RATE_PARENT,
2518         },
2519 };
2520 
2521 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
2522                                     9, 10, 11, 13, 14, };
2523 static const struct clk_parent_data gen_clk_parent_data[] = {
2524         { .fw_name = "xtal", },
2525         { .hw = &gxbb_vdec_1.hw },
2526         { .hw = &gxbb_vdec_hevc.hw },
2527         { .hw = &gxbb_mpll0.hw },
2528         { .hw = &gxbb_mpll1.hw },
2529         { .hw = &gxbb_mpll2.hw },
2530         { .hw = &gxbb_fclk_div4.hw },
2531         { .hw = &gxbb_fclk_div3.hw },
2532         { .hw = &gxbb_fclk_div5.hw },
2533         { .hw = &gxbb_fclk_div7.hw },
2534         { .hw = &gxbb_gp0_pll.hw },
2535 };
2536 
2537 static struct clk_regmap gxbb_gen_clk_sel = {
2538         .data = &(struct clk_regmap_mux_data){
2539                 .offset = HHI_GEN_CLK_CNTL,
2540                 .mask = 0xf,
2541                 .shift = 12,
2542                 .table = mux_table_gen_clk,
2543         },
2544         .hw.init = &(struct clk_init_data){
2545                 .name = "gen_clk_sel",
2546                 .ops = &clk_regmap_mux_ops,
2547                 /*
2548                  * bits 15:12 selects from 14 possible parents:
2549                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2550                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2551                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2552                  */
2553                 .parent_data = gen_clk_parent_data,
2554                 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2555         },
2556 };
2557 
2558 static struct clk_regmap gxbb_gen_clk_div = {
2559         .data = &(struct clk_regmap_div_data){
2560                 .offset = HHI_GEN_CLK_CNTL,
2561                 .shift = 0,
2562                 .width = 11,
2563         },
2564         .hw.init = &(struct clk_init_data){
2565                 .name = "gen_clk_div",
2566                 .ops = &clk_regmap_divider_ops,
2567                 .parent_hws = (const struct clk_hw *[]) {
2568                         &gxbb_gen_clk_sel.hw
2569                 },
2570                 .num_parents = 1,
2571                 .flags = CLK_SET_RATE_PARENT,
2572         },
2573 };
2574 
2575 static struct clk_regmap gxbb_gen_clk = {
2576         .data = &(struct clk_regmap_gate_data){
2577                 .offset = HHI_GEN_CLK_CNTL,
2578                 .bit_idx = 7,
2579         },
2580         .hw.init = &(struct clk_init_data){
2581                 .name = "gen_clk",
2582                 .ops = &clk_regmap_gate_ops,
2583                 .parent_hws = (const struct clk_hw *[]) {
2584                         &gxbb_gen_clk_div.hw
2585                 },
2586                 .num_parents = 1,
2587                 .flags = CLK_SET_RATE_PARENT,
2588         },
2589 };
2590 
2591 #define MESON_GATE(_name, _reg, _bit) \
2592         MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2593 
2594 /* Everything Else (EE) domain gates */
2595 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2596 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2597 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2598 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2599 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2600 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2601 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2602 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2603 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2604 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2605 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2606 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2607 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2608 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2609 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2610 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2611 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2612 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2613 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2614 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2615 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2616 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2617 
2618 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2619 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2620 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2621 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
2622 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
2623 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
2624 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
2625 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
2626 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
2627 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
2628 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
2629 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2630 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2631 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2632 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2633 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2634 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2635 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2636 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2637 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2638 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2639 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2640 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2641 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2642 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2643 
2644 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2645 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2646 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2647 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2648 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2649 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2650 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2651 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2652 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2653 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2654 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2655 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2656 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2657 
2658 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2659 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2660 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2661 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2662 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2663 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2664 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2665 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2666 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2667 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2668 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2669 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2670 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2671 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2672 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2673 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2674 
2675 /* Always On (AO) domain gates */
2676 
2677 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2678 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2679 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2680 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2681 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2682 
2683 /* Array of all clocks provided by this provider */
2684 
2685 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2686         .hws = {
2687                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2688                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
2689                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2690                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2691                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2692                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2693                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2694                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2695                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2696                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2697                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2698                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2699                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2700                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2701                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2702                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2703                 [CLKID_DOS]                 = &gxbb_dos.hw,
2704                 [CLKID_ISA]                 = &gxbb_isa.hw,
2705                 [CLKID_PL301]               = &gxbb_pl301.hw,
2706                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2707                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2708                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2709                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2710                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2711                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2712                 [CLKID_UART0]               = &gxbb_uart0.hw,
2713                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2714                 [CLKID_STREAM]              = &gxbb_stream.hw,
2715                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2716                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2717                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2718                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2719                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2720                 [CLKID_SPI]                 = &gxbb_spi.hw,
2721                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2722                 [CLKID_ETH]                 = &gxbb_eth.hw,
2723                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2724                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2725                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2726                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2727                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2728                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2729                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2730                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2731                 [CLKID_ADC]                 = &gxbb_adc.hw,
2732                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2733                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2734                 [CLKID_UART1]               = &gxbb_uart1.hw,
2735                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2736                 [CLKID_USB0]                = &gxbb_usb0.hw,
2737                 [CLKID_USB1]                = &gxbb_usb1.hw,
2738                 [CLKID_RESET]               = &gxbb_reset.hw,
2739                 [CLKID_NAND]                = &gxbb_nand.hw,
2740                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2741                 [CLKID_USB]                 = &gxbb_usb.hw,
2742                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2743                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2744                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2745                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2746                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2747                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2748                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2749                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2750                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2751                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2752                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2753                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2754                 [CLKID_UART2]               = &gxbb_uart2.hw,
2755                 [CLKID_SANA]                = &gxbb_sana.hw,
2756                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2757                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2758                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2759                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2760                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2761                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2762                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2763                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2764                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2765                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2766                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2767                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2768                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2769                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2770                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2771                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2772                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2773                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2774                 [CLKID_EDP]                 = &gxbb_edp.hw,
2775                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2776                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2777                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2778                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2779                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2780                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2781                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2782                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2783                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2784                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2785                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2786                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2787                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
2788                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
2789                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
2790                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
2791                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
2792                 [CLKID_MALI]                = &gxbb_mali.hw,
2793                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
2794                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
2795                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
2796                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
2797                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2798                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2799                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
2800                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
2801                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
2802                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
2803                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2804                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2805                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
2806                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2807                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2808                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
2809                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2810                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2811                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
2812                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
2813                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
2814                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
2815                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
2816                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
2817                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
2818                 [CLKID_VPU]                 = &gxbb_vpu.hw,
2819                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
2820                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
2821                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
2822                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
2823                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
2824                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
2825                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
2826                 [CLKID_VAPB]                = &gxbb_vapb.hw,
2827                 [CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
2828                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
2829                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
2830                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
2831                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
2832                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
2833                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
2834                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
2835                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
2836                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
2837                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
2838                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
2839                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
2840                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
2841                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
2842                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
2843                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
2844                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
2845                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
2846                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
2847                 [CLKID_HDMI_PLL_DCO]        = &gxbb_hdmi_pll_dco.hw,
2848                 [CLKID_HDMI_PLL_OD]         = &gxbb_hdmi_pll_od.hw,
2849                 [CLKID_HDMI_PLL_OD2]        = &gxbb_hdmi_pll_od2.hw,
2850                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
2851                 [CLKID_GP0_PLL_DCO]         = &gxbb_gp0_pll_dco.hw,
2852                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
2853                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
2854                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
2855                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
2856                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
2857                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
2858                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
2859                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
2860                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
2861                 [CLKID_VCLK]                = &gxbb_vclk.hw,
2862                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
2863                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
2864                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
2865                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
2866                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
2867                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
2868                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
2869                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
2870                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
2871                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
2872                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
2873                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
2874                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
2875                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
2876                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
2877                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
2878                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
2879                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
2880                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
2881                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
2882                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
2883                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
2884                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
2885                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
2886                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
2887                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
2888                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
2889                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
2890                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
2891                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
2892                 [NR_CLKS]                   = NULL,
2893         },
2894         .num = NR_CLKS,
2895 };
2896 
2897 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2898         .hws = {
2899                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2900                 [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
2901                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2902                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2903                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2904                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2905                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2906                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2907                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2908                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2909                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2910                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2911                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2912                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2913                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2914                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2915                 [CLKID_DOS]                 = &gxbb_dos.hw,
2916                 [CLKID_ISA]                 = &gxbb_isa.hw,
2917                 [CLKID_PL301]               = &gxbb_pl301.hw,
2918                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2919                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2920                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2921                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2922                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2923                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2924                 [CLKID_UART0]               = &gxbb_uart0.hw,
2925                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2926                 [CLKID_STREAM]              = &gxbb_stream.hw,
2927                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2928                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2929                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2930                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2931                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2932                 [CLKID_SPI]                 = &gxbb_spi.hw,
2933                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2934                 [CLKID_ETH]                 = &gxbb_eth.hw,
2935                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2936                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2937                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2938                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2939                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2940                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2941                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2942                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2943                 [CLKID_ADC]                 = &gxbb_adc.hw,
2944                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2945                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2946                 [CLKID_UART1]               = &gxbb_uart1.hw,
2947                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2948                 [CLKID_USB0]                = &gxbb_usb0.hw,
2949                 [CLKID_USB1]                = &gxbb_usb1.hw,
2950                 [CLKID_RESET]               = &gxbb_reset.hw,
2951                 [CLKID_NAND]                = &gxbb_nand.hw,
2952                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2953                 [CLKID_USB]                 = &gxbb_usb.hw,
2954                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2955                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2956                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2957                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2958                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2959                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2960                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2961                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2962                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2963                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2964                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2965                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2966                 [CLKID_UART2]               = &gxbb_uart2.hw,
2967                 [CLKID_SANA]                = &gxbb_sana.hw,
2968                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2969                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2970                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2971                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2972                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2973                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2974                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2975                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2976                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2977                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2978                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2979                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2980                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2981                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2982                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2983                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2984                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2985                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2986                 [CLKID_EDP]                 = &gxbb_edp.hw,
2987                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2988                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2989                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2990                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2991                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2992                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2993                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2994                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2995                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2996                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2997                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2998                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2999                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
3000                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
3001                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
3002                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
3003                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
3004                 [CLKID_MALI]                = &gxbb_mali.hw,
3005                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
3006                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
3007                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
3008                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
3009                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
3010                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
3011                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
3012                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
3013                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
3014                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
3015                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
3016                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
3017                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
3018                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
3019                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
3020                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
3021                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
3022                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
3023                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
3024                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
3025                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
3026                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
3027                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
3028                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
3029                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
3030                 [CLKID_VPU]                 = &gxbb_vpu.hw,
3031                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
3032                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
3033                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
3034                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
3035                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
3036                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
3037                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
3038                 [CLKID_VAPB]                = &gxbb_vapb.hw,
3039                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
3040                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
3041                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
3042                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
3043                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
3044                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
3045                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
3046                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
3047                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
3048                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
3049                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
3050                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
3051                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
3052                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
3053                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
3054                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
3055                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
3056                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
3057                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
3058                 [CLKID_HDMI_PLL_DCO]        = &gxl_hdmi_pll_dco.hw,
3059                 [CLKID_HDMI_PLL_OD]         = &gxl_hdmi_pll_od.hw,
3060                 [CLKID_HDMI_PLL_OD2]        = &gxl_hdmi_pll_od2.hw,
3061                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
3062                 [CLKID_GP0_PLL_DCO]         = &gxl_gp0_pll_dco.hw,
3063                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
3064                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
3065                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
3066                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
3067                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
3068                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
3069                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
3070                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
3071                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
3072                 [CLKID_VCLK]                = &gxbb_vclk.hw,
3073                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
3074                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
3075                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
3076                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
3077                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
3078                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
3079                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
3080                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
3081                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
3082                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
3083                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
3084                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
3085                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
3086                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
3087                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
3088                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
3089                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
3090                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
3091                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
3092                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
3093                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
3094                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
3095                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
3096                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
3097                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
3098                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
3099                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
3100                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
3101                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
3102                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
3103                 [NR_CLKS]                   = NULL,
3104         },
3105         .num = NR_CLKS,
3106 };
3107 
3108 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3109         &gxbb_clk81,
3110         &gxbb_ddr,
3111         &gxbb_dos,
3112         &gxbb_isa,
3113         &gxbb_pl301,
3114         &gxbb_periphs,
3115         &gxbb_spicc,
3116         &gxbb_i2c,
3117         &gxbb_sar_adc,
3118         &gxbb_smart_card,
3119         &gxbb_rng0,
3120         &gxbb_uart0,
3121         &gxbb_sdhc,
3122         &gxbb_stream,
3123         &gxbb_async_fifo,
3124         &gxbb_sdio,
3125         &gxbb_abuf,
3126         &gxbb_hiu_iface,
3127         &gxbb_assist_misc,
3128         &gxbb_spi,
3129         &gxbb_i2s_spdif,
3130         &gxbb_eth,
3131         &gxbb_demux,
3132         &gxbb_aiu_glue,
3133         &gxbb_iec958,
3134         &gxbb_i2s_out,
3135         &gxbb_amclk,
3136         &gxbb_aififo2,
3137         &gxbb_mixer,
3138         &gxbb_mixer_iface,
3139         &gxbb_adc,
3140         &gxbb_blkmv,
3141         &gxbb_aiu,
3142         &gxbb_uart1,
3143         &gxbb_g2d,
3144         &gxbb_usb0,
3145         &gxbb_usb1,
3146         &gxbb_reset,
3147         &gxbb_nand,
3148         &gxbb_dos_parser,
3149         &gxbb_usb,
3150         &gxbb_vdin1,
3151         &gxbb_ahb_arb0,
3152         &gxbb_efuse,
3153         &gxbb_boot_rom,
3154         &gxbb_ahb_data_bus,
3155         &gxbb_ahb_ctrl_bus,
3156         &gxbb_hdmi_intr_sync,
3157         &gxbb_hdmi_pclk,
3158         &gxbb_usb1_ddr_bridge,
3159         &gxbb_usb0_ddr_bridge,
3160         &gxbb_mmc_pclk,
3161         &gxbb_dvin,
3162         &gxbb_uart2,
3163         &gxbb_sana,
3164         &gxbb_vpu_intr,
3165         &gxbb_sec_ahb_ahb3_bridge,
3166         &gxbb_clk81_a53,
3167         &gxbb_vclk2_venci0,
3168         &gxbb_vclk2_venci1,
3169         &gxbb_vclk2_vencp0,
3170         &gxbb_vclk2_vencp1,
3171         &gxbb_gclk_venci_int0,
3172         &gxbb_gclk_vencp_int,
3173         &gxbb_dac_clk,
3174         &gxbb_aoclk_gate,
3175         &gxbb_iec958_gate,
3176         &gxbb_enc480p,
3177         &gxbb_rng1,
3178         &gxbb_gclk_venci_int1,
3179         &gxbb_vclk2_venclmcc,
3180         &gxbb_vclk2_vencl,
3181         &gxbb_vclk_other,
3182         &gxbb_edp,
3183         &gxbb_ao_media_cpu,
3184         &gxbb_ao_ahb_sram,
3185         &gxbb_ao_ahb_bus,
3186         &gxbb_ao_iface,
3187         &gxbb_ao_i2c,
3188         &gxbb_emmc_a,
3189         &gxbb_emmc_b,
3190         &gxbb_emmc_c,
3191         &gxbb_sar_adc_clk,
3192         &gxbb_mali_0,
3193         &gxbb_mali_1,
3194         &gxbb_cts_amclk,
3195         &gxbb_cts_mclk_i958,
3196         &gxbb_32k_clk,
3197         &gxbb_sd_emmc_a_clk0,
3198         &gxbb_sd_emmc_b_clk0,
3199         &gxbb_sd_emmc_c_clk0,
3200         &gxbb_vpu_0,
3201         &gxbb_vpu_1,
3202         &gxbb_vapb_0,
3203         &gxbb_vapb_1,
3204         &gxbb_vapb,
3205         &gxbb_mpeg_clk_div,
3206         &gxbb_sar_adc_clk_div,
3207         &gxbb_mali_0_div,
3208         &gxbb_mali_1_div,
3209         &gxbb_cts_mclk_i958_div,
3210         &gxbb_32k_clk_div,
3211         &gxbb_sd_emmc_a_clk0_div,
3212         &gxbb_sd_emmc_b_clk0_div,
3213         &gxbb_sd_emmc_c_clk0_div,
3214         &gxbb_vpu_0_div,
3215         &gxbb_vpu_1_div,
3216         &gxbb_vapb_0_div,
3217         &gxbb_vapb_1_div,
3218         &gxbb_mpeg_clk_sel,
3219         &gxbb_sar_adc_clk_sel,
3220         &gxbb_mali_0_sel,
3221         &gxbb_mali_1_sel,
3222         &gxbb_mali,
3223         &gxbb_cts_amclk_sel,
3224         &gxbb_cts_mclk_i958_sel,
3225         &gxbb_cts_i958,
3226         &gxbb_32k_clk_sel,
3227         &gxbb_sd_emmc_a_clk0_sel,
3228         &gxbb_sd_emmc_b_clk0_sel,
3229         &gxbb_sd_emmc_c_clk0_sel,
3230         &gxbb_vpu_0_sel,
3231         &gxbb_vpu_1_sel,
3232         &gxbb_vpu,
3233         &gxbb_vapb_0_sel,
3234         &gxbb_vapb_1_sel,
3235         &gxbb_vapb_sel,
3236         &gxbb_mpll0,
3237         &gxbb_mpll1,
3238         &gxbb_mpll2,
3239         &gxbb_mpll0_div,
3240         &gxbb_mpll1_div,
3241         &gxbb_mpll2_div,
3242         &gxbb_cts_amclk_div,
3243         &gxbb_fixed_pll,
3244         &gxbb_sys_pll,
3245         &gxbb_mpll_prediv,
3246         &gxbb_fclk_div2,
3247         &gxbb_fclk_div3,
3248         &gxbb_fclk_div4,
3249         &gxbb_fclk_div5,
3250         &gxbb_fclk_div7,
3251         &gxbb_vdec_1_sel,
3252         &gxbb_vdec_1_div,
3253         &gxbb_vdec_1,
3254         &gxbb_vdec_hevc_sel,
3255         &gxbb_vdec_hevc_div,
3256         &gxbb_vdec_hevc,
3257         &gxbb_gen_clk_sel,
3258         &gxbb_gen_clk_div,
3259         &gxbb_gen_clk,
3260         &gxbb_fixed_pll_dco,
3261         &gxbb_sys_pll_dco,
3262         &gxbb_gp0_pll,
3263         &gxbb_vid_pll,
3264         &gxbb_vid_pll_sel,
3265         &gxbb_vid_pll_div,
3266         &gxbb_vclk,
3267         &gxbb_vclk_sel,
3268         &gxbb_vclk_div,
3269         &gxbb_vclk_input,
3270         &gxbb_vclk_div1,
3271         &gxbb_vclk_div2_en,
3272         &gxbb_vclk_div4_en,
3273         &gxbb_vclk_div6_en,
3274         &gxbb_vclk_div12_en,
3275         &gxbb_vclk2,
3276         &gxbb_vclk2_sel,
3277         &gxbb_vclk2_div,
3278         &gxbb_vclk2_input,
3279         &gxbb_vclk2_div1,
3280         &gxbb_vclk2_div2_en,
3281         &gxbb_vclk2_div4_en,
3282         &gxbb_vclk2_div6_en,
3283         &gxbb_vclk2_div12_en,
3284         &gxbb_cts_enci,
3285         &gxbb_cts_enci_sel,
3286         &gxbb_cts_encp,
3287         &gxbb_cts_encp_sel,
3288         &gxbb_cts_vdac,
3289         &gxbb_cts_vdac_sel,
3290         &gxbb_hdmi_tx,
3291         &gxbb_hdmi_tx_sel,
3292         &gxbb_hdmi_sel,
3293         &gxbb_hdmi_div,
3294         &gxbb_hdmi,
3295         &gxbb_gp0_pll_dco,
3296         &gxbb_hdmi_pll,
3297         &gxbb_hdmi_pll_od,
3298         &gxbb_hdmi_pll_od2,
3299         &gxbb_hdmi_pll_dco,
3300 };
3301 
3302 static struct clk_regmap *const gxl_clk_regmaps[] = {
3303         &gxbb_clk81,
3304         &gxbb_ddr,
3305         &gxbb_dos,
3306         &gxbb_isa,
3307         &gxbb_pl301,
3308         &gxbb_periphs,
3309         &gxbb_spicc,
3310         &gxbb_i2c,
3311         &gxbb_sar_adc,
3312         &gxbb_smart_card,
3313         &gxbb_rng0,
3314         &gxbb_uart0,
3315         &gxbb_sdhc,
3316         &gxbb_stream,
3317         &gxbb_async_fifo,
3318         &gxbb_sdio,
3319         &gxbb_abuf,
3320         &gxbb_hiu_iface,
3321         &gxbb_assist_misc,
3322         &gxbb_spi,
3323         &gxbb_i2s_spdif,
3324         &gxbb_eth,
3325         &gxbb_demux,
3326         &gxbb_aiu_glue,
3327         &gxbb_iec958,
3328         &gxbb_i2s_out,
3329         &gxbb_amclk,
3330         &gxbb_aififo2,
3331         &gxbb_mixer,
3332         &gxbb_mixer_iface,
3333         &gxbb_adc,
3334         &gxbb_blkmv,
3335         &gxbb_aiu,
3336         &gxbb_uart1,
3337         &gxbb_g2d,
3338         &gxbb_usb0,
3339         &gxbb_usb1,
3340         &gxbb_reset,
3341         &gxbb_nand,
3342         &gxbb_dos_parser,
3343         &gxbb_usb,
3344         &gxbb_vdin1,
3345         &gxbb_ahb_arb0,
3346         &gxbb_efuse,
3347         &gxbb_boot_rom,
3348         &gxbb_ahb_data_bus,
3349         &gxbb_ahb_ctrl_bus,
3350         &gxbb_hdmi_intr_sync,
3351         &gxbb_hdmi_pclk,
3352         &gxbb_usb1_ddr_bridge,
3353         &gxbb_usb0_ddr_bridge,
3354         &gxbb_mmc_pclk,
3355         &gxbb_dvin,
3356         &gxbb_uart2,
3357         &gxbb_sana,
3358         &gxbb_vpu_intr,
3359         &gxbb_sec_ahb_ahb3_bridge,
3360         &gxbb_clk81_a53,
3361         &gxbb_vclk2_venci0,
3362         &gxbb_vclk2_venci1,
3363         &gxbb_vclk2_vencp0,
3364         &gxbb_vclk2_vencp1,
3365         &gxbb_gclk_venci_int0,
3366         &gxbb_gclk_vencp_int,
3367         &gxbb_dac_clk,
3368         &gxbb_aoclk_gate,
3369         &gxbb_iec958_gate,
3370         &gxbb_enc480p,
3371         &gxbb_rng1,
3372         &gxbb_gclk_venci_int1,
3373         &gxbb_vclk2_venclmcc,
3374         &gxbb_vclk2_vencl,
3375         &gxbb_vclk_other,
3376         &gxbb_edp,
3377         &gxbb_ao_media_cpu,
3378         &gxbb_ao_ahb_sram,
3379         &gxbb_ao_ahb_bus,
3380         &gxbb_ao_iface,
3381         &gxbb_ao_i2c,
3382         &gxbb_emmc_a,
3383         &gxbb_emmc_b,
3384         &gxbb_emmc_c,
3385         &gxbb_sar_adc_clk,
3386         &gxbb_mali_0,
3387         &gxbb_mali_1,
3388         &gxbb_cts_amclk,
3389         &gxbb_cts_mclk_i958,
3390         &gxbb_32k_clk,
3391         &gxbb_sd_emmc_a_clk0,
3392         &gxbb_sd_emmc_b_clk0,
3393         &gxbb_sd_emmc_c_clk0,
3394         &gxbb_vpu_0,
3395         &gxbb_vpu_1,
3396         &gxbb_vapb_0,
3397         &gxbb_vapb_1,
3398         &gxbb_vapb,
3399         &gxbb_mpeg_clk_div,
3400         &gxbb_sar_adc_clk_div,
3401         &gxbb_mali_0_div,
3402         &gxbb_mali_1_div,
3403         &gxbb_cts_mclk_i958_div,
3404         &gxbb_32k_clk_div,
3405         &gxbb_sd_emmc_a_clk0_div,
3406         &gxbb_sd_emmc_b_clk0_div,
3407         &gxbb_sd_emmc_c_clk0_div,
3408         &gxbb_vpu_0_div,
3409         &gxbb_vpu_1_div,
3410         &gxbb_vapb_0_div,
3411         &gxbb_vapb_1_div,
3412         &gxbb_mpeg_clk_sel,
3413         &gxbb_sar_adc_clk_sel,
3414         &gxbb_mali_0_sel,
3415         &gxbb_mali_1_sel,
3416         &gxbb_mali,
3417         &gxbb_cts_amclk_sel,
3418         &gxbb_cts_mclk_i958_sel,
3419         &gxbb_cts_i958,
3420         &gxbb_32k_clk_sel,
3421         &gxbb_sd_emmc_a_clk0_sel,
3422         &gxbb_sd_emmc_b_clk0_sel,
3423         &gxbb_sd_emmc_c_clk0_sel,
3424         &gxbb_vpu_0_sel,
3425         &gxbb_vpu_1_sel,
3426         &gxbb_vpu,
3427         &gxbb_vapb_0_sel,
3428         &gxbb_vapb_1_sel,
3429         &gxbb_vapb_sel,
3430         &gxbb_mpll0,
3431         &gxbb_mpll1,
3432         &gxbb_mpll2,
3433         &gxbb_mpll0_div,
3434         &gxbb_mpll1_div,
3435         &gxbb_mpll2_div,
3436         &gxbb_cts_amclk_div,
3437         &gxbb_fixed_pll,
3438         &gxbb_sys_pll,
3439         &gxbb_mpll_prediv,
3440         &gxbb_fclk_div2,
3441         &gxbb_fclk_div3,
3442         &gxbb_fclk_div4,
3443         &gxbb_fclk_div5,
3444         &gxbb_fclk_div7,
3445         &gxbb_vdec_1_sel,
3446         &gxbb_vdec_1_div,
3447         &gxbb_vdec_1,
3448         &gxbb_vdec_hevc_sel,
3449         &gxbb_vdec_hevc_div,
3450         &gxbb_vdec_hevc,
3451         &gxbb_gen_clk_sel,
3452         &gxbb_gen_clk_div,
3453         &gxbb_gen_clk,
3454         &gxbb_fixed_pll_dco,
3455         &gxbb_sys_pll_dco,
3456         &gxbb_gp0_pll,
3457         &gxbb_vid_pll,
3458         &gxbb_vid_pll_sel,
3459         &gxbb_vid_pll_div,
3460         &gxbb_vclk,
3461         &gxbb_vclk_sel,
3462         &gxbb_vclk_div,
3463         &gxbb_vclk_input,
3464         &gxbb_vclk_div1,
3465         &gxbb_vclk_div2_en,
3466         &gxbb_vclk_div4_en,
3467         &gxbb_vclk_div6_en,
3468         &gxbb_vclk_div12_en,
3469         &gxbb_vclk2,
3470         &gxbb_vclk2_sel,
3471         &gxbb_vclk2_div,
3472         &gxbb_vclk2_input,
3473         &gxbb_vclk2_div1,
3474         &gxbb_vclk2_div2_en,
3475         &gxbb_vclk2_div4_en,
3476         &gxbb_vclk2_div6_en,
3477         &gxbb_vclk2_div12_en,
3478         &gxbb_cts_enci,
3479         &gxbb_cts_enci_sel,
3480         &gxbb_cts_encp,
3481         &gxbb_cts_encp_sel,
3482         &gxbb_cts_vdac,
3483         &gxbb_cts_vdac_sel,
3484         &gxbb_hdmi_tx,
3485         &gxbb_hdmi_tx_sel,
3486         &gxbb_hdmi_sel,
3487         &gxbb_hdmi_div,
3488         &gxbb_hdmi,
3489         &gxl_gp0_pll_dco,
3490         &gxl_hdmi_pll,
3491         &gxl_hdmi_pll_od,
3492         &gxl_hdmi_pll_od2,
3493         &gxl_hdmi_pll_dco,
3494 };
3495 
3496 static const struct meson_eeclkc_data gxbb_clkc_data = {
3497         .regmap_clks = gxbb_clk_regmaps,
3498         .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3499         .hw_onecell_data = &gxbb_hw_onecell_data,
3500 };
3501 
3502 static const struct meson_eeclkc_data gxl_clkc_data = {
3503         .regmap_clks = gxl_clk_regmaps,
3504         .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3505         .hw_onecell_data = &gxl_hw_onecell_data,
3506 };
3507 
3508 static const struct of_device_id clkc_match_table[] = {
3509         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3510         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3511         {},
3512 };
3513 
3514 static struct platform_driver gxbb_driver = {
3515         .probe          = meson_eeclkc_probe,
3516         .driver         = {
3517                 .name   = "gxbb-clkc",
3518                 .of_match_table = clkc_match_table,
3519         },
3520 };
3521 
3522 builtin_platform_driver(gxbb_driver);

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