drivers/clk/versatile/clk-icst.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
vco_get
vco_set
icst_recalc_rate
icst_round_rate
icst_set_rate
icst_clk_setup
icst_clk_register
of_syscon_icst_setup
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the ICST307 VCO clock found in the ARM Reference designs.
   4  * We wrap the custom interface from <asm/hardware/icst.h> into the generic
   5  * clock framework.
   6  *
   7  * Copyright (C) 2012-2015 Linus Walleij
   8  *
   9  * TODO: when all ARM reference designs are migrated to generic clocks, the
  10  * ICST clock code from the ARM tree should probably be merged into this
  11  * file.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/export.h>
  16 #include <linux/err.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/io.h>
  19 #include <linux/regmap.h>
  20 #include <linux/mfd/syscon.h>
  21 
  22 #include "icst.h"
  23 #include "clk-icst.h"
  24 
  25 /* Magic unlocking token used on all Versatile boards */
  26 #define VERSATILE_LOCK_VAL      0xA05F
  27 
  28 #define VERSATILE_AUX_OSC_BITS 0x7FFFF
  29 #define INTEGRATOR_AP_CM_BITS 0xFF
  30 #define INTEGRATOR_AP_SYS_BITS 0xFF
  31 #define INTEGRATOR_CP_CM_CORE_BITS 0x7FF
  32 #define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000
  33 
  34 #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
  35 
  36 /**
  37  * enum icst_control_type - the type of ICST control register
  38  */
  39 enum icst_control_type {
  40         ICST_VERSATILE, /* The standard type, all control bits available */
  41         ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */
  42         ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */
  43         ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */
  44         ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */
  45         ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */
  46 };
  47 
  48 /**
  49  * struct clk_icst - ICST VCO clock wrapper
  50  * @hw: corresponding clock hardware entry
  51  * @vcoreg: VCO register address
  52  * @lockreg: VCO lock register address
  53  * @params: parameters for this ICST instance
  54  * @rate: current rate
  55  * @ctype: the type of control register for the ICST
  56  */
  57 struct clk_icst {
  58         struct clk_hw hw;
  59         struct regmap *map;
  60         u32 vcoreg_off;
  61         u32 lockreg_off;
  62         struct icst_params *params;
  63         unsigned long rate;
  64         enum icst_control_type ctype;
  65 };
  66 
  67 #define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
  68 
  69 /**
  70  * vco_get() - get ICST VCO settings from a certain ICST
  71  * @icst: the ICST clock to get
  72  * @vco: the VCO struct to return the value in
  73  */
  74 static int vco_get(struct clk_icst *icst, struct icst_vco *vco)
  75 {
  76         u32 val;
  77         int ret;
  78 
  79         ret = regmap_read(icst->map, icst->vcoreg_off, &val);
  80         if (ret)
  81                 return ret;
  82 
  83         /*
  84          * The Integrator/AP core clock can only access the low eight
  85          * bits of the v PLL divider. Bit 8 is tied low and always zero,
  86          * r is hardwired to 22 and output divider s is hardwired to 1
  87          * (divide by 2) according to the document
  88          * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and
  89          * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14.
  90          */
  91         if (icst->ctype == ICST_INTEGRATOR_AP_CM) {
  92                 vco->v = val & INTEGRATOR_AP_CM_BITS;
  93                 vco->r = 22;
  94                 vco->s = 1;
  95                 return 0;
  96         }
  97 
  98         /*
  99          * The Integrator/AP system clock on the base board can only
 100          * access the low eight bits of the v PLL divider. Bit 8 is tied low
 101          * and always zero, r is hardwired to 46, and the output divider is
 102          * hardwired to 3 (divide by 4) according to the document
 103          * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B,
 104          * page 3-16.
 105          */
 106         if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
 107                 vco->v = val & INTEGRATOR_AP_SYS_BITS;
 108                 vco->r = 46;
 109                 vco->s = 3;
 110                 return 0;
 111         }
 112 
 113         /*
 114          * The Integrator/AP PCI clock is using an odd pattern to create
 115          * the child clock, basically a single bit called DIVX/Y is used
 116          * to select between two different hardwired values: setting the
 117          * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the
 118          * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies
 119          * 33 or 25 MHz respectively.
 120          */
 121         if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
 122                 bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ);
 123 
 124                 vco->v = divxy ? 17 : 14;
 125                 vco->r = divxy ? 22 : 14;
 126                 vco->s = 1;
 127                 return 0;
 128         }
 129 
 130         /*
 131          * The Integrator/CP core clock can access the low eight bits
 132          * of the v PLL divider. Bit 8 is tied low and always zero,
 133          * r is hardwired to 22 and the output divider s is accessible
 134          * in bits 8 thru 10 according to the document
 135          * "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide"
 136          * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10.
 137          */
 138         if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
 139                 vco->v = val & 0xFF;
 140                 vco->r = 22;
 141                 vco->s = (val >> 8) & 7;
 142                 return 0;
 143         }
 144 
 145         if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
 146                 vco->v = (val >> 12) & 0xFF;
 147                 vco->r = 22;
 148                 vco->s = (val >> 20) & 7;
 149                 return 0;
 150         }
 151 
 152         vco->v = val & 0x1ff;
 153         vco->r = (val >> 9) & 0x7f;
 154         vco->s = (val >> 16) & 03;
 155         return 0;
 156 }
 157 
 158 /**
 159  * vco_set() - commit changes to an ICST VCO
 160  * @icst: the ICST clock to set
 161  * @vco: the VCO struct to set the changes from
 162  */
 163 static int vco_set(struct clk_icst *icst, struct icst_vco vco)
 164 {
 165         u32 mask;
 166         u32 val;
 167         int ret;
 168 
 169         /* Mask the bits used by the VCO */
 170         switch (icst->ctype) {
 171         case ICST_INTEGRATOR_AP_CM:
 172                 mask = INTEGRATOR_AP_CM_BITS;
 173                 val = vco.v & 0xFF;
 174                 if (vco.v & 0x100)
 175                         pr_err("ICST error: tried to set bit 8 of VDW\n");
 176                 if (vco.s != 1)
 177                         pr_err("ICST error: tried to use VOD != 1\n");
 178                 if (vco.r != 22)
 179                         pr_err("ICST error: tried to use RDW != 22\n");
 180                 break;
 181         case ICST_INTEGRATOR_AP_SYS:
 182                 mask = INTEGRATOR_AP_SYS_BITS;
 183                 val = vco.v & 0xFF;
 184                 if (vco.v & 0x100)
 185                         pr_err("ICST error: tried to set bit 8 of VDW\n");
 186                 if (vco.s != 3)
 187                         pr_err("ICST error: tried to use VOD != 1\n");
 188                 if (vco.r != 46)
 189                         pr_err("ICST error: tried to use RDW != 22\n");
 190                 break;
 191         case ICST_INTEGRATOR_CP_CM_CORE:
 192                 mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */
 193                 val = (vco.v & 0xFF) | vco.s << 8;
 194                 if (vco.v & 0x100)
 195                         pr_err("ICST error: tried to set bit 8 of VDW\n");
 196                 if (vco.r != 22)
 197                         pr_err("ICST error: tried to use RDW != 22\n");
 198                 break;
 199         case ICST_INTEGRATOR_CP_CM_MEM:
 200                 mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */
 201                 val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
 202                 if (vco.v & 0x100)
 203                         pr_err("ICST error: tried to set bit 8 of VDW\n");
 204                 if (vco.r != 22)
 205                         pr_err("ICST error: tried to use RDW != 22\n");
 206                 break;
 207         default:
 208                 /* Regular auxilary oscillator */
 209                 mask = VERSATILE_AUX_OSC_BITS;
 210                 val = vco.v | (vco.r << 9) | (vco.s << 16);
 211                 break;
 212         }
 213 
 214         pr_debug("ICST: new val = 0x%08x\n", val);
 215 
 216         /* This magic unlocks the VCO so it can be controlled */
 217         ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL);
 218         if (ret)
 219                 return ret;
 220         ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val);
 221         if (ret)
 222                 return ret;
 223         /* This locks the VCO again */
 224         ret = regmap_write(icst->map, icst->lockreg_off, 0);
 225         if (ret)
 226                 return ret;
 227         return 0;
 228 }
 229 
 230 static unsigned long icst_recalc_rate(struct clk_hw *hw,
 231                                       unsigned long parent_rate)
 232 {
 233         struct clk_icst *icst = to_icst(hw);
 234         struct icst_vco vco;
 235         int ret;
 236 
 237         if (parent_rate)
 238                 icst->params->ref = parent_rate;
 239         ret = vco_get(icst, &vco);
 240         if (ret) {
 241                 pr_err("ICST: could not get VCO setting\n");
 242                 return 0;
 243         }
 244         icst->rate = icst_hz(icst->params, vco);
 245         return icst->rate;
 246 }
 247 
 248 static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
 249                             unsigned long *prate)
 250 {
 251         struct clk_icst *icst = to_icst(hw);
 252         struct icst_vco vco;
 253 
 254         if (icst->ctype == ICST_INTEGRATOR_AP_CM ||
 255             icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
 256                 if (rate <= 12000000)
 257                         return 12000000;
 258                 if (rate >= 160000000)
 259                         return 160000000;
 260                 /* Slam to closest megahertz */
 261                 return DIV_ROUND_CLOSEST(rate, 1000000) * 1000000;
 262         }
 263 
 264         if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
 265                 if (rate <= 6000000)
 266                         return 6000000;
 267                 if (rate >= 66000000)
 268                         return 66000000;
 269                 /* Slam to closest 0.5 megahertz */
 270                 return DIV_ROUND_CLOSEST(rate, 500000) * 500000;
 271         }
 272 
 273         if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
 274                 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */
 275                 if (rate <= 3000000)
 276                         return 3000000;
 277                 if (rate >= 50000000)
 278                         return 5000000;
 279                 /* Slam to closest 0.25 MHz */
 280                 return DIV_ROUND_CLOSEST(rate, 250000) * 250000;
 281         }
 282 
 283         if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
 284                 /*
 285                  * If we're below or less than halfway from 25 to 33 MHz
 286                  * select 25 MHz
 287                  */
 288                 if (rate <= 25000000 || rate < 29000000)
 289                         return 25000000;
 290                 /* Else just return the default frequency */
 291                 return 33000000;
 292         }
 293 
 294         vco = icst_hz_to_vco(icst->params, rate);
 295         return icst_hz(icst->params, vco);
 296 }
 297 
 298 static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
 299                          unsigned long parent_rate)
 300 {
 301         struct clk_icst *icst = to_icst(hw);
 302         struct icst_vco vco;
 303 
 304         if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
 305                 /* This clock is especially primitive */
 306                 unsigned int val;
 307                 int ret;
 308 
 309                 if (rate == 25000000) {
 310                         val = 0;
 311                 } else if (rate == 33000000) {
 312                         val = INTEGRATOR_AP_PCI_25_33_MHZ;
 313                 } else {
 314                         pr_err("ICST: cannot set PCI frequency %lu\n",
 315                                rate);
 316                         return -EINVAL;
 317                 }
 318                 ret = regmap_write(icst->map, icst->lockreg_off,
 319                                    VERSATILE_LOCK_VAL);
 320                 if (ret)
 321                         return ret;
 322                 ret = regmap_update_bits(icst->map, icst->vcoreg_off,
 323                                          INTEGRATOR_AP_PCI_25_33_MHZ,
 324                                          val);
 325                 if (ret)
 326                         return ret;
 327                 /* This locks the VCO again */
 328                 ret = regmap_write(icst->map, icst->lockreg_off, 0);
 329                 if (ret)
 330                         return ret;
 331                 return 0;
 332         }
 333 
 334         if (parent_rate)
 335                 icst->params->ref = parent_rate;
 336         vco = icst_hz_to_vco(icst->params, rate);
 337         icst->rate = icst_hz(icst->params, vco);
 338         return vco_set(icst, vco);
 339 }
 340 
 341 static const struct clk_ops icst_ops = {
 342         .recalc_rate = icst_recalc_rate,
 343         .round_rate = icst_round_rate,
 344         .set_rate = icst_set_rate,
 345 };
 346 
 347 static struct clk *icst_clk_setup(struct device *dev,
 348                                   const struct clk_icst_desc *desc,
 349                                   const char *name,
 350                                   const char *parent_name,
 351                                   struct regmap *map,
 352                                   enum icst_control_type ctype)
 353 {
 354         struct clk *clk;
 355         struct clk_icst *icst;
 356         struct clk_init_data init;
 357         struct icst_params *pclone;
 358 
 359         icst = kzalloc(sizeof(*icst), GFP_KERNEL);
 360         if (!icst)
 361                 return ERR_PTR(-ENOMEM);
 362 
 363         pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
 364         if (!pclone) {
 365                 kfree(icst);
 366                 return ERR_PTR(-ENOMEM);
 367         }
 368 
 369         init.name = name;
 370         init.ops = &icst_ops;
 371         init.flags = 0;
 372         init.parent_names = (parent_name ? &parent_name : NULL);
 373         init.num_parents = (parent_name ? 1 : 0);
 374         icst->map = map;
 375         icst->hw.init = &init;
 376         icst->params = pclone;
 377         icst->vcoreg_off = desc->vco_offset;
 378         icst->lockreg_off = desc->lock_offset;
 379         icst->ctype = ctype;
 380 
 381         clk = clk_register(dev, &icst->hw);
 382         if (IS_ERR(clk)) {
 383                 kfree(pclone);
 384                 kfree(icst);
 385         }
 386 
 387         return clk;
 388 }
 389 
 390 struct clk *icst_clk_register(struct device *dev,
 391                         const struct clk_icst_desc *desc,
 392                         const char *name,
 393                         const char *parent_name,
 394                         void __iomem *base)
 395 {
 396         struct regmap_config icst_regmap_conf = {
 397                 .reg_bits = 32,
 398                 .val_bits = 32,
 399                 .reg_stride = 4,
 400         };
 401         struct regmap *map;
 402 
 403         map = regmap_init_mmio(dev, base, &icst_regmap_conf);
 404         if (IS_ERR(map)) {
 405                 pr_err("could not initialize ICST regmap\n");
 406                 return ERR_CAST(map);
 407         }
 408         return icst_clk_setup(dev, desc, name, parent_name, map,
 409                               ICST_VERSATILE);
 410 }
 411 EXPORT_SYMBOL_GPL(icst_clk_register);
 412 
 413 #ifdef CONFIG_OF
 414 /*
 415  * In a device tree, an memory-mapped ICST clock appear as a child
 416  * of a syscon node. Assume this and probe it only as a child of a
 417  * syscon.
 418  */
 419 
 420 static const struct icst_params icst525_params = {
 421         .vco_max        = ICST525_VCO_MAX_5V,
 422         .vco_min        = ICST525_VCO_MIN,
 423         .vd_min         = 8,
 424         .vd_max         = 263,
 425         .rd_min         = 3,
 426         .rd_max         = 65,
 427         .s2div          = icst525_s2div,
 428         .idx2s          = icst525_idx2s,
 429 };
 430 
 431 static const struct icst_params icst307_params = {
 432         .vco_max        = ICST307_VCO_MAX,
 433         .vco_min        = ICST307_VCO_MIN,
 434         .vd_min         = 4 + 8,
 435         .vd_max         = 511 + 8,
 436         .rd_min         = 1 + 2,
 437         .rd_max         = 127 + 2,
 438         .s2div          = icst307_s2div,
 439         .idx2s          = icst307_idx2s,
 440 };
 441 
 442 /**
 443  * The core modules on the Integrator/AP and Integrator/CP have
 444  * especially crippled ICST525 control.
 445  */
 446 static const struct icst_params icst525_apcp_cm_params = {
 447         .vco_max        = ICST525_VCO_MAX_5V,
 448         .vco_min        = ICST525_VCO_MIN,
 449         /* Minimum 12 MHz, VDW = 4 */
 450         .vd_min         = 12,
 451         /*
 452          * Maximum 160 MHz, VDW = 152 for all core modules, but
 453          * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually
 454          * go to 200 MHz (max VDW = 192).
 455          */
 456         .vd_max         = 192,
 457         /* r is hardcoded to 22 and this is the actual divisor, +2 */
 458         .rd_min         = 24,
 459         .rd_max         = 24,
 460         .s2div          = icst525_s2div,
 461         .idx2s          = icst525_idx2s,
 462 };
 463 
 464 static const struct icst_params icst525_ap_sys_params = {
 465         .vco_max        = ICST525_VCO_MAX_5V,
 466         .vco_min        = ICST525_VCO_MIN,
 467         /* Minimum 3 MHz, VDW = 4 */
 468         .vd_min         = 3,
 469         /* Maximum 50 MHz, VDW = 192 */
 470         .vd_max         = 50,
 471         /* r is hardcoded to 46 and this is the actual divisor, +2 */
 472         .rd_min         = 48,
 473         .rd_max         = 48,
 474         .s2div          = icst525_s2div,
 475         .idx2s          = icst525_idx2s,
 476 };
 477 
 478 static const struct icst_params icst525_ap_pci_params = {
 479         .vco_max        = ICST525_VCO_MAX_5V,
 480         .vco_min        = ICST525_VCO_MIN,
 481         /* Minimum 25 MHz */
 482         .vd_min         = 25,
 483         /* Maximum 33 MHz */
 484         .vd_max         = 33,
 485         /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */
 486         .rd_min         = 16,
 487         .rd_max         = 24,
 488         .s2div          = icst525_s2div,
 489         .idx2s          = icst525_idx2s,
 490 };
 491 
 492 static void __init of_syscon_icst_setup(struct device_node *np)
 493 {
 494         struct device_node *parent;
 495         struct regmap *map;
 496         struct clk_icst_desc icst_desc;
 497         const char *name = np->name;
 498         const char *parent_name;
 499         struct clk *regclk;
 500         enum icst_control_type ctype;
 501 
 502         /* We do not release this reference, we are using it perpetually */
 503         parent = of_get_parent(np);
 504         if (!parent) {
 505                 pr_err("no parent node for syscon ICST clock\n");
 506                 return;
 507         }
 508         map = syscon_node_to_regmap(parent);
 509         if (IS_ERR(map)) {
 510                 pr_err("no regmap for syscon ICST clock parent\n");
 511                 return;
 512         }
 513 
 514         if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
 515                 pr_err("no VCO register offset for ICST clock\n");
 516                 return;
 517         }
 518         if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) {
 519                 pr_err("no lock register offset for ICST clock\n");
 520                 return;
 521         }
 522 
 523         if (of_device_is_compatible(np, "arm,syscon-icst525")) {
 524                 icst_desc.params = &icst525_params;
 525                 ctype = ICST_VERSATILE;
 526         } else if (of_device_is_compatible(np, "arm,syscon-icst307")) {
 527                 icst_desc.params = &icst307_params;
 528                 ctype = ICST_VERSATILE;
 529         } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) {
 530                 icst_desc.params = &icst525_apcp_cm_params;
 531                 ctype = ICST_INTEGRATOR_AP_CM;
 532         } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) {
 533                 icst_desc.params = &icst525_ap_sys_params;
 534                 ctype = ICST_INTEGRATOR_AP_SYS;
 535         } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) {
 536                 icst_desc.params = &icst525_ap_pci_params;
 537                 ctype = ICST_INTEGRATOR_AP_PCI;
 538         } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) {
 539                 icst_desc.params = &icst525_apcp_cm_params;
 540                 ctype = ICST_INTEGRATOR_CP_CM_CORE;
 541         } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) {
 542                 icst_desc.params = &icst525_apcp_cm_params;
 543                 ctype = ICST_INTEGRATOR_CP_CM_MEM;
 544         } else {
 545                 pr_err("unknown ICST clock %s\n", name);
 546                 return;
 547         }
 548 
 549         /* Parent clock name is not the same as node parent */
 550         parent_name = of_clk_get_parent_name(np, 0);
 551 
 552         regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype);
 553         if (IS_ERR(regclk)) {
 554                 pr_err("error setting up syscon ICST clock %s\n", name);
 555                 return;
 556         }
 557         of_clk_add_provider(np, of_clk_src_simple_get, regclk);
 558         pr_debug("registered syscon ICST clock %s\n", name);
 559 }
 560 
 561 CLK_OF_DECLARE(arm_syscon_icst525_clk,
 562                "arm,syscon-icst525", of_syscon_icst_setup);
 563 CLK_OF_DECLARE(arm_syscon_icst307_clk,
 564                "arm,syscon-icst307", of_syscon_icst_setup);
 565 CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk,
 566                "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup);
 567 CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk,
 568                "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup);
 569 CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk,
 570                "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup);
 571 CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk,
 572                "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup);
 573 CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,
 574                "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup);
 575 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/clk/versatile/clk-icst.c

DEFINITIONS
