root/drivers/clk/clk-vt8500.c

DEFINITIONS

1. vtwm_set_pmc_base
2. vt8500_pmc_wait_busy
3. vt8500_dclk_enable
4. vt8500_dclk_disable
5. vt8500_dclk_is_enabled
6. vt8500_dclk_recalc_rate
7. vt8500_dclk_round_rate
8. vt8500_dclk_set_rate
9. vtwm_device_clk_init
10. vt8500_find_pll_bits
11. wm8650_find_pll_bits
12. wm8750_get_filter
13. wm8750_find_pll_bits
14. wm8850_find_pll_bits
15. vtwm_pll_set_rate
16. vtwm_pll_round_rate
17. vtwm_pll_recalc_rate
18. vtwm_pll_clk_init
19. vt8500_pll_init
20. wm8650_pll_init
21. wm8750_pll_init
22. wm8850_pll_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Clock implementation for VIA/Wondermedia SoC's
   4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  */
   6 
   7 #include <linux/io.h>
   8 #include <linux/of.h>
   9 #include <linux/of_address.h>
  10 #include <linux/slab.h>
  11 #include <linux/bitops.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk-provider.h>
  14 
  15 #define LEGACY_PMC_BASE         0xD8130000
  16 
  17 /* All clocks share the same lock as none can be changed concurrently */
  18 static DEFINE_SPINLOCK(_lock);
  19 
  20 struct clk_device {
  21         struct clk_hw   hw;
  22         void __iomem    *div_reg;
  23         unsigned int    div_mask;
  24         void __iomem    *en_reg;
  25         int             en_bit;
  26         spinlock_t      *lock;
  27 };
  28 
  29 /*
  30  * Add new PLL_TYPE_x definitions here as required. Use the first known model
  31  * to support the new type as the name.
  32  * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
  33  * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
  34  */
  35 
  36 #define PLL_TYPE_VT8500         0
  37 #define PLL_TYPE_WM8650         1
  38 #define PLL_TYPE_WM8750         2
  39 #define PLL_TYPE_WM8850         3
  40 
  41 struct clk_pll {
  42         struct clk_hw   hw;
  43         void __iomem    *reg;
  44         spinlock_t      *lock;
  45         int             type;
  46 };
  47 
  48 static void __iomem *pmc_base;
  49 
  50 static __init void vtwm_set_pmc_base(void)
  51 {
  52         struct device_node *np =
  53                 of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
  54 
  55         if (np)
  56                 pmc_base = of_iomap(np, 0);
  57         else
  58                 pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
  59         of_node_put(np);
  60 
  61         if (!pmc_base)
  62                 pr_err("%s:of_iomap(pmc) failed\n", __func__);
  63 }
  64 
  65 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
  66 
  67 #define VT8500_PMC_BUSY_MASK            0x18
  68 
  69 static void vt8500_pmc_wait_busy(void)
  70 {
  71         while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
  72                 cpu_relax();
  73 }
  74 
  75 static int vt8500_dclk_enable(struct clk_hw *hw)
  76 {
  77         struct clk_device *cdev = to_clk_device(hw);
  78         u32 en_val;
  79         unsigned long flags = 0;
  80 
  81         spin_lock_irqsave(cdev->lock, flags);
  82 
  83         en_val = readl(cdev->en_reg);
  84         en_val |= BIT(cdev->en_bit);
  85         writel(en_val, cdev->en_reg);
  86 
  87         spin_unlock_irqrestore(cdev->lock, flags);
  88         return 0;
  89 }
  90 
  91 static void vt8500_dclk_disable(struct clk_hw *hw)
  92 {
  93         struct clk_device *cdev = to_clk_device(hw);
  94         u32 en_val;
  95         unsigned long flags = 0;
  96 
  97         spin_lock_irqsave(cdev->lock, flags);
  98 
  99         en_val = readl(cdev->en_reg);
 100         en_val &= ~BIT(cdev->en_bit);
 101         writel(en_val, cdev->en_reg);
 102 
 103         spin_unlock_irqrestore(cdev->lock, flags);
 104 }
 105 
 106 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
 107 {
 108         struct clk_device *cdev = to_clk_device(hw);
 109         u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
 110 
 111         return en_val ? 1 : 0;
 112 }
 113 
 114 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
 115                                 unsigned long parent_rate)
 116 {
 117         struct clk_device *cdev = to_clk_device(hw);
 118         u32 div = readl(cdev->div_reg) & cdev->div_mask;
 119 
 120         /* Special case for SDMMC devices */
 121         if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
 122                 div = 64 * (div & 0x1f);
 123 
 124         /* div == 0 is actually the highest divisor */
 125         if (div == 0)
 126                 div = (cdev->div_mask + 1);
 127 
 128         return parent_rate / div;
 129 }
 130 
 131 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
 132                                 unsigned long *prate)
 133 {
 134         struct clk_device *cdev = to_clk_device(hw);
 135         u32 divisor;
 136 
 137         if (rate == 0)
 138                 return 0;
 139 
 140         divisor = *prate / rate;
 141 
 142         /* If prate / rate would be decimal, incr the divisor */
 143         if (rate * divisor < *prate)
 144                 divisor++;
 145 
 146         /*
 147          * If this is a request for SDMMC we have to adjust the divisor
 148          * when >31 to use the fixed predivisor
 149          */
 150         if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
 151                 divisor = 64 * ((divisor / 64) + 1);
 152         }
 153 
 154         return *prate / divisor;
 155 }
 156 
 157 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 158                                 unsigned long parent_rate)
 159 {
 160         struct clk_device *cdev = to_clk_device(hw);
 161         u32 divisor;
 162         unsigned long flags = 0;
 163 
 164         if (rate == 0)
 165                 return 0;
 166 
 167         divisor =  parent_rate / rate;
 168 
 169         if (divisor == cdev->div_mask + 1)
 170                 divisor = 0;
 171 
 172         /* SDMMC mask may need to be corrected before testing if its valid */
 173         if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
 174                 /*
 175                  * Bit 5 is a fixed /64 predivisor. If the requested divisor
 176                  * is >31 then correct for the fixed divisor being required.
 177                  */
 178                 divisor = 0x20 + (divisor / 64);
 179         }
 180 
 181         if (divisor > cdev->div_mask) {
 182                 pr_err("%s: invalid divisor for clock\n", __func__);
 183                 return -EINVAL;
 184         }
 185 
 186         spin_lock_irqsave(cdev->lock, flags);
 187 
 188         vt8500_pmc_wait_busy();
 189         writel(divisor, cdev->div_reg);
 190         vt8500_pmc_wait_busy();
 191 
 192         spin_unlock_irqrestore(cdev->lock, flags);
 193 
 194         return 0;
 195 }
 196 
 197 
 198 static const struct clk_ops vt8500_gated_clk_ops = {
 199         .enable = vt8500_dclk_enable,
 200         .disable = vt8500_dclk_disable,
 201         .is_enabled = vt8500_dclk_is_enabled,
 202 };
 203 
 204 static const struct clk_ops vt8500_divisor_clk_ops = {
 205         .round_rate = vt8500_dclk_round_rate,
 206         .set_rate = vt8500_dclk_set_rate,
 207         .recalc_rate = vt8500_dclk_recalc_rate,
 208 };
 209 
 210 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
 211         .enable = vt8500_dclk_enable,
 212         .disable = vt8500_dclk_disable,
 213         .is_enabled = vt8500_dclk_is_enabled,
 214         .round_rate = vt8500_dclk_round_rate,
 215         .set_rate = vt8500_dclk_set_rate,
 216         .recalc_rate = vt8500_dclk_recalc_rate,
 217 };
 218 
 219 #define CLK_INIT_GATED                  BIT(0)
 220 #define CLK_INIT_DIVISOR                BIT(1)
 221 #define CLK_INIT_GATED_DIVISOR          (CLK_INIT_DIVISOR | CLK_INIT_GATED)
 222 
 223 static __init void vtwm_device_clk_init(struct device_node *node)
 224 {
 225         u32 en_reg, div_reg;
 226         struct clk_hw *hw;
 227         struct clk_device *dev_clk;
 228         const char *clk_name = node->name;
 229         const char *parent_name;
 230         struct clk_init_data init;
 231         int rc;
 232         int clk_init_flags = 0;
 233 
 234         if (!pmc_base)
 235                 vtwm_set_pmc_base();
 236 
 237         dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
 238         if (WARN_ON(!dev_clk))
 239                 return;
 240 
 241         dev_clk->lock = &_lock;
 242 
 243         rc = of_property_read_u32(node, "enable-reg", &en_reg);
 244         if (!rc) {
 245                 dev_clk->en_reg = pmc_base + en_reg;
 246                 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
 247                 if (rc) {
 248                         pr_err("%s: enable-bit property required for gated clock\n",
 249                                                                 __func__);
 250                         return;
 251                 }
 252                 clk_init_flags |= CLK_INIT_GATED;
 253         }
 254 
 255         rc = of_property_read_u32(node, "divisor-reg", &div_reg);
 256         if (!rc) {
 257                 dev_clk->div_reg = pmc_base + div_reg;
 258                 /*
 259                  * use 0x1f as the default mask since it covers
 260                  * almost all the clocks and reduces dts properties
 261                  */
 262                 dev_clk->div_mask = 0x1f;
 263 
 264                 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
 265                 clk_init_flags |= CLK_INIT_DIVISOR;
 266         }
 267 
 268         of_property_read_string(node, "clock-output-names", &clk_name);
 269 
 270         switch (clk_init_flags) {
 271         case CLK_INIT_GATED:
 272                 init.ops = &vt8500_gated_clk_ops;
 273                 break;
 274         case CLK_INIT_DIVISOR:
 275                 init.ops = &vt8500_divisor_clk_ops;
 276                 break;
 277         case CLK_INIT_GATED_DIVISOR:
 278                 init.ops = &vt8500_gated_divisor_clk_ops;
 279                 break;
 280         default:
 281                 pr_err("%s: Invalid clock description in device tree\n",
 282                                                                 __func__);
 283                 kfree(dev_clk);
 284                 return;
 285         }
 286 
 287         init.name = clk_name;
 288         init.flags = 0;
 289         parent_name = of_clk_get_parent_name(node, 0);
 290         init.parent_names = &parent_name;
 291         init.num_parents = 1;
 292 
 293         dev_clk->hw.init = &init;
 294 
 295         hw = &dev_clk->hw;
 296         rc = clk_hw_register(NULL, hw);
 297         if (WARN_ON(rc)) {
 298                 kfree(dev_clk);
 299                 return;
 300         }
 301         rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
 302         clk_hw_register_clkdev(hw, clk_name, NULL);
 303 }
 304 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
 305 
 306 /* PLL clock related functions */
 307 
 308 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
 309 
 310 /* Helper macros for PLL_VT8500 */
 311 #define VT8500_PLL_MUL(x)       ((x & 0x1F) << 1)
 312 #define VT8500_PLL_DIV(x)       ((x & 0x100) ? 1 : 2)
 313 
 314 #define VT8500_BITS_TO_FREQ(r, m, d)                                    \
 315                                 ((r / d) * m)
 316 
 317 #define VT8500_BITS_TO_VAL(m, d)                                        \
 318                                 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
 319 
 320 /* Helper macros for PLL_WM8650 */
 321 #define WM8650_PLL_MUL(x)       (x & 0x3FF)
 322 #define WM8650_PLL_DIV(x)       (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
 323 
 324 #define WM8650_BITS_TO_FREQ(r, m, d1, d2)                               \
 325                                 (r * m / (d1 * (1 << d2)))
 326 
 327 #define WM8650_BITS_TO_VAL(m, d1, d2)                                   \
 328                                 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
 329 
 330 /* Helper macros for PLL_WM8750 */
 331 #define WM8750_PLL_MUL(x)       (((x >> 16) & 0xFF) + 1)
 332 #define WM8750_PLL_DIV(x)       ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
 333 
 334 #define WM8750_BITS_TO_FREQ(r, m, d1, d2)                               \
 335                                 (r * (m+1) / ((d1+1) * (1 << d2)))
 336 
 337 #define WM8750_BITS_TO_VAL(f, m, d1, d2)                                \
 338                 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
 339 
 340 /* Helper macros for PLL_WM8850 */
 341 #define WM8850_PLL_MUL(x)       ((((x >> 16) & 0x7F) + 1) * 2)
 342 #define WM8850_PLL_DIV(x)       ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
 343 
 344 #define WM8850_BITS_TO_FREQ(r, m, d1, d2)                               \
 345                                 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
 346 
 347 #define WM8850_BITS_TO_VAL(m, d1, d2)                                   \
 348                 ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
 349 
 350 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 351                                 u32 *multiplier, u32 *prediv)
 352 {
 353         unsigned long tclk;
 354 
 355         /* sanity check */
 356         if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
 357                 pr_err("%s: requested rate out of range\n", __func__);
 358                 *multiplier = 0;
 359                 *prediv = 1;
 360                 return -EINVAL;
 361         }
 362         if (rate <= parent_rate * 31)
 363                 /* use the prediv to double the resolution */
 364                 *prediv = 2;
 365         else
 366                 *prediv = 1;
 367 
 368         *multiplier = rate / (parent_rate / *prediv);
 369         tclk = (parent_rate / *prediv) * *multiplier;
 370 
 371         if (tclk != rate)
 372                 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
 373                                                                 rate, tclk);
 374 
 375         return 0;
 376 }
 377 
 378 /*
 379  * M * parent [O1] => / P [O2] => / D [O3]
 380  * Where O1 is 900MHz...3GHz;
 381  * O2 is 600MHz >= (M * parent) / P >= 300MHz;
 382  * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
 383  * Possible ranges (O3):
 384  * D = 8: 37,5MHz...75MHz
 385  * D = 4: 75MHz...150MHz
 386  * D = 2: 150MHz...300MHz
 387  * D = 1: 300MHz...600MHz
 388  */
 389 static int wm8650_find_pll_bits(unsigned long rate,
 390         unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
 391         u32 *divisor2)
 392 {
 393         unsigned long O1, min_err, rate_err;
 394 
 395         if (!parent_rate || (rate < 37500000) || (rate > 600000000))
 396                 return -EINVAL;
 397 
 398         *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
 399                                            rate <= 300000000 ? 1 : 0;
 400         /*
 401          * Divisor P cannot be calculated. Test all divisors and find where M
 402          * will be as close as possible to the requested rate.
 403          */
 404         min_err = ULONG_MAX;
 405         for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
 406                 O1 = rate * *divisor1 * (1 << (*divisor2));
 407                 rate_err = O1 % parent_rate;
 408                 if (rate_err < min_err) {
 409                         *multiplier = O1 / parent_rate;
 410                         if (rate_err == 0)
 411                                 return 0;
 412 
 413                         min_err = rate_err;
 414                 }
 415         }
 416 
 417         if ((*multiplier < 3) || (*multiplier > 1023))
 418                 return -EINVAL;
 419 
 420         pr_warn("%s: rate error is %lu\n", __func__, min_err);
 421 
 422         return 0;
 423 }
 424 
 425 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
 426 {
 427         /* calculate frequency (MHz) after pre-divisor */
 428         u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
 429 
 430         if ((freq < 10) || (freq > 200))
 431                 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
 432                                 __func__, freq);
 433 
 434         if (freq >= 166)
 435                 return 7;
 436         else if (freq >= 104)
 437                 return 6;
 438         else if (freq >= 65)
 439                 return 5;
 440         else if (freq >= 42)
 441                 return 4;
 442         else if (freq >= 26)
 443                 return 3;
 444         else if (freq >= 16)
 445                 return 2;
 446         else if (freq >= 10)
 447                 return 1;
 448 
 449         return 0;
 450 }
 451 
 452 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 453                                 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
 454 {
 455         u32 mul;
 456         int div1, div2;
 457         unsigned long tclk, rate_err, best_err;
 458 
 459         best_err = (unsigned long)-1;
 460 
 461         /* Find the closest match (lower or equal to requested) */
 462         for (div1 = 1; div1 >= 0; div1--)
 463                 for (div2 = 7; div2 >= 0; div2--)
 464                         for (mul = 0; mul <= 255; mul++) {
 465                                 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
 466                                 if (tclk > rate)
 467                                         continue;
 468                                 /* error will always be +ve */
 469                                 rate_err = rate - tclk;
 470                                 if (rate_err == 0) {
 471                                         *filter = wm8750_get_filter(parent_rate, div1);
 472                                         *multiplier = mul;
 473                                         *divisor1 = div1;
 474                                         *divisor2 = div2;
 475                                         return 0;
 476                                 }
 477 
 478                                 if (rate_err < best_err) {
 479                                         best_err = rate_err;
 480                                         *multiplier = mul;
 481                                         *divisor1 = div1;
 482                                         *divisor2 = div2;
 483                                 }
 484                         }
 485 
 486         if (best_err == (unsigned long)-1) {
 487                 pr_warn("%s: impossible rate %lu\n", __func__, rate);
 488                 return -EINVAL;
 489         }
 490 
 491         /* if we got here, it wasn't an exact match */
 492         pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 493                                                         rate - best_err);
 494 
 495         *filter = wm8750_get_filter(parent_rate, *divisor1);
 496 
 497         return 0;
 498 }
 499 
 500 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 501                                 u32 *multiplier, u32 *divisor1, u32 *divisor2)
 502 {
 503         u32 mul;
 504         int div1, div2;
 505         unsigned long tclk, rate_err, best_err;
 506 
 507         best_err = (unsigned long)-1;
 508 
 509         /* Find the closest match (lower or equal to requested) */
 510         for (div1 = 1; div1 >= 0; div1--)
 511                 for (div2 = 3; div2 >= 0; div2--)
 512                         for (mul = 0; mul <= 127; mul++) {
 513                                 tclk = parent_rate * ((mul + 1) * 2) /
 514                                                 ((div1 + 1) * (1 << div2));
 515                                 if (tclk > rate)
 516                                         continue;
 517                                 /* error will always be +ve */
 518                                 rate_err = rate - tclk;
 519                                 if (rate_err == 0) {
 520                                         *multiplier = mul;
 521                                         *divisor1 = div1;
 522                                         *divisor2 = div2;
 523                                         return 0;
 524                                 }
 525 
 526                                 if (rate_err < best_err) {
 527                                         best_err = rate_err;
 528                                         *multiplier = mul;
 529                                         *divisor1 = div1;
 530                                         *divisor2 = div2;
 531                                 }
 532                         }
 533 
 534         if (best_err == (unsigned long)-1) {
 535                 pr_warn("%s: impossible rate %lu\n", __func__, rate);
 536                 return -EINVAL;
 537         }
 538 
 539         /* if we got here, it wasn't an exact match */
 540         pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 541                                                         rate - best_err);
 542 
 543         return 0;
 544 }
 545 
 546 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 547                                 unsigned long parent_rate)
 548 {
 549         struct clk_pll *pll = to_clk_pll(hw);
 550         u32 filter, mul, div1, div2;
 551         u32 pll_val;
 552         unsigned long flags = 0;
 553         int ret;
 554 
 555         /* sanity check */
 556 
 557         switch (pll->type) {
 558         case PLL_TYPE_VT8500:
 559                 ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
 560                 if (!ret)
 561                         pll_val = VT8500_BITS_TO_VAL(mul, div1);
 562                 break;
 563         case PLL_TYPE_WM8650:
 564                 ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
 565                 if (!ret)
 566                         pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
 567                 break;
 568         case PLL_TYPE_WM8750:
 569                 ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
 570                 if (!ret)
 571                         pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
 572                 break;
 573         case PLL_TYPE_WM8850:
 574                 ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
 575                 if (!ret)
 576                         pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
 577                 break;
 578         default:
 579                 pr_err("%s: invalid pll type\n", __func__);
 580                 ret = -EINVAL;
 581         }
 582 
 583         if (ret)
 584                 return ret;
 585 
 586         spin_lock_irqsave(pll->lock, flags);
 587 
 588         vt8500_pmc_wait_busy();
 589         writel(pll_val, pll->reg);
 590         vt8500_pmc_wait_busy();
 591 
 592         spin_unlock_irqrestore(pll->lock, flags);
 593 
 594         return 0;
 595 }
 596 
 597 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 598                                 unsigned long *prate)
 599 {
 600         struct clk_pll *pll = to_clk_pll(hw);
 601         u32 filter, mul, div1, div2;
 602         long round_rate;
 603         int ret;
 604 
 605         switch (pll->type) {
 606         case PLL_TYPE_VT8500:
 607                 ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1);
 608                 if (!ret)
 609                         round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
 610                 break;
 611         case PLL_TYPE_WM8650:
 612                 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
 613                 if (!ret)
 614                         round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
 615                 break;
 616         case PLL_TYPE_WM8750:
 617                 ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
 618                 if (!ret)
 619                         round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
 620                 break;
 621         case PLL_TYPE_WM8850:
 622                 ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
 623                 if (!ret)
 624                         round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
 625                 break;
 626         default:
 627                 ret = -EINVAL;
 628         }
 629 
 630         if (ret)
 631                 return ret;
 632 
 633         return round_rate;
 634 }
 635 
 636 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
 637                                 unsigned long parent_rate)
 638 {
 639         struct clk_pll *pll = to_clk_pll(hw);
 640         u32 pll_val = readl(pll->reg);
 641         unsigned long pll_freq;
 642 
 643         switch (pll->type) {
 644         case PLL_TYPE_VT8500:
 645                 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
 646                 pll_freq /= VT8500_PLL_DIV(pll_val);
 647                 break;
 648         case PLL_TYPE_WM8650:
 649                 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
 650                 pll_freq /= WM8650_PLL_DIV(pll_val);
 651                 break;
 652         case PLL_TYPE_WM8750:
 653                 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
 654                 pll_freq /= WM8750_PLL_DIV(pll_val);
 655                 break;
 656         case PLL_TYPE_WM8850:
 657                 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
 658                 pll_freq /= WM8850_PLL_DIV(pll_val);
 659                 break;
 660         default:
 661                 pll_freq = 0;
 662         }
 663 
 664         return pll_freq;
 665 }
 666 
 667 static const struct clk_ops vtwm_pll_ops = {
 668         .round_rate = vtwm_pll_round_rate,
 669         .set_rate = vtwm_pll_set_rate,
 670         .recalc_rate = vtwm_pll_recalc_rate,
 671 };
 672 
 673 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
 674 {
 675         u32 reg;
 676         struct clk_hw *hw;
 677         struct clk_pll *pll_clk;
 678         const char *clk_name = node->name;
 679         const char *parent_name;
 680         struct clk_init_data init;
 681         int rc;
 682 
 683         if (!pmc_base)
 684                 vtwm_set_pmc_base();
 685 
 686         rc = of_property_read_u32(node, "reg", &reg);
 687         if (WARN_ON(rc))
 688                 return;
 689 
 690         pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
 691         if (WARN_ON(!pll_clk))
 692                 return;
 693 
 694         pll_clk->reg = pmc_base + reg;
 695         pll_clk->lock = &_lock;
 696         pll_clk->type = pll_type;
 697 
 698         of_property_read_string(node, "clock-output-names", &clk_name);
 699 
 700         init.name = clk_name;
 701         init.ops = &vtwm_pll_ops;
 702         init.flags = 0;
 703         parent_name = of_clk_get_parent_name(node, 0);
 704         init.parent_names = &parent_name;
 705         init.num_parents = 1;
 706 
 707         pll_clk->hw.init = &init;
 708 
 709         hw = &pll_clk->hw;
 710         rc = clk_hw_register(NULL, &pll_clk->hw);
 711         if (WARN_ON(rc)) {
 712                 kfree(pll_clk);
 713                 return;
 714         }
 715         rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
 716         clk_hw_register_clkdev(hw, clk_name, NULL);
 717 }
 718 
 719 
 720 /* Wrappers for initialization functions */
 721 
 722 static void __init vt8500_pll_init(struct device_node *node)
 723 {
 724         vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
 725 }
 726 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
 727 
 728 static void __init wm8650_pll_init(struct device_node *node)
 729 {
 730         vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
 731 }
 732 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
 733 
 734 static void __init wm8750_pll_init(struct device_node *node)
 735 {
 736         vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
 737 }
 738 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
 739 
 740 static void __init wm8850_pll_init(struct device_node *node)
 741 {
 742         vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
 743 }
 744 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);