This source file includes following definitions.
- get_sdram_rows
- mdrefr_dri
- pxa27x_get_clk_frequency_khz
- pxa27x_is_ppll_disabled
- clk_pxa27x_cpll_get_rate
- clk_pxa27x_cpll_determine_rate
- clk_pxa27x_cpll_set_rate
- clk_pxa27x_lcd_base_get_rate
- clk_pxa27x_lcd_base_get_parent
- pxa27x_register_plls
- clk_pxa27x_core_get_parent
- clk_pxa27x_core_set_parent
- clk_pxa27x_core_determine_rate
- clk_pxa27x_run_get_rate
- pxa27x_register_core
- clk_pxa27x_system_bus_get_rate
- clk_pxa27x_system_bus_get_parent
- clk_pxa27x_memory_get_rate
- clk_pxa27x_memory_get_parent
- pxa27x_dummy_clocks_init
- pxa27x_base_clocks_init
- pxa27x_clocks_init
- pxa27x_dt_clocks_init
1
2
3
4
5
6
7
8
9 #include <linux/clk-provider.h>
10 #include <mach/pxa2xx-regs.h>
11 #include <linux/io.h>
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/of.h>
15
16 #include <mach/smemc.h>
17
18 #include <dt-bindings/clock/pxa-clock.h>
19 #include "clk-pxa.h"
20
21 #define KHz 1000
22 #define MHz (1000 * 1000)
23
24 enum {
25 PXA_CORE_13Mhz = 0,
26 PXA_CORE_RUN,
27 PXA_CORE_TURBO,
28 };
29
30 enum {
31 PXA_BUS_13Mhz = 0,
32 PXA_BUS_RUN,
33 };
34
35 enum {
36 PXA_LCD_13Mhz = 0,
37 PXA_LCD_RUN,
38 };
39
40 enum {
41 PXA_MEM_13Mhz = 0,
42 PXA_MEM_SYSTEM_BUS,
43 PXA_MEM_RUN,
44 };
45
46 #define PXA27x_CLKCFG(B, HT, T) \
47 (CLKCFG_FCS | \
48 ((B) ? CLKCFG_FASTBUS : 0) | \
49 ((HT) ? CLKCFG_HALFTURBO : 0) | \
50 ((T) ? CLKCFG_TURBO : 0))
51 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
52
53 #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
54 #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
55
56
57 #define SDRAM_TREF 64
58
59 static const char * const get_freq_khz[] = {
60 "core", "run", "cpll", "memory",
61 "system_bus"
62 };
63
64 static int get_sdram_rows(void)
65 {
66 static int sdram_rows;
67 unsigned int drac2 = 0, drac0 = 0;
68 u32 mdcnfg;
69
70 if (sdram_rows)
71 return sdram_rows;
72
73 mdcnfg = readl_relaxed(MDCNFG);
74
75 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
76 drac2 = MDCNFG_DRAC2(mdcnfg);
77
78 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
79 drac0 = MDCNFG_DRAC0(mdcnfg);
80
81 sdram_rows = 1 << (11 + max(drac0, drac2));
82 return sdram_rows;
83 }
84
85 static u32 mdrefr_dri(unsigned int freq_khz)
86 {
87 u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();
88
89 return (interval - 31) / 32;
90 }
91
92
93
94
95
96
97 unsigned int pxa27x_get_clk_frequency_khz(int info)
98 {
99 struct clk *clk;
100 unsigned long clks[5];
101 int i;
102
103 for (i = 0; i < 5; i++) {
104 clk = clk_get(NULL, get_freq_khz[i]);
105 if (IS_ERR(clk)) {
106 clks[i] = 0;
107 } else {
108 clks[i] = clk_get_rate(clk);
109 clk_put(clk);
110 }
111 }
112 if (info) {
113 pr_info("Run Mode clock: %ld.%02ldMHz\n",
114 clks[1] / 1000000, (clks[1] % 1000000) / 10000);
115 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
116 clks[2] / 1000000, (clks[2] % 1000000) / 10000);
117 pr_info("Memory clock: %ld.%02ldMHz\n",
118 clks[3] / 1000000, (clks[3] % 1000000) / 10000);
119 pr_info("System bus clock: %ld.%02ldMHz\n",
120 clks[4] / 1000000, (clks[4] % 1000000) / 10000);
121 }
122 return (unsigned int)clks[0] / KHz;
123 }
124
125 bool pxa27x_is_ppll_disabled(void)
126 {
127 unsigned long ccsr = readl(CCSR);
128
129 return ccsr & (1 << CCCR_PPDIS_BIT);
130 }
131
132 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
133 bit, is_lp, flags) \
134 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
135 is_lp, CKEN, CKEN_ ## bit, flags)
136 #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
137 PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
138 div_hp, bit, pxa27x_is_ppll_disabled, 0)
139
140 PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
141 PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
142 PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
143 PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
144 PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
145
146 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
147 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
148 CKEN, CKEN_ ## bit, 0)
149 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
150 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
151 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
152
153 static struct desc_clk_cken pxa27x_clocks[] __initdata = {
154 PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
155 PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
156 PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
157 PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
158 PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
159 PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
160 PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
161 PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
162 PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
163 PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
164 PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
165 PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
166 PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
167 PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
168 PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
169 PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
170 PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
171 PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
172 PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
173 PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
174 PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
175
176 PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
177 pxa27x_32Mhz_bus_parents, 0),
178 PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
179 PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
180 PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
181 pxa27x_lcd_bus_parents, 0),
182 PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
183 pxa27x_membus_parents, 0),
184
185 };
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213 static struct pxa2xx_freq pxa27x_freqs[] = {
214 {104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
215 {156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
216 {208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
217 {312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
218 {416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
219 {520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
220 {624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
221 };
222
223 static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
224 unsigned long parent_rate)
225 {
226 unsigned long clkcfg;
227 unsigned int t, ht;
228 unsigned int l, L, n2, N;
229 unsigned long ccsr = readl(CCSR);
230
231 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
232 t = clkcfg & (1 << 0);
233 ht = clkcfg & (1 << 2);
234
235 l = ccsr & CCSR_L_MASK;
236 n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
237 L = l * parent_rate;
238 N = (L * n2) / 2;
239
240 return N;
241 }
242
243 static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
244 struct clk_rate_request *req)
245 {
246 return pxa2xx_determine_rate(req, pxa27x_freqs,
247 ARRAY_SIZE(pxa27x_freqs));
248 }
249
250 static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
251 unsigned long parent_rate)
252 {
253 int i;
254
255 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
256 for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
257 if (pxa27x_freqs[i].cpll == rate)
258 break;
259
260 if (i >= ARRAY_SIZE(pxa27x_freqs))
261 return -EINVAL;
262
263 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR);
264 return 0;
265 }
266
267 PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
268 RATE_OPS(clk_pxa27x_cpll, "cpll");
269
270 static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
271 unsigned long parent_rate)
272 {
273 unsigned int l, osc_forced;
274 unsigned long ccsr = readl(CCSR);
275 unsigned long cccr = readl(CCCR);
276
277 l = ccsr & CCSR_L_MASK;
278 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
279 if (osc_forced) {
280 if (cccr & (1 << CCCR_LCD_26_BIT))
281 return parent_rate * 2;
282 else
283 return parent_rate;
284 }
285
286 if (l <= 7)
287 return parent_rate;
288 if (l <= 16)
289 return parent_rate / 2;
290 return parent_rate / 4;
291 }
292
293 static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
294 {
295 unsigned int osc_forced;
296 unsigned long ccsr = readl(CCSR);
297
298 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
299 if (osc_forced)
300 return PXA_LCD_13Mhz;
301 else
302 return PXA_LCD_RUN;
303 }
304
305 PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
306 MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
307
308 static void __init pxa27x_register_plls(void)
309 {
310 clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
311 CLK_GET_RATE_NOCACHE,
312 13 * MHz);
313 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
314 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
315 CLK_GET_RATE_NOCACHE,
316 32768 * KHz));
317 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
318 clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
319 }
320
321 static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
322 {
323 unsigned long clkcfg;
324 unsigned int t, ht, osc_forced;
325 unsigned long ccsr = readl(CCSR);
326
327 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
328 if (osc_forced)
329 return PXA_CORE_13Mhz;
330
331 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
332 t = clkcfg & (1 << 0);
333 ht = clkcfg & (1 << 2);
334
335 if (ht || t)
336 return PXA_CORE_TURBO;
337 return PXA_CORE_RUN;
338 }
339
340 static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
341 {
342 if (index > PXA_CORE_TURBO)
343 return -EINVAL;
344
345 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
346
347 return 0;
348 }
349
350 static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
351 struct clk_rate_request *req)
352 {
353 return __clk_mux_determine_rate(hw, req);
354 }
355
356 PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
357 MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
358
359 static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
360 unsigned long parent_rate)
361 {
362 unsigned long ccsr = readl(CCSR);
363 unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
364
365 return (parent_rate / n2) * 2;
366 }
367 PARENTS(clk_pxa27x_run) = { "cpll" };
368 RATE_RO_OPS(clk_pxa27x_run, "run");
369
370 static void __init pxa27x_register_core(void)
371 {
372 clkdev_pxa_register(CLK_NONE, "cpll", NULL,
373 clk_register_clk_pxa27x_cpll());
374 clkdev_pxa_register(CLK_NONE, "run", NULL,
375 clk_register_clk_pxa27x_run());
376 clkdev_pxa_register(CLK_CORE, "core", NULL,
377 clk_register_clk_pxa27x_core());
378 }
379
380 static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
381 unsigned long parent_rate)
382 {
383 unsigned long clkcfg;
384 unsigned int b, osc_forced;
385 unsigned long ccsr = readl(CCSR);
386
387 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
388 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
389 b = clkcfg & (1 << 3);
390
391 if (osc_forced)
392 return parent_rate;
393 if (b)
394 return parent_rate;
395 else
396 return parent_rate / 2;
397 }
398
399 static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
400 {
401 unsigned int osc_forced;
402 unsigned long ccsr = readl(CCSR);
403
404 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
405 if (osc_forced)
406 return PXA_BUS_13Mhz;
407 else
408 return PXA_BUS_RUN;
409 }
410
411 PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
412 MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
413
414 static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
415 unsigned long parent_rate)
416 {
417 unsigned int a, l, osc_forced;
418 unsigned long cccr = readl(CCCR);
419 unsigned long ccsr = readl(CCSR);
420
421 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
422 a = cccr & (1 << CCCR_A_BIT);
423 l = ccsr & CCSR_L_MASK;
424
425 if (osc_forced || a)
426 return parent_rate;
427 if (l <= 10)
428 return parent_rate;
429 if (l <= 20)
430 return parent_rate / 2;
431 return parent_rate / 4;
432 }
433
434 static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
435 {
436 unsigned int osc_forced, a;
437 unsigned long cccr = readl(CCCR);
438 unsigned long ccsr = readl(CCSR);
439
440 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
441 a = cccr & (1 << CCCR_A_BIT);
442 if (osc_forced)
443 return PXA_MEM_13Mhz;
444 if (a)
445 return PXA_MEM_SYSTEM_BUS;
446 else
447 return PXA_MEM_RUN;
448 }
449
450 PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
451 MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
452
453 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
454 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
455 struct dummy_clk {
456 const char *con_id;
457 const char *dev_id;
458 const char *parent;
459 };
460 static struct dummy_clk dummy_clks[] __initdata = {
461 DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
462 DUMMY_CLK(NULL, "pxa-rtc", "osc_32_768khz"),
463 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
464 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
465 };
466
467 static void __init pxa27x_dummy_clocks_init(void)
468 {
469 struct clk *clk;
470 struct dummy_clk *d;
471 const char *name;
472 int i;
473
474 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
475 d = &dummy_clks[i];
476 name = d->dev_id ? d->dev_id : d->con_id;
477 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
478 clk_register_clkdev(clk, d->con_id, d->dev_id);
479 }
480 }
481
482 static void __init pxa27x_base_clocks_init(void)
483 {
484 pxa27x_register_plls();
485 pxa27x_register_core();
486 clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
487 clk_register_clk_pxa27x_system_bus());
488 clkdev_pxa_register(CLK_NONE, "memory", NULL,
489 clk_register_clk_pxa27x_memory());
490 clk_register_clk_pxa27x_lcd_base();
491 }
492
493 int __init pxa27x_clocks_init(void)
494 {
495 pxa27x_base_clocks_init();
496 pxa27x_dummy_clocks_init();
497 return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
498 }
499
500 static void __init pxa27x_dt_clocks_init(struct device_node *np)
501 {
502 pxa27x_clocks_init();
503 clk_pxa_dt_common_init(np);
504 }
505 CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);