root/drivers/clk/sunxi-ng/ccu-sun8i-r40.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5 
   6 #ifndef _CCU_SUN8I_R40_H_
   7 #define _CCU_SUN8I_R40_H_
   8 
   9 #include <dt-bindings/clock/sun8i-r40-ccu.h>
  10 #include <dt-bindings/reset/sun8i-r40-ccu.h>
  11 
  12 #define CLK_OSC_12M             0
  13 #define CLK_PLL_CPU             1
  14 #define CLK_PLL_AUDIO_BASE      2
  15 #define CLK_PLL_AUDIO           3
  16 #define CLK_PLL_AUDIO_2X        4
  17 #define CLK_PLL_AUDIO_4X        5
  18 #define CLK_PLL_AUDIO_8X        6
  19 
  20 /* PLL_VIDEO0 is exported */
  21 
  22 #define CLK_PLL_VIDEO0_2X       8
  23 #define CLK_PLL_VE              9
  24 #define CLK_PLL_DDR0            10
  25 #define CLK_PLL_PERIPH0         11
  26 #define CLK_PLL_PERIPH0_SATA    12
  27 #define CLK_PLL_PERIPH0_2X      13
  28 #define CLK_PLL_PERIPH1         14
  29 #define CLK_PLL_PERIPH1_2X      15
  30 
  31 /* PLL_VIDEO1 is exported */
  32 
  33 #define CLK_PLL_VIDEO1_2X       17
  34 #define CLK_PLL_SATA            18
  35 #define CLK_PLL_SATA_OUT        19
  36 #define CLK_PLL_GPU             20
  37 #define CLK_PLL_MIPI            21
  38 #define CLK_PLL_DE              22
  39 #define CLK_PLL_DDR1            23
  40 
  41 /* The CPU clock is exported */
  42 
  43 #define CLK_AXI                 25
  44 #define CLK_AHB1                26
  45 #define CLK_APB1                27
  46 #define CLK_APB2                28
  47 
  48 /* All the bus gates are exported */
  49 
  50 /* The first bunch of module clocks are exported */
  51 
  52 #define CLK_DRAM                132
  53 
  54 /* All the DRAM gates are exported */
  55 
  56 /* Some more module clocks are exported */
  57 
  58 #define CLK_MBUS                155
  59 
  60 /* Another bunch of module clocks are exported */
  61 
  62 #define CLK_NUMBER              (CLK_OUTB + 1)
  63 
  64 #endif /* _CCU_SUN8I_R40_H_ */