root/drivers/bcma/driver_chipcommon_pmu.c

DEFINITIONS

1. bcma_chipco_pll_read
2. bcma_chipco_pll_write
3. bcma_chipco_pll_maskset
4. bcma_chipco_chipctl_maskset
5. bcma_chipco_regctl_maskset
6. bcma_pmu_xtalfreq
7. bcma_pmu2_pll_init0
8. bcma_pmu_pll_init
9. bcma_pmu_resources_init
10. bcma_chipco_bcm4331_ext_pa_lines_ctl
11. bcma_pmu_workarounds
12. bcma_pmu_early_init
13. bcma_pmu_init
14. bcma_pmu_get_alp_clock
15. bcma_pmu_pll_clock
16. bcma_pmu_pll_clock_bcm4706
17. bcma_pmu_get_bus_clock
18. bcma_pmu_get_cpu_clock
19. bcma_pmu_spuravoid_pll_write
20. bcma_pmu_spuravoid_pllupdate

   1 /*
   2  * Broadcom specific AMBA
   3  * ChipCommon Power Management Unit driver
   4  *
   5  * Copyright 2009, Michael Buesch <m@bues.ch>
   6  * Copyright 2007, 2011, Broadcom Corporation
   7  * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
   8  *
   9  * Licensed under the GNU/GPL. See COPYING for details.
  10  */
  11 
  12 #include "bcma_private.h"
  13 #include <linux/export.h>
  14 #include <linux/bcma/bcma.h>
  15 
  16 u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
  17 {
  18         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  19         bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  20         return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
  21 }
  22 EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
  23 
  24 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
  25 {
  26         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  27         bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  28         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
  29 }
  30 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
  31 
  32 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  33                              u32 set)
  34 {
  35         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  36         bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  37         bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
  38 }
  39 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
  40 
  41 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  42                                  u32 offset, u32 mask, u32 set)
  43 {
  44         bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
  45         bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
  46         bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
  47 }
  48 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
  49 
  50 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  51                                 u32 set)
  52 {
  53         bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
  54         bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
  55         bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
  56 }
  57 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
  58 
  59 static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
  60 {
  61         u32 ilp_ctl, alp_hz;
  62 
  63         if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
  64               BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
  65                 return 0;
  66 
  67         bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
  68                          BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
  69         usleep_range(1000, 2000);
  70 
  71         ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
  72         ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
  73 
  74         bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
  75 
  76         alp_hz = ilp_ctl * 32768 / 4;
  77         return (alp_hz + 50000) / 100000 * 100;
  78 }
  79 
  80 static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
  81 {
  82         struct bcma_bus *bus = cc->core->bus;
  83         u32 freq_tgt_target = 0, freq_tgt_current;
  84         u32 pll0, mask;
  85 
  86         switch (bus->chipinfo.id) {
  87         case BCMA_CHIP_ID_BCM43142:
  88                 /* pmu2_xtaltab0_adfll_485 */
  89                 switch (xtalfreq) {
  90                 case 12000:
  91                         freq_tgt_target = 0x50D52;
  92                         break;
  93                 case 20000:
  94                         freq_tgt_target = 0x307FE;
  95                         break;
  96                 case 26000:
  97                         freq_tgt_target = 0x254EA;
  98                         break;
  99                 case 37400:
 100                         freq_tgt_target = 0x19EF8;
 101                         break;
 102                 case 52000:
 103                         freq_tgt_target = 0x12A75;
 104                         break;
 105                 }
 106                 break;
 107         }
 108 
 109         if (!freq_tgt_target) {
 110                 bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
 111                          xtalfreq);
 112                 return;
 113         }
 114 
 115         pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
 116         freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
 117                 BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
 118 
 119         if (freq_tgt_current == freq_tgt_target) {
 120                 bcma_debug(bus, "Target TGT frequency already set\n");
 121                 return;
 122         }
 123 
 124         /* Turn off PLL */
 125         switch (bus->chipinfo.id) {
 126         case BCMA_CHIP_ID_BCM43142:
 127                 mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
 128                               BCMA_RES_4314_MACPHY_CLK_AVAIL);
 129 
 130                 bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
 131                 bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
 132                 bcma_wait_value(cc->core, BCMA_CLKCTLST,
 133                                 BCMA_CLKCTLST_HAVEHT, 0, 20000);
 134                 break;
 135         }
 136 
 137         pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
 138         pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
 139         bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
 140 
 141         /* Flush */
 142         if (cc->pmu.rev >= 2)
 143                 bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
 144 
 145         /* TODO: Do we need to update OTP? */
 146 }
 147 
 148 static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
 149 {
 150         struct bcma_bus *bus = cc->core->bus;
 151         u32 xtalfreq = bcma_pmu_xtalfreq(cc);
 152 
 153         switch (bus->chipinfo.id) {
 154         case BCMA_CHIP_ID_BCM43142:
 155                 if (xtalfreq == 0)
 156                         xtalfreq = 20000;
 157                 bcma_pmu2_pll_init0(cc, xtalfreq);
 158                 break;
 159         }
 160 }
 161 
 162 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
 163 {
 164         struct bcma_bus *bus = cc->core->bus;
 165         u32 min_msk = 0, max_msk = 0;
 166 
 167         switch (bus->chipinfo.id) {
 168         case BCMA_CHIP_ID_BCM4313:
 169                 min_msk = 0x200D;
 170                 max_msk = 0xFFFF;
 171                 break;
 172         case BCMA_CHIP_ID_BCM43142:
 173                 min_msk = BCMA_RES_4314_LPLDO_PU |
 174                           BCMA_RES_4314_PMU_SLEEP_DIS |
 175                           BCMA_RES_4314_PMU_BG_PU |
 176                           BCMA_RES_4314_CBUCK_LPOM_PU |
 177                           BCMA_RES_4314_CBUCK_PFM_PU |
 178                           BCMA_RES_4314_CLDO_PU |
 179                           BCMA_RES_4314_LPLDO2_LVM |
 180                           BCMA_RES_4314_WL_PMU_PU |
 181                           BCMA_RES_4314_LDO3P3_PU |
 182                           BCMA_RES_4314_OTP_PU |
 183                           BCMA_RES_4314_WL_PWRSW_PU |
 184                           BCMA_RES_4314_LQ_AVAIL |
 185                           BCMA_RES_4314_LOGIC_RET |
 186                           BCMA_RES_4314_MEM_SLEEP |
 187                           BCMA_RES_4314_MACPHY_RET |
 188                           BCMA_RES_4314_WL_CORE_READY;
 189                 max_msk = 0x3FFFFFFF;
 190                 break;
 191         default:
 192                 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
 193                            bus->chipinfo.id);
 194         }
 195 
 196         /* Set the resource masks. */
 197         if (min_msk)
 198                 bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
 199         if (max_msk)
 200                 bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
 201 
 202         /*
 203          * Add some delay; allow resources to come up and settle.
 204          * Delay is required for SoC (early init).
 205          */
 206         usleep_range(2000, 2500);
 207 }
 208 
 209 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
 210 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
 211 {
 212         struct bcma_bus *bus = cc->core->bus;
 213         u32 val;
 214 
 215         val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
 216         if (enable) {
 217                 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
 218                 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
 219                         val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 220                 else if (bus->chipinfo.rev > 0)
 221                         val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
 222         } else {
 223                 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
 224                 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
 225                 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 226         }
 227         bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
 228 }
 229 
 230 static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
 231 {
 232         struct bcma_bus *bus = cc->core->bus;
 233 
 234         switch (bus->chipinfo.id) {
 235         case BCMA_CHIP_ID_BCM4313:
 236                 /* enable 12 mA drive strenth for 4313 and set chipControl
 237                    register bit 1 */
 238                 bcma_chipco_chipctl_maskset(cc, 0,
 239                                             ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
 240                                             BCMA_CCTRL_4313_12MA_LED_DRIVE);
 241                 break;
 242         case BCMA_CHIP_ID_BCM4331:
 243         case BCMA_CHIP_ID_BCM43431:
 244                 /* Ext PA lines must be enabled for tx on BCM4331 */
 245                 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
 246                 break;
 247         case BCMA_CHIP_ID_BCM43224:
 248         case BCMA_CHIP_ID_BCM43421:
 249                 /* enable 12 mA drive strenth for 43224 and set chipControl
 250                    register bit 15 */
 251                 if (bus->chipinfo.rev == 0) {
 252                         bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
 253                                           ~BCMA_CCTRL_43224_GPIO_TOGGLE,
 254                                           BCMA_CCTRL_43224_GPIO_TOGGLE);
 255                         bcma_chipco_chipctl_maskset(cc, 0,
 256                                                     ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
 257                                                     BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
 258                 } else {
 259                         bcma_chipco_chipctl_maskset(cc, 0,
 260                                                     ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
 261                                                     BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
 262                 }
 263                 break;
 264         default:
 265                 bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
 266                            bus->chipinfo.id);
 267         }
 268 }
 269 
 270 void bcma_pmu_early_init(struct bcma_drv_cc *cc)
 271 {
 272         struct bcma_bus *bus = cc->core->bus;
 273         u32 pmucap;
 274 
 275         if (cc->core->id.rev >= 35 &&
 276             cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
 277                 cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
 278                 if (!cc->pmu.core)
 279                         bcma_warn(bus, "Couldn't find expected PMU core");
 280         }
 281         if (!cc->pmu.core)
 282                 cc->pmu.core = cc->core;
 283 
 284         pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
 285         cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
 286 
 287         bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
 288                    pmucap);
 289 }
 290 
 291 void bcma_pmu_init(struct bcma_drv_cc *cc)
 292 {
 293         if (cc->pmu.rev == 1)
 294                 bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
 295                                 ~BCMA_CC_PMU_CTL_NOILPONW);
 296         else
 297                 bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
 298                                BCMA_CC_PMU_CTL_NOILPONW);
 299 
 300         bcma_pmu_pll_init(cc);
 301         bcma_pmu_resources_init(cc);
 302         bcma_pmu_workarounds(cc);
 303 }
 304 
 305 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
 306 {
 307         struct bcma_bus *bus = cc->core->bus;
 308 
 309         switch (bus->chipinfo.id) {
 310         case BCMA_CHIP_ID_BCM4313:
 311         case BCMA_CHIP_ID_BCM43224:
 312         case BCMA_CHIP_ID_BCM43225:
 313         case BCMA_CHIP_ID_BCM43227:
 314         case BCMA_CHIP_ID_BCM43228:
 315         case BCMA_CHIP_ID_BCM4331:
 316         case BCMA_CHIP_ID_BCM43421:
 317         case BCMA_CHIP_ID_BCM43428:
 318         case BCMA_CHIP_ID_BCM43431:
 319         case BCMA_CHIP_ID_BCM4716:
 320         case BCMA_CHIP_ID_BCM47162:
 321         case BCMA_CHIP_ID_BCM4748:
 322         case BCMA_CHIP_ID_BCM4749:
 323         case BCMA_CHIP_ID_BCM5357:
 324         case BCMA_CHIP_ID_BCM53572:
 325         case BCMA_CHIP_ID_BCM6362:
 326                 /* always 20Mhz */
 327                 return 20000 * 1000;
 328         case BCMA_CHIP_ID_BCM4706:
 329         case BCMA_CHIP_ID_BCM5356:
 330                 /* always 25Mhz */
 331                 return 25000 * 1000;
 332         case BCMA_CHIP_ID_BCM43460:
 333         case BCMA_CHIP_ID_BCM4352:
 334         case BCMA_CHIP_ID_BCM4360:
 335                 if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
 336                         return 40000 * 1000;
 337                 else
 338                         return 20000 * 1000;
 339         default:
 340                 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
 341                           bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
 342         }
 343         return BCMA_CC_PMU_ALP_CLOCK;
 344 }
 345 
 346 /* Find the output of the "m" pll divider given pll controls that start with
 347  * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 348  */
 349 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 350 {
 351         u32 tmp, div, ndiv, p1, p2, fc;
 352         struct bcma_bus *bus = cc->core->bus;
 353 
 354         BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
 355 
 356         BUG_ON(!m || m > 4);
 357 
 358         if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
 359             bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
 360                 /* Detect failure in clock setting */
 361                 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 362                 if (tmp & 0x40000)
 363                         return 133 * 1000000;
 364         }
 365 
 366         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
 367         p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
 368         p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
 369 
 370         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
 371         div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
 372                 BCMA_CC_PPL_MDIV_MASK;
 373 
 374         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
 375         ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
 376 
 377         /* Do calculation in Mhz */
 378         fc = bcma_pmu_get_alp_clock(cc) / 1000000;
 379         fc = (p1 * ndiv * fc) / p2;
 380 
 381         /* Return clock in Hertz */
 382         return (fc / div) * 1000000;
 383 }
 384 
 385 static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 386 {
 387         u32 tmp, ndiv, p1div, p2div;
 388         u32 clock;
 389 
 390         BUG_ON(!m || m > 4);
 391 
 392         /* Get N, P1 and P2 dividers to determine CPU clock */
 393         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
 394         ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
 395                 >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
 396         p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
 397                 >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
 398         p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
 399                 >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
 400 
 401         tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 402         if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
 403                 /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
 404                 clock = (25000000 / 4) * ndiv * p2div / p1div;
 405         else
 406                 /* Fixed reference clock 25MHz and m = 2 */
 407                 clock = (25000000 / 2) * ndiv * p2div / p1div;
 408 
 409         if (m == BCMA_CC_PMU5_MAINPLL_SSB)
 410                 clock = clock / 4;
 411 
 412         return clock;
 413 }
 414 
 415 /* query bus clock frequency for PMU-enabled chipcommon */
 416 u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
 417 {
 418         struct bcma_bus *bus = cc->core->bus;
 419 
 420         switch (bus->chipinfo.id) {
 421         case BCMA_CHIP_ID_BCM4716:
 422         case BCMA_CHIP_ID_BCM4748:
 423         case BCMA_CHIP_ID_BCM47162:
 424                 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
 425                                           BCMA_CC_PMU5_MAINPLL_SSB);
 426         case BCMA_CHIP_ID_BCM5356:
 427                 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
 428                                           BCMA_CC_PMU5_MAINPLL_SSB);
 429         case BCMA_CHIP_ID_BCM5357:
 430         case BCMA_CHIP_ID_BCM4749:
 431                 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
 432                                           BCMA_CC_PMU5_MAINPLL_SSB);
 433         case BCMA_CHIP_ID_BCM4706:
 434                 return bcma_pmu_pll_clock_bcm4706(cc,
 435                                                   BCMA_CC_PMU4706_MAINPLL_PLL0,
 436                                                   BCMA_CC_PMU5_MAINPLL_SSB);
 437         case BCMA_CHIP_ID_BCM53572:
 438                 return 75000000;
 439         default:
 440                 bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
 441                           bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
 442         }
 443         return BCMA_CC_PMU_HT_CLOCK;
 444 }
 445 EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
 446 
 447 /* query cpu clock frequency for PMU-enabled chipcommon */
 448 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
 449 {
 450         struct bcma_bus *bus = cc->core->bus;
 451 
 452         if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
 453                 return 300000000;
 454 
 455         /* New PMUs can have different clock for bus and CPU */
 456         if (cc->pmu.rev >= 5) {
 457                 u32 pll;
 458                 switch (bus->chipinfo.id) {
 459                 case BCMA_CHIP_ID_BCM4706:
 460                         return bcma_pmu_pll_clock_bcm4706(cc,
 461                                                 BCMA_CC_PMU4706_MAINPLL_PLL0,
 462                                                 BCMA_CC_PMU5_MAINPLL_CPU);
 463                 case BCMA_CHIP_ID_BCM5356:
 464                         pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
 465                         break;
 466                 case BCMA_CHIP_ID_BCM5357:
 467                 case BCMA_CHIP_ID_BCM4749:
 468                         pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
 469                         break;
 470                 default:
 471                         pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
 472                         break;
 473                 }
 474 
 475                 return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 476         }
 477 
 478         /* On old PMUs CPU has the same clock as the bus */
 479         return bcma_pmu_get_bus_clock(cc);
 480 }
 481 
 482 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
 483                                          u32 value)
 484 {
 485         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
 486         bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
 487 }
 488 
 489 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
 490 {
 491         u32 tmp = 0;
 492         u8 phypll_offset = 0;
 493         u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
 494         u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
 495         struct bcma_bus *bus = cc->core->bus;
 496 
 497         switch (bus->chipinfo.id) {
 498         case BCMA_CHIP_ID_BCM5357:
 499         case BCMA_CHIP_ID_BCM4749:
 500         case BCMA_CHIP_ID_BCM53572:
 501                 /* 5357[ab]0, 43236[ab]0, and 6362b0 */
 502 
 503                 /* BCM5357 needs to touch PLL1_PLLCTL[02],
 504                    so offset PLL0_PLLCTL[02] by 6 */
 505                 phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
 506                        bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
 507                        bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
 508 
 509                 /* RMW only the P1 divider */
 510                 bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
 511                                 BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
 512                 tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
 513                 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
 514                 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
 515                 bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
 516 
 517                 /* RMW only the int feedback divider */
 518                 bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
 519                                 BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
 520                 tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
 521                 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
 522                 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
 523                 bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
 524 
 525                 tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 526                 break;
 527 
 528         case BCMA_CHIP_ID_BCM4331:
 529         case BCMA_CHIP_ID_BCM43431:
 530                 if (spuravoid == 2) {
 531                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 532                                                      0x11500014);
 533                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 534                                                      0x0FC00a08);
 535                 } else if (spuravoid == 1) {
 536                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 537                                                      0x11500014);
 538                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 539                                                      0x0F600a08);
 540                 } else {
 541                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 542                                                      0x11100014);
 543                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 544                                                      0x03000a08);
 545                 }
 546                 tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 547                 break;
 548 
 549         case BCMA_CHIP_ID_BCM43224:
 550         case BCMA_CHIP_ID_BCM43225:
 551         case BCMA_CHIP_ID_BCM43421:
 552                 if (spuravoid == 1) {
 553                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 554                                                      0x11500010);
 555                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 556                                                      0x000C0C06);
 557                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 558                                                      0x0F600a08);
 559                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 560                                                      0x00000000);
 561                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 562                                                      0x2001E920);
 563                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 564                                                      0x88888815);
 565                 } else {
 566                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 567                                                      0x11100010);
 568                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 569                                                      0x000c0c06);
 570                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 571                                                      0x03000a08);
 572                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 573                                                      0x00000000);
 574                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 575                                                      0x200005c0);
 576                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 577                                                      0x88888815);
 578                 }
 579                 tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 580                 break;
 581 
 582         case BCMA_CHIP_ID_BCM4716:
 583         case BCMA_CHIP_ID_BCM4748:
 584         case BCMA_CHIP_ID_BCM47162:
 585                 if (spuravoid == 1) {
 586                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 587                                                      0x11500060);
 588                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 589                                                      0x080C0C06);
 590                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 591                                                      0x0F600000);
 592                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 593                                                      0x00000000);
 594                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 595                                                      0x2001E924);
 596                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 597                                                      0x88888815);
 598                 } else {
 599                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 600                                                      0x11100060);
 601                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 602                                                      0x080c0c06);
 603                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 604                                                      0x03000000);
 605                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 606                                                      0x00000000);
 607                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 608                                                      0x200005c0);
 609                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 610                                                      0x88888815);
 611                 }
 612 
 613                 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
 614                 break;
 615 
 616         case BCMA_CHIP_ID_BCM43131:
 617         case BCMA_CHIP_ID_BCM43217:
 618         case BCMA_CHIP_ID_BCM43227:
 619         case BCMA_CHIP_ID_BCM43228:
 620         case BCMA_CHIP_ID_BCM43428:
 621                 /* LCNXN */
 622                 /* PLL Settings for spur avoidance on/off mode,
 623                    no on2 support for 43228A0 */
 624                 if (spuravoid == 1) {
 625                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 626                                                      0x01100014);
 627                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 628                                                      0x040C0C06);
 629                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 630                                                      0x03140A08);
 631                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 632                                                      0x00333333);
 633                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 634                                                      0x202C2820);
 635                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 636                                                      0x88888815);
 637                 } else {
 638                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
 639                                                      0x11100014);
 640                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
 641                                                      0x040c0c06);
 642                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 643                                                      0x03000a08);
 644                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
 645                                                      0x00000000);
 646                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
 647                                                      0x200005c0);
 648                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 649                                                      0x88888815);
 650                 }
 651                 tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 652                 break;
 653         default:
 654                 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 655                          bus->chipinfo.id);
 656                 break;
 657         }
 658 
 659         tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
 660         bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
 661 }
 662 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);