This source file includes following definitions.
- stm32_timer_is_trgo2_name
- stm32_timer_is_trgo_name
- stm32_timer_start
- stm32_timer_stop
- stm32_tt_store_frequency
- stm32_tt_read_frequency
- stm32_tt_show_master_mode
- stm32_tt_store_master_mode
- stm32_tt_show_master_mode_avail
- stm32_setup_iio_triggers
- stm32_counter_read_raw
- stm32_counter_write_raw
- stm32_counter_validate_trigger
- stm32_set_trigger_mode
- stm32_get_trigger_mode
- stm32_enable_mode2sms
- stm32_set_enable_mode
- stm32_sms2enable_mode
- stm32_get_enable_mode
- stm32_count_get_preset
- stm32_count_set_preset
- stm32_setup_counter_device
- is_stm32_timer_trigger
- stm32_timer_detect_trgo2
- stm32_timer_trigger_probe
1
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8
9 #include <linux/iio/iio.h>
10 #include <linux/iio/sysfs.h>
11 #include <linux/iio/timer/stm32-timer-trigger.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/mfd/stm32-timers.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_device.h>
17
18 #define MAX_TRIGGERS 7
19 #define MAX_VALIDS 5
20
21
22 static const void *triggers_table[][MAX_TRIGGERS] = {
23 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
24 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
25 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
26 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
27 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
28 { TIM6_TRGO,},
29 { TIM7_TRGO,},
30 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
31 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
32 { TIM10_OC1,},
33 { TIM11_OC1,},
34 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
35 { TIM13_OC1,},
36 { TIM14_OC1,},
37 { TIM15_TRGO,},
38 { TIM16_OC1,},
39 { TIM17_OC1,},
40 };
41
42
43 static const void *valids_table[][MAX_VALIDS] = {
44 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
45 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
46 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
47 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
48 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
49 { },
50 { },
51 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
52 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
53 { },
54 { },
55 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
56 };
57
58 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
59 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
60 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
61 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
62 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
63 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
64 { },
65 { },
66 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
67 { },
68 { },
69 { },
70 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
71 { },
72 { },
73 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
74 { },
75 { },
76 };
77
78 struct stm32_timer_trigger {
79 struct device *dev;
80 struct regmap *regmap;
81 struct clk *clk;
82 u32 max_arr;
83 const void *triggers;
84 const void *valids;
85 bool has_trgo2;
86 };
87
88 struct stm32_timer_trigger_cfg {
89 const void *(*valids_table)[MAX_VALIDS];
90 const unsigned int num_valids_table;
91 };
92
93 static bool stm32_timer_is_trgo2_name(const char *name)
94 {
95 return !!strstr(name, "trgo2");
96 }
97
98 static bool stm32_timer_is_trgo_name(const char *name)
99 {
100 return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
101 }
102
103 static int stm32_timer_start(struct stm32_timer_trigger *priv,
104 struct iio_trigger *trig,
105 unsigned int frequency)
106 {
107 unsigned long long prd, div;
108 int prescaler = 0;
109 u32 ccer, cr1;
110
111
112 div = (unsigned long long)clk_get_rate(priv->clk);
113
114 do_div(div, frequency);
115
116 prd = div;
117
118
119
120
121
122 while (div > priv->max_arr) {
123 prescaler++;
124 div = prd;
125 do_div(div, (prescaler + 1));
126 }
127 prd = div;
128
129 if (prescaler > MAX_TIM_PSC) {
130 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
131 return -EINVAL;
132 }
133
134
135 regmap_read(priv->regmap, TIM_CCER, &ccer);
136 if (ccer & TIM_CCER_CCXE)
137 return -EBUSY;
138
139 regmap_read(priv->regmap, TIM_CR1, &cr1);
140 if (!(cr1 & TIM_CR1_CEN))
141 clk_enable(priv->clk);
142
143 regmap_write(priv->regmap, TIM_PSC, prescaler);
144 regmap_write(priv->regmap, TIM_ARR, prd - 1);
145 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
146
147
148 if (stm32_timer_is_trgo2_name(trig->name))
149 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
150 0x2 << TIM_CR2_MMS2_SHIFT);
151 else
152 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
153 0x2 << TIM_CR2_MMS_SHIFT);
154
155
156 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
157
158
159 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
160
161 return 0;
162 }
163
164 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
165 struct iio_trigger *trig)
166 {
167 u32 ccer, cr1;
168
169 regmap_read(priv->regmap, TIM_CCER, &ccer);
170 if (ccer & TIM_CCER_CCXE)
171 return;
172
173 regmap_read(priv->regmap, TIM_CR1, &cr1);
174 if (cr1 & TIM_CR1_CEN)
175 clk_disable(priv->clk);
176
177
178 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
179 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
180 regmap_write(priv->regmap, TIM_PSC, 0);
181 regmap_write(priv->regmap, TIM_ARR, 0);
182
183
184 if (stm32_timer_is_trgo2_name(trig->name))
185 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
186 else
187 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
188
189
190 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
191 }
192
193 static ssize_t stm32_tt_store_frequency(struct device *dev,
194 struct device_attribute *attr,
195 const char *buf, size_t len)
196 {
197 struct iio_trigger *trig = to_iio_trigger(dev);
198 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
199 unsigned int freq;
200 int ret;
201
202 ret = kstrtouint(buf, 10, &freq);
203 if (ret)
204 return ret;
205
206 if (freq == 0) {
207 stm32_timer_stop(priv, trig);
208 } else {
209 ret = stm32_timer_start(priv, trig, freq);
210 if (ret)
211 return ret;
212 }
213
214 return len;
215 }
216
217 static ssize_t stm32_tt_read_frequency(struct device *dev,
218 struct device_attribute *attr, char *buf)
219 {
220 struct iio_trigger *trig = to_iio_trigger(dev);
221 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
222 u32 psc, arr, cr1;
223 unsigned long long freq = 0;
224
225 regmap_read(priv->regmap, TIM_CR1, &cr1);
226 regmap_read(priv->regmap, TIM_PSC, &psc);
227 regmap_read(priv->regmap, TIM_ARR, &arr);
228
229 if (cr1 & TIM_CR1_CEN) {
230 freq = (unsigned long long)clk_get_rate(priv->clk);
231 do_div(freq, psc + 1);
232 do_div(freq, arr + 1);
233 }
234
235 return sprintf(buf, "%d\n", (unsigned int)freq);
236 }
237
238 static IIO_DEV_ATTR_SAMP_FREQ(0660,
239 stm32_tt_read_frequency,
240 stm32_tt_store_frequency);
241
242 #define MASTER_MODE_MAX 7
243 #define MASTER_MODE2_MAX 15
244
245 static char *master_mode_table[] = {
246 "reset",
247 "enable",
248 "update",
249 "compare_pulse",
250 "OC1REF",
251 "OC2REF",
252 "OC3REF",
253 "OC4REF",
254
255 "OC5REF",
256 "OC6REF",
257 "compare_pulse_OC4REF",
258 "compare_pulse_OC6REF",
259 "compare_pulse_OC4REF_r_or_OC6REF_r",
260 "compare_pulse_OC4REF_r_or_OC6REF_f",
261 "compare_pulse_OC5REF_r_or_OC6REF_r",
262 "compare_pulse_OC5REF_r_or_OC6REF_f",
263 };
264
265 static ssize_t stm32_tt_show_master_mode(struct device *dev,
266 struct device_attribute *attr,
267 char *buf)
268 {
269 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
270 struct iio_trigger *trig = to_iio_trigger(dev);
271 u32 cr2;
272
273 regmap_read(priv->regmap, TIM_CR2, &cr2);
274
275 if (stm32_timer_is_trgo2_name(trig->name))
276 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
277 else
278 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
279
280 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
281 }
282
283 static ssize_t stm32_tt_store_master_mode(struct device *dev,
284 struct device_attribute *attr,
285 const char *buf, size_t len)
286 {
287 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
288 struct iio_trigger *trig = to_iio_trigger(dev);
289 u32 mask, shift, master_mode_max;
290 int i;
291
292 if (stm32_timer_is_trgo2_name(trig->name)) {
293 mask = TIM_CR2_MMS2;
294 shift = TIM_CR2_MMS2_SHIFT;
295 master_mode_max = MASTER_MODE2_MAX;
296 } else {
297 mask = TIM_CR2_MMS;
298 shift = TIM_CR2_MMS_SHIFT;
299 master_mode_max = MASTER_MODE_MAX;
300 }
301
302 for (i = 0; i <= master_mode_max; i++) {
303 if (!strncmp(master_mode_table[i], buf,
304 strlen(master_mode_table[i]))) {
305 regmap_update_bits(priv->regmap, TIM_CR2, mask,
306 i << shift);
307
308 regmap_update_bits(priv->regmap, TIM_EGR,
309 TIM_EGR_UG, TIM_EGR_UG);
310 return len;
311 }
312 }
313
314 return -EINVAL;
315 }
316
317 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
318 struct device_attribute *attr,
319 char *buf)
320 {
321 struct iio_trigger *trig = to_iio_trigger(dev);
322 unsigned int i, master_mode_max;
323 size_t len = 0;
324
325 if (stm32_timer_is_trgo2_name(trig->name))
326 master_mode_max = MASTER_MODE2_MAX;
327 else
328 master_mode_max = MASTER_MODE_MAX;
329
330 for (i = 0; i <= master_mode_max; i++)
331 len += scnprintf(buf + len, PAGE_SIZE - len,
332 "%s ", master_mode_table[i]);
333
334
335 buf[len - 1] = '\n';
336
337 return len;
338 }
339
340 static IIO_DEVICE_ATTR(master_mode_available, 0444,
341 stm32_tt_show_master_mode_avail, NULL, 0);
342
343 static IIO_DEVICE_ATTR(master_mode, 0660,
344 stm32_tt_show_master_mode,
345 stm32_tt_store_master_mode,
346 0);
347
348 static struct attribute *stm32_trigger_attrs[] = {
349 &iio_dev_attr_sampling_frequency.dev_attr.attr,
350 &iio_dev_attr_master_mode.dev_attr.attr,
351 &iio_dev_attr_master_mode_available.dev_attr.attr,
352 NULL,
353 };
354
355 static const struct attribute_group stm32_trigger_attr_group = {
356 .attrs = stm32_trigger_attrs,
357 };
358
359 static const struct attribute_group *stm32_trigger_attr_groups[] = {
360 &stm32_trigger_attr_group,
361 NULL,
362 };
363
364 static const struct iio_trigger_ops timer_trigger_ops = {
365 };
366
367 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
368 {
369 int ret;
370 const char * const *cur = priv->triggers;
371
372 while (cur && *cur) {
373 struct iio_trigger *trig;
374 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
375 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
376
377 if (cur_is_trgo2 && !priv->has_trgo2) {
378 cur++;
379 continue;
380 }
381
382 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
383 if (!trig)
384 return -ENOMEM;
385
386 trig->dev.parent = priv->dev->parent;
387 trig->ops = &timer_trigger_ops;
388
389
390
391
392
393 if (cur_is_trgo || cur_is_trgo2)
394 trig->dev.groups = stm32_trigger_attr_groups;
395
396 iio_trigger_set_drvdata(trig, priv);
397
398 ret = devm_iio_trigger_register(priv->dev, trig);
399 if (ret)
400 return ret;
401 cur++;
402 }
403
404 return 0;
405 }
406
407 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
408 struct iio_chan_spec const *chan,
409 int *val, int *val2, long mask)
410 {
411 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
412 u32 dat;
413
414 switch (mask) {
415 case IIO_CHAN_INFO_RAW:
416 regmap_read(priv->regmap, TIM_CNT, &dat);
417 *val = dat;
418 return IIO_VAL_INT;
419
420 case IIO_CHAN_INFO_ENABLE:
421 regmap_read(priv->regmap, TIM_CR1, &dat);
422 *val = (dat & TIM_CR1_CEN) ? 1 : 0;
423 return IIO_VAL_INT;
424
425 case IIO_CHAN_INFO_SCALE:
426 regmap_read(priv->regmap, TIM_SMCR, &dat);
427 dat &= TIM_SMCR_SMS;
428
429 *val = 1;
430 *val2 = 0;
431
432
433 if (dat == 3)
434 *val2 = 2;
435
436 return IIO_VAL_FRACTIONAL_LOG2;
437 }
438
439 return -EINVAL;
440 }
441
442 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
443 struct iio_chan_spec const *chan,
444 int val, int val2, long mask)
445 {
446 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
447 u32 dat;
448
449 switch (mask) {
450 case IIO_CHAN_INFO_RAW:
451 return regmap_write(priv->regmap, TIM_CNT, val);
452
453 case IIO_CHAN_INFO_SCALE:
454
455 return -EINVAL;
456
457 case IIO_CHAN_INFO_ENABLE:
458 if (val) {
459 regmap_read(priv->regmap, TIM_CR1, &dat);
460 if (!(dat & TIM_CR1_CEN))
461 clk_enable(priv->clk);
462 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
463 TIM_CR1_CEN);
464 } else {
465 regmap_read(priv->regmap, TIM_CR1, &dat);
466 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
467 0);
468 if (dat & TIM_CR1_CEN)
469 clk_disable(priv->clk);
470 }
471 return 0;
472 }
473
474 return -EINVAL;
475 }
476
477 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
478 struct iio_trigger *trig)
479 {
480 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
481 const char * const *cur = priv->valids;
482 unsigned int i = 0;
483
484 if (!is_stm32_timer_trigger(trig))
485 return -EINVAL;
486
487 while (cur && *cur) {
488 if (!strncmp(trig->name, *cur, strlen(trig->name))) {
489 regmap_update_bits(priv->regmap,
490 TIM_SMCR, TIM_SMCR_TS,
491 i << TIM_SMCR_TS_SHIFT);
492 return 0;
493 }
494 cur++;
495 i++;
496 }
497
498 return -EINVAL;
499 }
500
501 static const struct iio_info stm32_trigger_info = {
502 .validate_trigger = stm32_counter_validate_trigger,
503 .read_raw = stm32_counter_read_raw,
504 .write_raw = stm32_counter_write_raw
505 };
506
507 static const char *const stm32_trigger_modes[] = {
508 "trigger",
509 };
510
511 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
512 const struct iio_chan_spec *chan,
513 unsigned int mode)
514 {
515 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
516
517 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
518
519 return 0;
520 }
521
522 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
523 const struct iio_chan_spec *chan)
524 {
525 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
526 u32 smcr;
527
528 regmap_read(priv->regmap, TIM_SMCR, &smcr);
529
530 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
531 }
532
533 static const struct iio_enum stm32_trigger_mode_enum = {
534 .items = stm32_trigger_modes,
535 .num_items = ARRAY_SIZE(stm32_trigger_modes),
536 .set = stm32_set_trigger_mode,
537 .get = stm32_get_trigger_mode
538 };
539
540 static const char *const stm32_enable_modes[] = {
541 "always",
542 "gated",
543 "triggered",
544 };
545
546 static int stm32_enable_mode2sms(int mode)
547 {
548 switch (mode) {
549 case 0:
550 return 0;
551 case 1:
552 return 5;
553 case 2:
554 return 6;
555 }
556
557 return -EINVAL;
558 }
559
560 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
561 const struct iio_chan_spec *chan,
562 unsigned int mode)
563 {
564 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
565 int sms = stm32_enable_mode2sms(mode);
566 u32 val;
567
568 if (sms < 0)
569 return sms;
570
571
572
573
574 if (sms == 6) {
575 regmap_read(priv->regmap, TIM_CR1, &val);
576 if (!(val & TIM_CR1_CEN))
577 clk_enable(priv->clk);
578 }
579
580 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
581
582 return 0;
583 }
584
585 static int stm32_sms2enable_mode(int mode)
586 {
587 switch (mode) {
588 case 0:
589 return 0;
590 case 5:
591 return 1;
592 case 6:
593 return 2;
594 }
595
596 return -EINVAL;
597 }
598
599 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
600 const struct iio_chan_spec *chan)
601 {
602 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
603 u32 smcr;
604
605 regmap_read(priv->regmap, TIM_SMCR, &smcr);
606 smcr &= TIM_SMCR_SMS;
607
608 return stm32_sms2enable_mode(smcr);
609 }
610
611 static const struct iio_enum stm32_enable_mode_enum = {
612 .items = stm32_enable_modes,
613 .num_items = ARRAY_SIZE(stm32_enable_modes),
614 .set = stm32_set_enable_mode,
615 .get = stm32_get_enable_mode
616 };
617
618 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
619 uintptr_t private,
620 const struct iio_chan_spec *chan,
621 char *buf)
622 {
623 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
624 u32 arr;
625
626 regmap_read(priv->regmap, TIM_ARR, &arr);
627
628 return snprintf(buf, PAGE_SIZE, "%u\n", arr);
629 }
630
631 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
632 uintptr_t private,
633 const struct iio_chan_spec *chan,
634 const char *buf, size_t len)
635 {
636 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
637 unsigned int preset;
638 int ret;
639
640 ret = kstrtouint(buf, 0, &preset);
641 if (ret)
642 return ret;
643
644
645 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
646 regmap_write(priv->regmap, TIM_ARR, preset);
647
648 return len;
649 }
650
651 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
652 {
653 .name = "preset",
654 .shared = IIO_SEPARATE,
655 .read = stm32_count_get_preset,
656 .write = stm32_count_set_preset
657 },
658 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
659 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
660 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
661 IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
662 {}
663 };
664
665 static const struct iio_chan_spec stm32_trigger_channel = {
666 .type = IIO_COUNT,
667 .channel = 0,
668 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
669 BIT(IIO_CHAN_INFO_ENABLE) |
670 BIT(IIO_CHAN_INFO_SCALE),
671 .ext_info = stm32_trigger_count_info,
672 .indexed = 1
673 };
674
675 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
676 {
677 struct iio_dev *indio_dev;
678 int ret;
679
680 indio_dev = devm_iio_device_alloc(dev,
681 sizeof(struct stm32_timer_trigger));
682 if (!indio_dev)
683 return NULL;
684
685 indio_dev->name = dev_name(dev);
686 indio_dev->dev.parent = dev;
687 indio_dev->info = &stm32_trigger_info;
688 indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
689 indio_dev->num_channels = 1;
690 indio_dev->channels = &stm32_trigger_channel;
691 indio_dev->dev.of_node = dev->of_node;
692
693 ret = devm_iio_device_register(dev, indio_dev);
694 if (ret)
695 return NULL;
696
697 return iio_priv(indio_dev);
698 }
699
700
701
702
703
704
705
706
707 bool is_stm32_timer_trigger(struct iio_trigger *trig)
708 {
709 return (trig->ops == &timer_trigger_ops);
710 }
711 EXPORT_SYMBOL(is_stm32_timer_trigger);
712
713 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
714 {
715 u32 val;
716
717
718
719
720
721 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
722 regmap_read(priv->regmap, TIM_CR2, &val);
723 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
724 priv->has_trgo2 = !!val;
725 }
726
727 static int stm32_timer_trigger_probe(struct platform_device *pdev)
728 {
729 struct device *dev = &pdev->dev;
730 struct stm32_timer_trigger *priv;
731 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
732 const struct stm32_timer_trigger_cfg *cfg;
733 unsigned int index;
734 int ret;
735
736 if (of_property_read_u32(dev->of_node, "reg", &index))
737 return -EINVAL;
738
739 cfg = (const struct stm32_timer_trigger_cfg *)
740 of_match_device(dev->driver->of_match_table, dev)->data;
741
742 if (index >= ARRAY_SIZE(triggers_table) ||
743 index >= cfg->num_valids_table)
744 return -EINVAL;
745
746
747 if (*cfg->valids_table[index])
748 priv = stm32_setup_counter_device(dev);
749 else
750 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
751
752 if (!priv)
753 return -ENOMEM;
754
755 priv->dev = dev;
756 priv->regmap = ddata->regmap;
757 priv->clk = ddata->clk;
758 priv->max_arr = ddata->max_arr;
759 priv->triggers = triggers_table[index];
760 priv->valids = cfg->valids_table[index];
761 stm32_timer_detect_trgo2(priv);
762
763 ret = stm32_setup_iio_triggers(priv);
764 if (ret)
765 return ret;
766
767 platform_set_drvdata(pdev, priv);
768
769 return 0;
770 }
771
772 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
773 .valids_table = valids_table,
774 .num_valids_table = ARRAY_SIZE(valids_table),
775 };
776
777 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
778 .valids_table = stm32h7_valids_table,
779 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
780 };
781
782 static const struct of_device_id stm32_trig_of_match[] = {
783 {
784 .compatible = "st,stm32-timer-trigger",
785 .data = (void *)&stm32_timer_trg_cfg,
786 }, {
787 .compatible = "st,stm32h7-timer-trigger",
788 .data = (void *)&stm32h7_timer_trg_cfg,
789 },
790 { },
791 };
792 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
793
794 static struct platform_driver stm32_timer_trigger_driver = {
795 .probe = stm32_timer_trigger_probe,
796 .driver = {
797 .name = "stm32-timer-trigger",
798 .of_match_table = stm32_trig_of_match,
799 },
800 };
801 module_platform_driver(stm32_timer_trigger_driver);
802
803 MODULE_ALIAS("platform: stm32-timer-trigger");
804 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
805 MODULE_LICENSE("GPL v2");