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9 #ifndef MDF_STM32_DFSDM__H
10 #define MDF_STM32_DFSDM__H
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12 #include <linux/bitfield.h>
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40 #define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
41 #define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
42 #define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
43 #define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C)
44 #define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)
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46
47 #define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)
48 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
49 #define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
50 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
51 #define DFSDM_CHCFGR1_SCDEN_MASK BIT(5)
52 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
53 #define DFSDM_CHCFGR1_CKABEN_MASK BIT(6)
54 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
55 #define DFSDM_CHCFGR1_CHEN_MASK BIT(7)
56 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
57 #define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8)
58 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
59 #define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)
60 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
61 #define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
62 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
63 #define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
64 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
65 #define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)
66 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
67 #define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31)
68 #define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
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71 #define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)
72 #define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
73 #define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)
74 #define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
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77 #define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)
78 #define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
79 #define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)
80 #define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
81 #define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)
82 #define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
83 #define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)
84 #define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
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89 #define DFSDM_FILTER_BASE_ADR 0x100
90 #define DFSDM_FILTER_REG_MASK 0x7F
91 #define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)
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93 #define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00)
94 #define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04)
95 #define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08)
96 #define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C)
97 #define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10)
98 #define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14)
99 #define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18)
100 #define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C)
101 #define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20)
102 #define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24)
103 #define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28)
104 #define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C)
105 #define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30)
106 #define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34)
107 #define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38)
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110 #define DFSDM_CR1_DFEN_MASK BIT(0)
111 #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
112 #define DFSDM_CR1_JSWSTART_MASK BIT(1)
113 #define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
114 #define DFSDM_CR1_JSYNC_MASK BIT(3)
115 #define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
116 #define DFSDM_CR1_JSCAN_MASK BIT(4)
117 #define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
118 #define DFSDM_CR1_JDMAEN_MASK BIT(5)
119 #define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
120 #define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)
121 #define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
122 #define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)
123 #define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
124 #define DFSDM_CR1_RSWSTART_MASK BIT(17)
125 #define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
126 #define DFSDM_CR1_RCONT_MASK BIT(18)
127 #define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
128 #define DFSDM_CR1_RSYNC_MASK BIT(19)
129 #define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
130 #define DFSDM_CR1_RDMAEN_MASK BIT(21)
131 #define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
132 #define DFSDM_CR1_RCH_MASK GENMASK(26, 24)
133 #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
134 #define DFSDM_CR1_FAST_MASK BIT(29)
135 #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
136 #define DFSDM_CR1_AWFSEL_MASK BIT(30)
137 #define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
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140 #define DFSDM_CR2_IE_MASK GENMASK(6, 0)
141 #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
142 #define DFSDM_CR2_JEOCIE_MASK BIT(0)
143 #define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
144 #define DFSDM_CR2_REOCIE_MASK BIT(1)
145 #define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
146 #define DFSDM_CR2_JOVRIE_MASK BIT(2)
147 #define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
148 #define DFSDM_CR2_ROVRIE_MASK BIT(3)
149 #define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
150 #define DFSDM_CR2_AWDIE_MASK BIT(4)
151 #define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
152 #define DFSDM_CR2_SCDIE_MASK BIT(5)
153 #define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
154 #define DFSDM_CR2_CKABIE_MASK BIT(6)
155 #define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
156 #define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)
157 #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
158 #define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)
159 #define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
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162 #define DFSDM_ISR_JEOCF_MASK BIT(0)
163 #define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
164 #define DFSDM_ISR_REOCF_MASK BIT(1)
165 #define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
166 #define DFSDM_ISR_JOVRF_MASK BIT(2)
167 #define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
168 #define DFSDM_ISR_ROVRF_MASK BIT(3)
169 #define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
170 #define DFSDM_ISR_AWDF_MASK BIT(4)
171 #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
172 #define DFSDM_ISR_JCIP_MASK BIT(13)
173 #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
174 #define DFSDM_ISR_RCIP_MASK BIT(14)
175 #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
176 #define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)
177 #define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
178 #define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)
179 #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
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182 #define DFSDM_ICR_CLRJOVRF_MASK BIT(2)
183 #define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
184 #define DFSDM_ICR_CLRROVRF_MASK BIT(3)
185 #define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
186 #define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)
187 #define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
188 #define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))
189 #define DFSDM_ICR_CLRCKABF_CH(v, y) \
190 (((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
191 #define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)
192 #define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
193 #define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y))
194 #define DFSDM_ICR_CLRSCDF_CH(v, y) \
195 (((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
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198 #define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)
199 #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
200 #define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)
201 #define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
202 #define DFSDM_FCR_FORD_MASK GENMASK(31, 29)
203 #define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
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206 #define DFSDM_DATAR_CH_MASK GENMASK(2, 0)
207 #define DFSDM_DATAR_DATA_OFFSET 8
208 #define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
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211 #define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)
212 #define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
213 #define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)
214 #define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
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217 #define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)
218 #define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
219 #define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)
220 #define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
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223 #define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)
224 #define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
225 #define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)
226 #define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
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229 #define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)
230 #define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
231 #define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)
232 #define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
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235 enum stm32_dfsdm_sinc_order {
236 DFSDM_FASTSINC_ORDER,
237 DFSDM_SINC1_ORDER,
238 DFSDM_SINC2_ORDER,
239 DFSDM_SINC3_ORDER,
240 DFSDM_SINC4_ORDER,
241 DFSDM_SINC5_ORDER,
242 DFSDM_NB_SINC_ORDER,
243 };
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254 struct stm32_dfsdm_filter_osr {
255 unsigned int iosr;
256 unsigned int fosr;
257 unsigned int rshift;
258 unsigned int lshift;
259 u64 res;
260 s32 max;
261 };
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270 struct stm32_dfsdm_filter {
271 enum stm32_dfsdm_sinc_order ford;
272 struct stm32_dfsdm_filter_osr flo[2];
273 unsigned int sync_mode;
274 unsigned int fast;
275 };
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284 struct stm32_dfsdm_channel {
285 unsigned int id;
286 unsigned int type;
287 unsigned int src;
288 unsigned int alt_si;
289 };
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302 struct stm32_dfsdm {
303 void __iomem *base;
304 phys_addr_t phys_base;
305 struct regmap *regmap;
306 struct stm32_dfsdm_filter *fl_list;
307 unsigned int num_fls;
308 struct stm32_dfsdm_channel *ch_list;
309 unsigned int num_chs;
310 unsigned int spi_master_freq;
311 };
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314 enum stm32_dfsdm_spi_clk_src {
315 DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,
316 DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,
317 DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,
318 DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
319 };
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321 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);
322 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);
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324 #endif