This source file includes following definitions.
- ad799x_write_config
- ad799x_read_config
- ad799x_trigger_handler
- ad799x_update_scan_mode
- ad799x_scan_direct
- ad799x_read_raw
- ad799x_read_frequency
- ad799x_write_frequency
- ad799x_read_event_config
- ad799x_write_event_config
- ad799x_threshold_reg
- ad799x_write_event_value
- ad799x_read_event_value
- ad799x_event_handler
- ad799x_probe
- ad799x_remove
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 #include <linux/interrupt.h>
22 #include <linux/device.h>
23 #include <linux/kernel.h>
24 #include <linux/sysfs.h>
25 #include <linux/i2c.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
29 #include <linux/err.h>
30 #include <linux/module.h>
31 #include <linux/bitops.h>
32
33 #include <linux/iio/iio.h>
34 #include <linux/iio/sysfs.h>
35 #include <linux/iio/events.h>
36 #include <linux/iio/buffer.h>
37 #include <linux/iio/trigger_consumer.h>
38 #include <linux/iio/triggered_buffer.h>
39
40 #define AD799X_CHANNEL_SHIFT 4
41
42
43
44
45
46 #define AD7991_REF_SEL 0x08
47 #define AD7991_FLTR 0x04
48 #define AD7991_BIT_TRIAL_DELAY 0x02
49 #define AD7991_SAMPLE_DELAY 0x01
50
51
52
53
54
55 #define AD7998_FLTR BIT(3)
56 #define AD7998_ALERT_EN BIT(2)
57 #define AD7998_BUSY_ALERT BIT(1)
58 #define AD7998_BUSY_ALERT_POL BIT(0)
59
60 #define AD7998_CONV_RES_REG 0x0
61 #define AD7998_ALERT_STAT_REG 0x1
62 #define AD7998_CONF_REG 0x2
63 #define AD7998_CYCLE_TMR_REG 0x3
64
65 #define AD7998_DATALOW_REG(x) ((x) * 3 + 0x4)
66 #define AD7998_DATAHIGH_REG(x) ((x) * 3 + 0x5)
67 #define AD7998_HYST_REG(x) ((x) * 3 + 0x6)
68
69 #define AD7998_CYC_MASK GENMASK(2, 0)
70 #define AD7998_CYC_DIS 0x0
71 #define AD7998_CYC_TCONF_32 0x1
72 #define AD7998_CYC_TCONF_64 0x2
73 #define AD7998_CYC_TCONF_128 0x3
74 #define AD7998_CYC_TCONF_256 0x4
75 #define AD7998_CYC_TCONF_512 0x5
76 #define AD7998_CYC_TCONF_1024 0x6
77 #define AD7998_CYC_TCONF_2048 0x7
78
79 #define AD7998_ALERT_STAT_CLEAR 0xFF
80
81
82
83
84
85 #define AD7997_8_READ_SINGLE BIT(7)
86 #define AD7997_8_READ_SEQUENCE (BIT(6) | BIT(5) | BIT(4))
87
88 enum {
89 ad7991,
90 ad7995,
91 ad7999,
92 ad7992,
93 ad7993,
94 ad7994,
95 ad7997,
96 ad7998
97 };
98
99
100
101
102
103
104
105 struct ad799x_chip_config {
106 const struct iio_chan_spec channel[9];
107 u16 default_config;
108 const struct iio_info *info;
109 };
110
111
112
113
114
115
116
117 struct ad799x_chip_info {
118 int num_channels;
119 const struct ad799x_chip_config noirq_config;
120 const struct ad799x_chip_config irq_config;
121 };
122
123 struct ad799x_state {
124 struct i2c_client *client;
125 const struct ad799x_chip_config *chip_config;
126 struct regulator *reg;
127 struct regulator *vref;
128 unsigned id;
129 u16 config;
130
131 u8 *rx_buf;
132 unsigned int transfer_size;
133 };
134
135 static int ad799x_write_config(struct ad799x_state *st, u16 val)
136 {
137 switch (st->id) {
138 case ad7997:
139 case ad7998:
140 return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG,
141 val);
142 case ad7992:
143 case ad7993:
144 case ad7994:
145 return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG,
146 val);
147 default:
148
149 st->config = val;
150 return 0;
151 }
152 }
153
154 static int ad799x_read_config(struct ad799x_state *st)
155 {
156 switch (st->id) {
157 case ad7997:
158 case ad7998:
159 return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG);
160 case ad7992:
161 case ad7993:
162 case ad7994:
163 return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG);
164 default:
165
166 return st->config;
167 }
168 }
169
170
171
172
173
174
175
176 static irqreturn_t ad799x_trigger_handler(int irq, void *p)
177 {
178 struct iio_poll_func *pf = p;
179 struct iio_dev *indio_dev = pf->indio_dev;
180 struct ad799x_state *st = iio_priv(indio_dev);
181 int b_sent;
182 u8 cmd;
183
184 switch (st->id) {
185 case ad7991:
186 case ad7995:
187 case ad7999:
188 cmd = st->config |
189 (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT);
190 break;
191 case ad7992:
192 case ad7993:
193 case ad7994:
194 cmd = (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT) |
195 AD7998_CONV_RES_REG;
196 break;
197 case ad7997:
198 case ad7998:
199 cmd = AD7997_8_READ_SEQUENCE | AD7998_CONV_RES_REG;
200 break;
201 default:
202 cmd = 0;
203 }
204
205 b_sent = i2c_smbus_read_i2c_block_data(st->client,
206 cmd, st->transfer_size, st->rx_buf);
207 if (b_sent < 0)
208 goto out;
209
210 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
211 iio_get_time_ns(indio_dev));
212 out:
213 iio_trigger_notify_done(indio_dev->trig);
214
215 return IRQ_HANDLED;
216 }
217
218 static int ad799x_update_scan_mode(struct iio_dev *indio_dev,
219 const unsigned long *scan_mask)
220 {
221 struct ad799x_state *st = iio_priv(indio_dev);
222
223 kfree(st->rx_buf);
224 st->rx_buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
225 if (!st->rx_buf)
226 return -ENOMEM;
227
228 st->transfer_size = bitmap_weight(scan_mask, indio_dev->masklength) * 2;
229
230 switch (st->id) {
231 case ad7992:
232 case ad7993:
233 case ad7994:
234 case ad7997:
235 case ad7998:
236 st->config &= ~(GENMASK(7, 0) << AD799X_CHANNEL_SHIFT);
237 st->config |= (*scan_mask << AD799X_CHANNEL_SHIFT);
238 return ad799x_write_config(st, st->config);
239 default:
240 return 0;
241 }
242 }
243
244 static int ad799x_scan_direct(struct ad799x_state *st, unsigned ch)
245 {
246 u8 cmd;
247
248 switch (st->id) {
249 case ad7991:
250 case ad7995:
251 case ad7999:
252 cmd = st->config | (BIT(ch) << AD799X_CHANNEL_SHIFT);
253 break;
254 case ad7992:
255 case ad7993:
256 case ad7994:
257 cmd = BIT(ch) << AD799X_CHANNEL_SHIFT;
258 break;
259 case ad7997:
260 case ad7998:
261 cmd = (ch << AD799X_CHANNEL_SHIFT) | AD7997_8_READ_SINGLE;
262 break;
263 default:
264 return -EINVAL;
265 }
266
267 return i2c_smbus_read_word_swapped(st->client, cmd);
268 }
269
270 static int ad799x_read_raw(struct iio_dev *indio_dev,
271 struct iio_chan_spec const *chan,
272 int *val,
273 int *val2,
274 long m)
275 {
276 int ret;
277 struct ad799x_state *st = iio_priv(indio_dev);
278
279 switch (m) {
280 case IIO_CHAN_INFO_RAW:
281 ret = iio_device_claim_direct_mode(indio_dev);
282 if (ret)
283 return ret;
284 ret = ad799x_scan_direct(st, chan->scan_index);
285 iio_device_release_direct_mode(indio_dev);
286
287 if (ret < 0)
288 return ret;
289 *val = (ret >> chan->scan_type.shift) &
290 GENMASK(chan->scan_type.realbits - 1, 0);
291 return IIO_VAL_INT;
292 case IIO_CHAN_INFO_SCALE:
293 ret = regulator_get_voltage(st->vref);
294 if (ret < 0)
295 return ret;
296 *val = ret / 1000;
297 *val2 = chan->scan_type.realbits;
298 return IIO_VAL_FRACTIONAL_LOG2;
299 }
300 return -EINVAL;
301 }
302 static const unsigned int ad7998_frequencies[] = {
303 [AD7998_CYC_DIS] = 0,
304 [AD7998_CYC_TCONF_32] = 15625,
305 [AD7998_CYC_TCONF_64] = 7812,
306 [AD7998_CYC_TCONF_128] = 3906,
307 [AD7998_CYC_TCONF_512] = 976,
308 [AD7998_CYC_TCONF_1024] = 488,
309 [AD7998_CYC_TCONF_2048] = 244,
310 };
311
312 static ssize_t ad799x_read_frequency(struct device *dev,
313 struct device_attribute *attr,
314 char *buf)
315 {
316 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
317 struct ad799x_state *st = iio_priv(indio_dev);
318
319 int ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
320 if (ret < 0)
321 return ret;
322
323 return sprintf(buf, "%u\n", ad7998_frequencies[ret & AD7998_CYC_MASK]);
324 }
325
326 static ssize_t ad799x_write_frequency(struct device *dev,
327 struct device_attribute *attr,
328 const char *buf,
329 size_t len)
330 {
331 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
332 struct ad799x_state *st = iio_priv(indio_dev);
333
334 long val;
335 int ret, i;
336
337 ret = kstrtol(buf, 10, &val);
338 if (ret)
339 return ret;
340
341 mutex_lock(&indio_dev->mlock);
342 ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
343 if (ret < 0)
344 goto error_ret_mutex;
345
346 ret &= ~AD7998_CYC_MASK;
347
348 for (i = 0; i < ARRAY_SIZE(ad7998_frequencies); i++)
349 if (val == ad7998_frequencies[i])
350 break;
351 if (i == ARRAY_SIZE(ad7998_frequencies)) {
352 ret = -EINVAL;
353 goto error_ret_mutex;
354 }
355
356 ret = i2c_smbus_write_byte_data(st->client, AD7998_CYCLE_TMR_REG,
357 ret | i);
358 if (ret < 0)
359 goto error_ret_mutex;
360 ret = len;
361
362 error_ret_mutex:
363 mutex_unlock(&indio_dev->mlock);
364
365 return ret;
366 }
367
368 static int ad799x_read_event_config(struct iio_dev *indio_dev,
369 const struct iio_chan_spec *chan,
370 enum iio_event_type type,
371 enum iio_event_direction dir)
372 {
373 struct ad799x_state *st = iio_priv(indio_dev);
374
375 if (!(st->config & AD7998_ALERT_EN))
376 return 0;
377
378 if ((st->config >> AD799X_CHANNEL_SHIFT) & BIT(chan->scan_index))
379 return 1;
380
381 return 0;
382 }
383
384 static int ad799x_write_event_config(struct iio_dev *indio_dev,
385 const struct iio_chan_spec *chan,
386 enum iio_event_type type,
387 enum iio_event_direction dir,
388 int state)
389 {
390 struct ad799x_state *st = iio_priv(indio_dev);
391 int ret;
392
393 ret = iio_device_claim_direct_mode(indio_dev);
394 if (ret)
395 return ret;
396
397 if (state)
398 st->config |= BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT;
399 else
400 st->config &= ~(BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT);
401
402 if (st->config >> AD799X_CHANNEL_SHIFT)
403 st->config |= AD7998_ALERT_EN;
404 else
405 st->config &= ~AD7998_ALERT_EN;
406
407 ret = ad799x_write_config(st, st->config);
408 iio_device_release_direct_mode(indio_dev);
409 return ret;
410 }
411
412 static unsigned int ad799x_threshold_reg(const struct iio_chan_spec *chan,
413 enum iio_event_direction dir,
414 enum iio_event_info info)
415 {
416 switch (info) {
417 case IIO_EV_INFO_VALUE:
418 if (dir == IIO_EV_DIR_FALLING)
419 return AD7998_DATALOW_REG(chan->channel);
420 else
421 return AD7998_DATAHIGH_REG(chan->channel);
422 case IIO_EV_INFO_HYSTERESIS:
423 return AD7998_HYST_REG(chan->channel);
424 default:
425 return -EINVAL;
426 }
427
428 return 0;
429 }
430
431 static int ad799x_write_event_value(struct iio_dev *indio_dev,
432 const struct iio_chan_spec *chan,
433 enum iio_event_type type,
434 enum iio_event_direction dir,
435 enum iio_event_info info,
436 int val, int val2)
437 {
438 int ret;
439 struct ad799x_state *st = iio_priv(indio_dev);
440
441 if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
442 return -EINVAL;
443
444 mutex_lock(&indio_dev->mlock);
445 ret = i2c_smbus_write_word_swapped(st->client,
446 ad799x_threshold_reg(chan, dir, info),
447 val << chan->scan_type.shift);
448 mutex_unlock(&indio_dev->mlock);
449
450 return ret;
451 }
452
453 static int ad799x_read_event_value(struct iio_dev *indio_dev,
454 const struct iio_chan_spec *chan,
455 enum iio_event_type type,
456 enum iio_event_direction dir,
457 enum iio_event_info info,
458 int *val, int *val2)
459 {
460 int ret;
461 struct ad799x_state *st = iio_priv(indio_dev);
462
463 mutex_lock(&indio_dev->mlock);
464 ret = i2c_smbus_read_word_swapped(st->client,
465 ad799x_threshold_reg(chan, dir, info));
466 mutex_unlock(&indio_dev->mlock);
467 if (ret < 0)
468 return ret;
469 *val = (ret >> chan->scan_type.shift) &
470 GENMASK(chan->scan_type.realbits - 1, 0);
471
472 return IIO_VAL_INT;
473 }
474
475 static irqreturn_t ad799x_event_handler(int irq, void *private)
476 {
477 struct iio_dev *indio_dev = private;
478 struct ad799x_state *st = iio_priv(private);
479 int i, ret;
480
481 ret = i2c_smbus_read_byte_data(st->client, AD7998_ALERT_STAT_REG);
482 if (ret <= 0)
483 goto done;
484
485 if (i2c_smbus_write_byte_data(st->client, AD7998_ALERT_STAT_REG,
486 AD7998_ALERT_STAT_CLEAR) < 0)
487 goto done;
488
489 for (i = 0; i < 8; i++) {
490 if (ret & BIT(i))
491 iio_push_event(indio_dev,
492 i & 0x1 ?
493 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
494 (i >> 1),
495 IIO_EV_TYPE_THRESH,
496 IIO_EV_DIR_RISING) :
497 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
498 (i >> 1),
499 IIO_EV_TYPE_THRESH,
500 IIO_EV_DIR_FALLING),
501 iio_get_time_ns(indio_dev));
502 }
503
504 done:
505 return IRQ_HANDLED;
506 }
507
508 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
509 ad799x_read_frequency,
510 ad799x_write_frequency);
511 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("15625 7812 3906 1953 976 488 244 0");
512
513 static struct attribute *ad799x_event_attributes[] = {
514 &iio_dev_attr_sampling_frequency.dev_attr.attr,
515 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
516 NULL,
517 };
518
519 static const struct attribute_group ad799x_event_attrs_group = {
520 .attrs = ad799x_event_attributes,
521 };
522
523 static const struct iio_info ad7991_info = {
524 .read_raw = &ad799x_read_raw,
525 .update_scan_mode = ad799x_update_scan_mode,
526 };
527
528 static const struct iio_info ad7993_4_7_8_noirq_info = {
529 .read_raw = &ad799x_read_raw,
530 .update_scan_mode = ad799x_update_scan_mode,
531 };
532
533 static const struct iio_info ad7993_4_7_8_irq_info = {
534 .read_raw = &ad799x_read_raw,
535 .event_attrs = &ad799x_event_attrs_group,
536 .read_event_config = &ad799x_read_event_config,
537 .write_event_config = &ad799x_write_event_config,
538 .read_event_value = &ad799x_read_event_value,
539 .write_event_value = &ad799x_write_event_value,
540 .update_scan_mode = ad799x_update_scan_mode,
541 };
542
543 static const struct iio_event_spec ad799x_events[] = {
544 {
545 .type = IIO_EV_TYPE_THRESH,
546 .dir = IIO_EV_DIR_RISING,
547 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
548 BIT(IIO_EV_INFO_ENABLE),
549 }, {
550 .type = IIO_EV_TYPE_THRESH,
551 .dir = IIO_EV_DIR_FALLING,
552 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
553 BIT(IIO_EV_INFO_ENABLE),
554 }, {
555 .type = IIO_EV_TYPE_THRESH,
556 .dir = IIO_EV_DIR_EITHER,
557 .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),
558 },
559 };
560
561 #define _AD799X_CHANNEL(_index, _realbits, _ev_spec, _num_ev_spec) { \
562 .type = IIO_VOLTAGE, \
563 .indexed = 1, \
564 .channel = (_index), \
565 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
566 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
567 .scan_index = (_index), \
568 .scan_type = { \
569 .sign = 'u', \
570 .realbits = (_realbits), \
571 .storagebits = 16, \
572 .shift = 12 - (_realbits), \
573 .endianness = IIO_BE, \
574 }, \
575 .event_spec = _ev_spec, \
576 .num_event_specs = _num_ev_spec, \
577 }
578
579 #define AD799X_CHANNEL(_index, _realbits) \
580 _AD799X_CHANNEL(_index, _realbits, NULL, 0)
581
582 #define AD799X_CHANNEL_WITH_EVENTS(_index, _realbits) \
583 _AD799X_CHANNEL(_index, _realbits, ad799x_events, \
584 ARRAY_SIZE(ad799x_events))
585
586 static const struct ad799x_chip_info ad799x_chip_info_tbl[] = {
587 [ad7991] = {
588 .num_channels = 5,
589 .noirq_config = {
590 .channel = {
591 AD799X_CHANNEL(0, 12),
592 AD799X_CHANNEL(1, 12),
593 AD799X_CHANNEL(2, 12),
594 AD799X_CHANNEL(3, 12),
595 IIO_CHAN_SOFT_TIMESTAMP(4),
596 },
597 .info = &ad7991_info,
598 },
599 },
600 [ad7995] = {
601 .num_channels = 5,
602 .noirq_config = {
603 .channel = {
604 AD799X_CHANNEL(0, 10),
605 AD799X_CHANNEL(1, 10),
606 AD799X_CHANNEL(2, 10),
607 AD799X_CHANNEL(3, 10),
608 IIO_CHAN_SOFT_TIMESTAMP(4),
609 },
610 .info = &ad7991_info,
611 },
612 },
613 [ad7999] = {
614 .num_channels = 5,
615 .noirq_config = {
616 .channel = {
617 AD799X_CHANNEL(0, 8),
618 AD799X_CHANNEL(1, 8),
619 AD799X_CHANNEL(2, 8),
620 AD799X_CHANNEL(3, 8),
621 IIO_CHAN_SOFT_TIMESTAMP(4),
622 },
623 .info = &ad7991_info,
624 },
625 },
626 [ad7992] = {
627 .num_channels = 3,
628 .noirq_config = {
629 .channel = {
630 AD799X_CHANNEL(0, 12),
631 AD799X_CHANNEL(1, 12),
632 IIO_CHAN_SOFT_TIMESTAMP(3),
633 },
634 .info = &ad7993_4_7_8_noirq_info,
635 },
636 .irq_config = {
637 .channel = {
638 AD799X_CHANNEL_WITH_EVENTS(0, 12),
639 AD799X_CHANNEL_WITH_EVENTS(1, 12),
640 IIO_CHAN_SOFT_TIMESTAMP(3),
641 },
642 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
643 .info = &ad7993_4_7_8_irq_info,
644 },
645 },
646 [ad7993] = {
647 .num_channels = 5,
648 .noirq_config = {
649 .channel = {
650 AD799X_CHANNEL(0, 10),
651 AD799X_CHANNEL(1, 10),
652 AD799X_CHANNEL(2, 10),
653 AD799X_CHANNEL(3, 10),
654 IIO_CHAN_SOFT_TIMESTAMP(4),
655 },
656 .info = &ad7993_4_7_8_noirq_info,
657 },
658 .irq_config = {
659 .channel = {
660 AD799X_CHANNEL_WITH_EVENTS(0, 10),
661 AD799X_CHANNEL_WITH_EVENTS(1, 10),
662 AD799X_CHANNEL_WITH_EVENTS(2, 10),
663 AD799X_CHANNEL_WITH_EVENTS(3, 10),
664 IIO_CHAN_SOFT_TIMESTAMP(4),
665 },
666 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
667 .info = &ad7993_4_7_8_irq_info,
668 },
669 },
670 [ad7994] = {
671 .num_channels = 5,
672 .noirq_config = {
673 .channel = {
674 AD799X_CHANNEL(0, 12),
675 AD799X_CHANNEL(1, 12),
676 AD799X_CHANNEL(2, 12),
677 AD799X_CHANNEL(3, 12),
678 IIO_CHAN_SOFT_TIMESTAMP(4),
679 },
680 .info = &ad7993_4_7_8_noirq_info,
681 },
682 .irq_config = {
683 .channel = {
684 AD799X_CHANNEL_WITH_EVENTS(0, 12),
685 AD799X_CHANNEL_WITH_EVENTS(1, 12),
686 AD799X_CHANNEL_WITH_EVENTS(2, 12),
687 AD799X_CHANNEL_WITH_EVENTS(3, 12),
688 IIO_CHAN_SOFT_TIMESTAMP(4),
689 },
690 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
691 .info = &ad7993_4_7_8_irq_info,
692 },
693 },
694 [ad7997] = {
695 .num_channels = 9,
696 .noirq_config = {
697 .channel = {
698 AD799X_CHANNEL(0, 10),
699 AD799X_CHANNEL(1, 10),
700 AD799X_CHANNEL(2, 10),
701 AD799X_CHANNEL(3, 10),
702 AD799X_CHANNEL(4, 10),
703 AD799X_CHANNEL(5, 10),
704 AD799X_CHANNEL(6, 10),
705 AD799X_CHANNEL(7, 10),
706 IIO_CHAN_SOFT_TIMESTAMP(8),
707 },
708 .info = &ad7993_4_7_8_noirq_info,
709 },
710 .irq_config = {
711 .channel = {
712 AD799X_CHANNEL_WITH_EVENTS(0, 10),
713 AD799X_CHANNEL_WITH_EVENTS(1, 10),
714 AD799X_CHANNEL_WITH_EVENTS(2, 10),
715 AD799X_CHANNEL_WITH_EVENTS(3, 10),
716 AD799X_CHANNEL(4, 10),
717 AD799X_CHANNEL(5, 10),
718 AD799X_CHANNEL(6, 10),
719 AD799X_CHANNEL(7, 10),
720 IIO_CHAN_SOFT_TIMESTAMP(8),
721 },
722 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
723 .info = &ad7993_4_7_8_irq_info,
724 },
725 },
726 [ad7998] = {
727 .num_channels = 9,
728 .noirq_config = {
729 .channel = {
730 AD799X_CHANNEL(0, 12),
731 AD799X_CHANNEL(1, 12),
732 AD799X_CHANNEL(2, 12),
733 AD799X_CHANNEL(3, 12),
734 AD799X_CHANNEL(4, 12),
735 AD799X_CHANNEL(5, 12),
736 AD799X_CHANNEL(6, 12),
737 AD799X_CHANNEL(7, 12),
738 IIO_CHAN_SOFT_TIMESTAMP(8),
739 },
740 .info = &ad7993_4_7_8_noirq_info,
741 },
742 .irq_config = {
743 .channel = {
744 AD799X_CHANNEL_WITH_EVENTS(0, 12),
745 AD799X_CHANNEL_WITH_EVENTS(1, 12),
746 AD799X_CHANNEL_WITH_EVENTS(2, 12),
747 AD799X_CHANNEL_WITH_EVENTS(3, 12),
748 AD799X_CHANNEL(4, 12),
749 AD799X_CHANNEL(5, 12),
750 AD799X_CHANNEL(6, 12),
751 AD799X_CHANNEL(7, 12),
752 IIO_CHAN_SOFT_TIMESTAMP(8),
753 },
754 .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
755 .info = &ad7993_4_7_8_irq_info,
756 },
757 },
758 };
759
760 static int ad799x_probe(struct i2c_client *client,
761 const struct i2c_device_id *id)
762 {
763 int ret;
764 struct ad799x_state *st;
765 struct iio_dev *indio_dev;
766 const struct ad799x_chip_info *chip_info =
767 &ad799x_chip_info_tbl[id->driver_data];
768
769 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
770 if (indio_dev == NULL)
771 return -ENOMEM;
772
773 st = iio_priv(indio_dev);
774
775 i2c_set_clientdata(client, indio_dev);
776
777 st->id = id->driver_data;
778 if (client->irq > 0 && chip_info->irq_config.info)
779 st->chip_config = &chip_info->irq_config;
780 else
781 st->chip_config = &chip_info->noirq_config;
782
783
784
785 st->reg = devm_regulator_get(&client->dev, "vcc");
786 if (IS_ERR(st->reg))
787 return PTR_ERR(st->reg);
788 ret = regulator_enable(st->reg);
789 if (ret)
790 return ret;
791 st->vref = devm_regulator_get(&client->dev, "vref");
792 if (IS_ERR(st->vref)) {
793 ret = PTR_ERR(st->vref);
794 goto error_disable_reg;
795 }
796 ret = regulator_enable(st->vref);
797 if (ret)
798 goto error_disable_reg;
799
800 st->client = client;
801
802 indio_dev->dev.parent = &client->dev;
803 indio_dev->dev.of_node = client->dev.of_node;
804 indio_dev->name = id->name;
805 indio_dev->info = st->chip_config->info;
806
807 indio_dev->modes = INDIO_DIRECT_MODE;
808 indio_dev->channels = st->chip_config->channel;
809 indio_dev->num_channels = chip_info->num_channels;
810
811 ret = ad799x_write_config(st, st->chip_config->default_config);
812 if (ret < 0)
813 goto error_disable_vref;
814 ret = ad799x_read_config(st);
815 if (ret < 0)
816 goto error_disable_vref;
817 st->config = ret;
818
819 ret = iio_triggered_buffer_setup(indio_dev, NULL,
820 &ad799x_trigger_handler, NULL);
821 if (ret)
822 goto error_disable_vref;
823
824 if (client->irq > 0) {
825 ret = devm_request_threaded_irq(&client->dev,
826 client->irq,
827 NULL,
828 ad799x_event_handler,
829 IRQF_TRIGGER_FALLING |
830 IRQF_ONESHOT,
831 client->name,
832 indio_dev);
833 if (ret)
834 goto error_cleanup_ring;
835 }
836 ret = iio_device_register(indio_dev);
837 if (ret)
838 goto error_cleanup_ring;
839
840 return 0;
841
842 error_cleanup_ring:
843 iio_triggered_buffer_cleanup(indio_dev);
844 error_disable_vref:
845 regulator_disable(st->vref);
846 error_disable_reg:
847 regulator_disable(st->reg);
848
849 return ret;
850 }
851
852 static int ad799x_remove(struct i2c_client *client)
853 {
854 struct iio_dev *indio_dev = i2c_get_clientdata(client);
855 struct ad799x_state *st = iio_priv(indio_dev);
856
857 iio_device_unregister(indio_dev);
858
859 iio_triggered_buffer_cleanup(indio_dev);
860 regulator_disable(st->vref);
861 regulator_disable(st->reg);
862 kfree(st->rx_buf);
863
864 return 0;
865 }
866
867 static const struct i2c_device_id ad799x_id[] = {
868 { "ad7991", ad7991 },
869 { "ad7995", ad7995 },
870 { "ad7999", ad7999 },
871 { "ad7992", ad7992 },
872 { "ad7993", ad7993 },
873 { "ad7994", ad7994 },
874 { "ad7997", ad7997 },
875 { "ad7998", ad7998 },
876 {}
877 };
878
879 MODULE_DEVICE_TABLE(i2c, ad799x_id);
880
881 static struct i2c_driver ad799x_driver = {
882 .driver = {
883 .name = "ad799x",
884 },
885 .probe = ad799x_probe,
886 .remove = ad799x_remove,
887 .id_table = ad799x_id,
888 };
889 module_i2c_driver(ad799x_driver);
890
891 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
892 MODULE_DESCRIPTION("Analog Devices AD799x ADC");
893 MODULE_LICENSE("GPL v2");