root/drivers/iio/adc/stm32-adc-core.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * This file is part of STM32 ADC driver
   4  *
   5  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
   6  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
   7  *
   8  */
   9 
  10 #ifndef __STM32_ADC_H
  11 #define __STM32_ADC_H
  12 
  13 /*
  14  * STM32 - ADC global register map
  15  * ________________________________________________________
  16  * | Offset |                 Register                    |
  17  * --------------------------------------------------------
  18  * | 0x000  |                Master ADC1                  |
  19  * --------------------------------------------------------
  20  * | 0x100  |                Slave ADC2                   |
  21  * --------------------------------------------------------
  22  * | 0x200  |                Slave ADC3                   |
  23  * --------------------------------------------------------
  24  * | 0x300  |         Master & Slave common regs          |
  25  * --------------------------------------------------------
  26  */
  27 #define STM32_ADC_MAX_ADCS              3
  28 #define STM32_ADC_OFFSET                0x100
  29 #define STM32_ADCX_COMN_OFFSET          0x300
  30 
  31 /* STM32F4 - Registers for each ADC instance */
  32 #define STM32F4_ADC_SR                  0x00
  33 #define STM32F4_ADC_CR1                 0x04
  34 #define STM32F4_ADC_CR2                 0x08
  35 #define STM32F4_ADC_SMPR1               0x0C
  36 #define STM32F4_ADC_SMPR2               0x10
  37 #define STM32F4_ADC_HTR                 0x24
  38 #define STM32F4_ADC_LTR                 0x28
  39 #define STM32F4_ADC_SQR1                0x2C
  40 #define STM32F4_ADC_SQR2                0x30
  41 #define STM32F4_ADC_SQR3                0x34
  42 #define STM32F4_ADC_JSQR                0x38
  43 #define STM32F4_ADC_JDR1                0x3C
  44 #define STM32F4_ADC_JDR2                0x40
  45 #define STM32F4_ADC_JDR3                0x44
  46 #define STM32F4_ADC_JDR4                0x48
  47 #define STM32F4_ADC_DR                  0x4C
  48 
  49 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
  50 #define STM32F4_ADC_CSR                 (STM32_ADCX_COMN_OFFSET + 0x00)
  51 #define STM32F4_ADC_CCR                 (STM32_ADCX_COMN_OFFSET + 0x04)
  52 
  53 /* STM32F4_ADC_SR - bit fields */
  54 #define STM32F4_STRT                    BIT(4)
  55 #define STM32F4_EOC                     BIT(1)
  56 
  57 /* STM32F4_ADC_CR1 - bit fields */
  58 #define STM32F4_RES_SHIFT               24
  59 #define STM32F4_RES_MASK                GENMASK(25, 24)
  60 #define STM32F4_SCAN                    BIT(8)
  61 #define STM32F4_EOCIE                   BIT(5)
  62 
  63 /* STM32F4_ADC_CR2 - bit fields */
  64 #define STM32F4_SWSTART                 BIT(30)
  65 #define STM32F4_EXTEN_SHIFT             28
  66 #define STM32F4_EXTEN_MASK              GENMASK(29, 28)
  67 #define STM32F4_EXTSEL_SHIFT            24
  68 #define STM32F4_EXTSEL_MASK             GENMASK(27, 24)
  69 #define STM32F4_EOCS                    BIT(10)
  70 #define STM32F4_DDS                     BIT(9)
  71 #define STM32F4_DMA                     BIT(8)
  72 #define STM32F4_ADON                    BIT(0)
  73 
  74 /* STM32F4_ADC_CSR - bit fields */
  75 #define STM32F4_EOC3                    BIT(17)
  76 #define STM32F4_EOC2                    BIT(9)
  77 #define STM32F4_EOC1                    BIT(1)
  78 
  79 /* STM32F4_ADC_CCR - bit fields */
  80 #define STM32F4_ADC_ADCPRE_SHIFT        16
  81 #define STM32F4_ADC_ADCPRE_MASK         GENMASK(17, 16)
  82 
  83 /* STM32H7 - Registers for each ADC instance */
  84 #define STM32H7_ADC_ISR                 0x00
  85 #define STM32H7_ADC_IER                 0x04
  86 #define STM32H7_ADC_CR                  0x08
  87 #define STM32H7_ADC_CFGR                0x0C
  88 #define STM32H7_ADC_SMPR1               0x14
  89 #define STM32H7_ADC_SMPR2               0x18
  90 #define STM32H7_ADC_PCSEL               0x1C
  91 #define STM32H7_ADC_SQR1                0x30
  92 #define STM32H7_ADC_SQR2                0x34
  93 #define STM32H7_ADC_SQR3                0x38
  94 #define STM32H7_ADC_SQR4                0x3C
  95 #define STM32H7_ADC_DR                  0x40
  96 #define STM32H7_ADC_DIFSEL              0xC0
  97 #define STM32H7_ADC_CALFACT             0xC4
  98 #define STM32H7_ADC_CALFACT2            0xC8
  99 
 100 /* STM32H7 - common registers for all ADC instances */
 101 #define STM32H7_ADC_CSR                 (STM32_ADCX_COMN_OFFSET + 0x00)
 102 #define STM32H7_ADC_CCR                 (STM32_ADCX_COMN_OFFSET + 0x08)
 103 
 104 /* STM32H7_ADC_ISR - bit fields */
 105 #define STM32MP1_VREGREADY              BIT(12)
 106 #define STM32H7_EOC                     BIT(2)
 107 #define STM32H7_ADRDY                   BIT(0)
 108 
 109 /* STM32H7_ADC_IER - bit fields */
 110 #define STM32H7_EOCIE                   STM32H7_EOC
 111 
 112 /* STM32H7_ADC_CR - bit fields */
 113 #define STM32H7_ADCAL                   BIT(31)
 114 #define STM32H7_ADCALDIF                BIT(30)
 115 #define STM32H7_DEEPPWD                 BIT(29)
 116 #define STM32H7_ADVREGEN                BIT(28)
 117 #define STM32H7_LINCALRDYW6             BIT(27)
 118 #define STM32H7_LINCALRDYW5             BIT(26)
 119 #define STM32H7_LINCALRDYW4             BIT(25)
 120 #define STM32H7_LINCALRDYW3             BIT(24)
 121 #define STM32H7_LINCALRDYW2             BIT(23)
 122 #define STM32H7_LINCALRDYW1             BIT(22)
 123 #define STM32H7_ADCALLIN                BIT(16)
 124 #define STM32H7_BOOST                   BIT(8)
 125 #define STM32H7_ADSTP                   BIT(4)
 126 #define STM32H7_ADSTART                 BIT(2)
 127 #define STM32H7_ADDIS                   BIT(1)
 128 #define STM32H7_ADEN                    BIT(0)
 129 
 130 /* STM32H7_ADC_CFGR bit fields */
 131 #define STM32H7_EXTEN_SHIFT             10
 132 #define STM32H7_EXTEN_MASK              GENMASK(11, 10)
 133 #define STM32H7_EXTSEL_SHIFT            5
 134 #define STM32H7_EXTSEL_MASK             GENMASK(9, 5)
 135 #define STM32H7_RES_SHIFT               2
 136 #define STM32H7_RES_MASK                GENMASK(4, 2)
 137 #define STM32H7_DMNGT_SHIFT             0
 138 #define STM32H7_DMNGT_MASK              GENMASK(1, 0)
 139 
 140 enum stm32h7_adc_dmngt {
 141         STM32H7_DMNGT_DR_ONLY,          /* Regular data in DR only */
 142         STM32H7_DMNGT_DMA_ONESHOT,      /* DMA one shot mode */
 143         STM32H7_DMNGT_DFSDM,            /* DFSDM mode */
 144         STM32H7_DMNGT_DMA_CIRC,         /* DMA circular mode */
 145 };
 146 
 147 /* STM32H7_ADC_CALFACT - bit fields */
 148 #define STM32H7_CALFACT_D_SHIFT         16
 149 #define STM32H7_CALFACT_D_MASK          GENMASK(26, 16)
 150 #define STM32H7_CALFACT_S_SHIFT         0
 151 #define STM32H7_CALFACT_S_MASK          GENMASK(10, 0)
 152 
 153 /* STM32H7_ADC_CALFACT2 - bit fields */
 154 #define STM32H7_LINCALFACT_SHIFT        0
 155 #define STM32H7_LINCALFACT_MASK         GENMASK(29, 0)
 156 
 157 /* STM32H7_ADC_CSR - bit fields */
 158 #define STM32H7_EOC_SLV                 BIT(18)
 159 #define STM32H7_EOC_MST                 BIT(2)
 160 
 161 /* STM32H7_ADC_CCR - bit fields */
 162 #define STM32H7_PRESC_SHIFT             18
 163 #define STM32H7_PRESC_MASK              GENMASK(21, 18)
 164 #define STM32H7_CKMODE_SHIFT            16
 165 #define STM32H7_CKMODE_MASK             GENMASK(17, 16)
 166 
 167 /**
 168  * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
 169  * @base:               control registers base cpu addr
 170  * @phys_base:          control registers base physical addr
 171  * @rate:               clock rate used for analog circuitry
 172  * @vref_mv:            vref voltage (mv)
 173  */
 174 struct stm32_adc_common {
 175         void __iomem                    *base;
 176         phys_addr_t                     phys_base;
 177         unsigned long                   rate;
 178         int                             vref_mv;
 179 };
 180 
 181 #endif