This source file includes following definitions.
- adc12138_mode_programming
- adc12138_read_status
- __adc12138_start_conv
- adc12138_start_conv
- adc12138_start_and_read_conv
- adc12138_read_conv_data
- adc12138_wait_eoc
- adc12138_adc_conversion
- adc12138_read_raw
- adc12138_init
- adc12138_trigger_handler
- adc12138_eoc_handler
- adc12138_probe
- adc12138_remove
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10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/completion.h>
13 #include <linux/clk.h>
14 #include <linux/spi/spi.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/buffer.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/triggered_buffer.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/regulator/consumer.h>
21
22 #define ADC12138_MODE_AUTO_CAL 0x08
23 #define ADC12138_MODE_READ_STATUS 0x0c
24 #define ADC12138_MODE_ACQUISITION_TIME_6 0x0e
25 #define ADC12138_MODE_ACQUISITION_TIME_10 0x4e
26 #define ADC12138_MODE_ACQUISITION_TIME_18 0x8e
27 #define ADC12138_MODE_ACQUISITION_TIME_34 0xce
28
29 #define ADC12138_STATUS_CAL BIT(6)
30
31 enum {
32 adc12130,
33 adc12132,
34 adc12138,
35 };
36
37 struct adc12138 {
38 struct spi_device *spi;
39 unsigned int id;
40
41 struct clk *cclk;
42
43 struct regulator *vref_p;
44
45 struct regulator *vref_n;
46 struct mutex lock;
47 struct completion complete;
48
49 unsigned int acquisition_time;
50
51 u8 tx_buf[2] ____cacheline_aligned;
52 u8 rx_buf[2];
53 };
54
55 #define ADC12138_VOLTAGE_CHANNEL(chan) \
56 { \
57 .type = IIO_VOLTAGE, \
58 .indexed = 1, \
59 .channel = chan, \
60 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
61 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
62 | BIT(IIO_CHAN_INFO_OFFSET), \
63 .scan_index = chan, \
64 .scan_type = { \
65 .sign = 's', \
66 .realbits = 13, \
67 .storagebits = 16, \
68 .shift = 3, \
69 .endianness = IIO_BE, \
70 }, \
71 }
72
73 #define ADC12138_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \
74 { \
75 .type = IIO_VOLTAGE, \
76 .indexed = 1, \
77 .channel = (chan1), \
78 .channel2 = (chan2), \
79 .differential = 1, \
80 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
81 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
82 | BIT(IIO_CHAN_INFO_OFFSET), \
83 .scan_index = si, \
84 .scan_type = { \
85 .sign = 's', \
86 .realbits = 13, \
87 .storagebits = 16, \
88 .shift = 3, \
89 .endianness = IIO_BE, \
90 }, \
91 }
92
93 static const struct iio_chan_spec adc12132_channels[] = {
94 ADC12138_VOLTAGE_CHANNEL(0),
95 ADC12138_VOLTAGE_CHANNEL(1),
96 ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
97 ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
98 IIO_CHAN_SOFT_TIMESTAMP(4),
99 };
100
101 static const struct iio_chan_spec adc12138_channels[] = {
102 ADC12138_VOLTAGE_CHANNEL(0),
103 ADC12138_VOLTAGE_CHANNEL(1),
104 ADC12138_VOLTAGE_CHANNEL(2),
105 ADC12138_VOLTAGE_CHANNEL(3),
106 ADC12138_VOLTAGE_CHANNEL(4),
107 ADC12138_VOLTAGE_CHANNEL(5),
108 ADC12138_VOLTAGE_CHANNEL(6),
109 ADC12138_VOLTAGE_CHANNEL(7),
110 ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
111 ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
112 ADC12138_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
113 ADC12138_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
114 ADC12138_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
115 ADC12138_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
116 ADC12138_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
117 ADC12138_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
118 IIO_CHAN_SOFT_TIMESTAMP(16),
119 };
120
121 static int adc12138_mode_programming(struct adc12138 *adc, u8 mode,
122 void *rx_buf, int len)
123 {
124 struct spi_transfer xfer = {
125 .tx_buf = adc->tx_buf,
126 .rx_buf = adc->rx_buf,
127 .len = len,
128 };
129 int ret;
130
131
132 if (adc->id != adc12138)
133 mode = (mode & 0xc0) | ((mode & 0x0f) << 2);
134
135 adc->tx_buf[0] = mode;
136
137 ret = spi_sync_transfer(adc->spi, &xfer, 1);
138 if (ret)
139 return ret;
140
141 memcpy(rx_buf, adc->rx_buf, len);
142
143 return 0;
144 }
145
146 static int adc12138_read_status(struct adc12138 *adc)
147 {
148 u8 rx_buf[2];
149 int ret;
150
151 ret = adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
152 rx_buf, 2);
153 if (ret)
154 return ret;
155
156 return (rx_buf[0] << 1) | (rx_buf[1] >> 7);
157 }
158
159 static int __adc12138_start_conv(struct adc12138 *adc,
160 struct iio_chan_spec const *channel,
161 void *data, int len)
162
163 {
164 static const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 };
165 u8 mode = (ch_to_mux[channel->channel] << 4) |
166 (channel->differential ? 0 : 0x80);
167
168 return adc12138_mode_programming(adc, mode, data, len);
169 }
170
171 static int adc12138_start_conv(struct adc12138 *adc,
172 struct iio_chan_spec const *channel)
173 {
174 u8 trash;
175
176 return __adc12138_start_conv(adc, channel, &trash, 1);
177 }
178
179 static int adc12138_start_and_read_conv(struct adc12138 *adc,
180 struct iio_chan_spec const *channel,
181 __be16 *data)
182 {
183 return __adc12138_start_conv(adc, channel, data, 2);
184 }
185
186 static int adc12138_read_conv_data(struct adc12138 *adc, __be16 *value)
187 {
188
189 return adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,
190 value, sizeof(*value));
191 }
192
193 static int adc12138_wait_eoc(struct adc12138 *adc, unsigned long timeout)
194 {
195 if (!wait_for_completion_timeout(&adc->complete, timeout))
196 return -ETIMEDOUT;
197
198 return 0;
199 }
200
201 static int adc12138_adc_conversion(struct adc12138 *adc,
202 struct iio_chan_spec const *channel,
203 __be16 *value)
204 {
205 int ret;
206
207 reinit_completion(&adc->complete);
208
209 ret = adc12138_start_conv(adc, channel);
210 if (ret)
211 return ret;
212
213 ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
214 if (ret)
215 return ret;
216
217 return adc12138_read_conv_data(adc, value);
218 }
219
220 static int adc12138_read_raw(struct iio_dev *iio,
221 struct iio_chan_spec const *channel, int *value,
222 int *shift, long mask)
223 {
224 struct adc12138 *adc = iio_priv(iio);
225 int ret;
226 __be16 data;
227
228 switch (mask) {
229 case IIO_CHAN_INFO_RAW:
230 mutex_lock(&adc->lock);
231 ret = adc12138_adc_conversion(adc, channel, &data);
232 mutex_unlock(&adc->lock);
233 if (ret)
234 return ret;
235
236 *value = sign_extend32(be16_to_cpu(data) >> 3, 12);
237
238 return IIO_VAL_INT;
239 case IIO_CHAN_INFO_SCALE:
240 ret = regulator_get_voltage(adc->vref_p);
241 if (ret < 0)
242 return ret;
243 *value = ret;
244
245 if (!IS_ERR(adc->vref_n)) {
246 ret = regulator_get_voltage(adc->vref_n);
247 if (ret < 0)
248 return ret;
249 *value -= ret;
250 }
251
252
253 *value /= 1000;
254 *shift = channel->scan_type.realbits - 1;
255
256 return IIO_VAL_FRACTIONAL_LOG2;
257 case IIO_CHAN_INFO_OFFSET:
258 if (!IS_ERR(adc->vref_n)) {
259 *value = regulator_get_voltage(adc->vref_n);
260 if (*value < 0)
261 return *value;
262 } else {
263 *value = 0;
264 }
265
266
267 *value /= 1000;
268
269 return IIO_VAL_INT;
270 }
271
272 return -EINVAL;
273 }
274
275 static const struct iio_info adc12138_info = {
276 .read_raw = adc12138_read_raw,
277 };
278
279 static int adc12138_init(struct adc12138 *adc)
280 {
281 int ret;
282 int status;
283 u8 mode;
284 u8 trash;
285
286 reinit_completion(&adc->complete);
287
288 ret = adc12138_mode_programming(adc, ADC12138_MODE_AUTO_CAL, &trash, 1);
289 if (ret)
290 return ret;
291
292
293 status = adc12138_read_status(adc);
294 if (status < 0)
295 return status;
296
297 adc12138_wait_eoc(adc, msecs_to_jiffies(100));
298
299 status = adc12138_read_status(adc);
300 if (status & ADC12138_STATUS_CAL) {
301 dev_warn(&adc->spi->dev,
302 "Auto Cal sequence is still in progress: %#x\n",
303 status);
304 return -EIO;
305 }
306
307 switch (adc->acquisition_time) {
308 case 6:
309 mode = ADC12138_MODE_ACQUISITION_TIME_6;
310 break;
311 case 10:
312 mode = ADC12138_MODE_ACQUISITION_TIME_10;
313 break;
314 case 18:
315 mode = ADC12138_MODE_ACQUISITION_TIME_18;
316 break;
317 case 34:
318 mode = ADC12138_MODE_ACQUISITION_TIME_34;
319 break;
320 default:
321 return -EINVAL;
322 }
323
324 return adc12138_mode_programming(adc, mode, &trash, 1);
325 }
326
327 static irqreturn_t adc12138_trigger_handler(int irq, void *p)
328 {
329 struct iio_poll_func *pf = p;
330 struct iio_dev *indio_dev = pf->indio_dev;
331 struct adc12138 *adc = iio_priv(indio_dev);
332 __be16 data[20] = { };
333 __be16 trash;
334 int ret;
335 int scan_index;
336 int i = 0;
337
338 mutex_lock(&adc->lock);
339
340 for_each_set_bit(scan_index, indio_dev->active_scan_mask,
341 indio_dev->masklength) {
342 const struct iio_chan_spec *scan_chan =
343 &indio_dev->channels[scan_index];
344
345 reinit_completion(&adc->complete);
346
347 ret = adc12138_start_and_read_conv(adc, scan_chan,
348 i ? &data[i - 1] : &trash);
349 if (ret) {
350 dev_warn(&adc->spi->dev,
351 "failed to start conversion\n");
352 goto out;
353 }
354
355 ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));
356 if (ret) {
357 dev_warn(&adc->spi->dev, "wait eoc timeout\n");
358 goto out;
359 }
360
361 i++;
362 }
363
364 if (i) {
365 ret = adc12138_read_conv_data(adc, &data[i - 1]);
366 if (ret) {
367 dev_warn(&adc->spi->dev,
368 "failed to get conversion data\n");
369 goto out;
370 }
371 }
372
373 iio_push_to_buffers_with_timestamp(indio_dev, data,
374 iio_get_time_ns(indio_dev));
375 out:
376 mutex_unlock(&adc->lock);
377
378 iio_trigger_notify_done(indio_dev->trig);
379
380 return IRQ_HANDLED;
381 }
382
383 static irqreturn_t adc12138_eoc_handler(int irq, void *p)
384 {
385 struct iio_dev *indio_dev = p;
386 struct adc12138 *adc = iio_priv(indio_dev);
387
388 complete(&adc->complete);
389
390 return IRQ_HANDLED;
391 }
392
393 static int adc12138_probe(struct spi_device *spi)
394 {
395 struct iio_dev *indio_dev;
396 struct adc12138 *adc;
397 int ret;
398
399 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
400 if (!indio_dev)
401 return -ENOMEM;
402
403 adc = iio_priv(indio_dev);
404 adc->spi = spi;
405 adc->id = spi_get_device_id(spi)->driver_data;
406 mutex_init(&adc->lock);
407 init_completion(&adc->complete);
408
409 indio_dev->name = spi_get_device_id(spi)->name;
410 indio_dev->dev.parent = &spi->dev;
411 indio_dev->info = &adc12138_info;
412 indio_dev->modes = INDIO_DIRECT_MODE;
413
414 switch (adc->id) {
415 case adc12130:
416 case adc12132:
417 indio_dev->channels = adc12132_channels;
418 indio_dev->num_channels = ARRAY_SIZE(adc12132_channels);
419 break;
420 case adc12138:
421 indio_dev->channels = adc12138_channels;
422 indio_dev->num_channels = ARRAY_SIZE(adc12138_channels);
423 break;
424 default:
425 return -EINVAL;
426 }
427
428 ret = of_property_read_u32(spi->dev.of_node, "ti,acquisition-time",
429 &adc->acquisition_time);
430 if (ret)
431 adc->acquisition_time = 10;
432
433 adc->cclk = devm_clk_get(&spi->dev, NULL);
434 if (IS_ERR(adc->cclk))
435 return PTR_ERR(adc->cclk);
436
437 adc->vref_p = devm_regulator_get(&spi->dev, "vref-p");
438 if (IS_ERR(adc->vref_p))
439 return PTR_ERR(adc->vref_p);
440
441 adc->vref_n = devm_regulator_get_optional(&spi->dev, "vref-n");
442 if (IS_ERR(adc->vref_n)) {
443
444
445
446
447 ret = PTR_ERR(adc->vref_n);
448 if (ret != -ENODEV)
449 return ret;
450 }
451
452 ret = devm_request_irq(&spi->dev, spi->irq, adc12138_eoc_handler,
453 IRQF_TRIGGER_RISING, indio_dev->name, indio_dev);
454 if (ret)
455 return ret;
456
457 ret = clk_prepare_enable(adc->cclk);
458 if (ret)
459 return ret;
460
461 ret = regulator_enable(adc->vref_p);
462 if (ret)
463 goto err_clk_disable;
464
465 if (!IS_ERR(adc->vref_n)) {
466 ret = regulator_enable(adc->vref_n);
467 if (ret)
468 goto err_vref_p_disable;
469 }
470
471 ret = adc12138_init(adc);
472 if (ret)
473 goto err_vref_n_disable;
474
475 spi_set_drvdata(spi, indio_dev);
476
477 ret = iio_triggered_buffer_setup(indio_dev, NULL,
478 adc12138_trigger_handler, NULL);
479 if (ret)
480 goto err_vref_n_disable;
481
482 ret = iio_device_register(indio_dev);
483 if (ret)
484 goto err_buffer_cleanup;
485
486 return 0;
487 err_buffer_cleanup:
488 iio_triggered_buffer_cleanup(indio_dev);
489 err_vref_n_disable:
490 if (!IS_ERR(adc->vref_n))
491 regulator_disable(adc->vref_n);
492 err_vref_p_disable:
493 regulator_disable(adc->vref_p);
494 err_clk_disable:
495 clk_disable_unprepare(adc->cclk);
496
497 return ret;
498 }
499
500 static int adc12138_remove(struct spi_device *spi)
501 {
502 struct iio_dev *indio_dev = spi_get_drvdata(spi);
503 struct adc12138 *adc = iio_priv(indio_dev);
504
505 iio_device_unregister(indio_dev);
506 iio_triggered_buffer_cleanup(indio_dev);
507 if (!IS_ERR(adc->vref_n))
508 regulator_disable(adc->vref_n);
509 regulator_disable(adc->vref_p);
510 clk_disable_unprepare(adc->cclk);
511
512 return 0;
513 }
514
515 #ifdef CONFIG_OF
516
517 static const struct of_device_id adc12138_dt_ids[] = {
518 { .compatible = "ti,adc12130", },
519 { .compatible = "ti,adc12132", },
520 { .compatible = "ti,adc12138", },
521 {}
522 };
523 MODULE_DEVICE_TABLE(of, adc12138_dt_ids);
524
525 #endif
526
527 static const struct spi_device_id adc12138_id[] = {
528 { "adc12130", adc12130 },
529 { "adc12132", adc12132 },
530 { "adc12138", adc12138 },
531 {}
532 };
533 MODULE_DEVICE_TABLE(spi, adc12138_id);
534
535 static struct spi_driver adc12138_driver = {
536 .driver = {
537 .name = "adc12138",
538 .of_match_table = of_match_ptr(adc12138_dt_ids),
539 },
540 .probe = adc12138_probe,
541 .remove = adc12138_remove,
542 .id_table = adc12138_id,
543 };
544 module_spi_driver(adc12138_driver);
545
546 MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
547 MODULE_DESCRIPTION("ADC12130/ADC12132/ADC12138 driver");
548 MODULE_LICENSE("GPL v2");