drivers/iio/adc/xilinx-xadc-core.c

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This source file includes following definitions.
xadc_write_reg
xadc_read_reg
xadc_zynq_write_fifo
xadc_zynq_drain_fifo
xadc_zynq_update_intmsk
xadc_zynq_write_adc_reg
xadc_zynq_read_adc_reg
xadc_zynq_transform_alarm
xadc_zynq_unmask_worker
xadc_zynq_interrupt_handler
xadc_zynq_setup
xadc_zynq_get_dclk_rate
xadc_zynq_update_alarm
xadc_axi_read_adc_reg
xadc_axi_write_adc_reg
xadc_axi_setup
xadc_axi_interrupt_handler
xadc_axi_update_alarm
xadc_axi_get_dclk
_xadc_update_adc_reg
xadc_update_adc_reg
xadc_get_dclk_rate
xadc_update_scan_mode
xadc_scan_index_to_channel
xadc_trigger_handler
xadc_trigger_set_state
xadc_alloc_trigger
xadc_power_adc_b
xadc_get_seq_mode
xadc_postdisable
xadc_preenable
xadc_read_samplerate
xadc_read_raw
xadc_write_samplerate
xadc_write_raw
xadc_parse_dt
xadc_probe
xadc_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Xilinx XADC driver
   4  *
   5  * Copyright 2013-2014 Analog Devices Inc.
   6  *  Author: Lars-Peter Clauen <lars@metafoo.de>
   7  *
   8  * Documentation for the parts can be found at:
   9  *  - XADC hardmacro: Xilinx UG480
  10  *  - ZYNQ XADC interface: Xilinx UG585
  11  *  - AXI XADC interface: Xilinx PG019
  12  */
  13 
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/sysfs.h>
  25 
  26 #include <linux/iio/buffer.h>
  27 #include <linux/iio/events.h>
  28 #include <linux/iio/iio.h>
  29 #include <linux/iio/sysfs.h>
  30 #include <linux/iio/trigger.h>
  31 #include <linux/iio/trigger_consumer.h>
  32 #include <linux/iio/triggered_buffer.h>
  33 
  34 #include "xilinx-xadc.h"
  35 
  36 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
  37 
  38 /* ZYNQ register definitions */
  39 #define XADC_ZYNQ_REG_CFG       0x00
  40 #define XADC_ZYNQ_REG_INTSTS    0x04
  41 #define XADC_ZYNQ_REG_INTMSK    0x08
  42 #define XADC_ZYNQ_REG_STATUS    0x0c
  43 #define XADC_ZYNQ_REG_CFIFO     0x10
  44 #define XADC_ZYNQ_REG_DFIFO     0x14
  45 #define XADC_ZYNQ_REG_CTL               0x18
  46 
  47 #define XADC_ZYNQ_CFG_ENABLE            BIT(31)
  48 #define XADC_ZYNQ_CFG_CFIFOTH_MASK      (0xf << 20)
  49 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET    20
  50 #define XADC_ZYNQ_CFG_DFIFOTH_MASK      (0xf << 16)
  51 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET    16
  52 #define XADC_ZYNQ_CFG_WEDGE             BIT(13)
  53 #define XADC_ZYNQ_CFG_REDGE             BIT(12)
  54 #define XADC_ZYNQ_CFG_TCKRATE_MASK      (0x3 << 8)
  55 #define XADC_ZYNQ_CFG_TCKRATE_DIV2      (0x0 << 8)
  56 #define XADC_ZYNQ_CFG_TCKRATE_DIV4      (0x1 << 8)
  57 #define XADC_ZYNQ_CFG_TCKRATE_DIV8      (0x2 << 8)
  58 #define XADC_ZYNQ_CFG_TCKRATE_DIV16     (0x3 << 8)
  59 #define XADC_ZYNQ_CFG_IGAP_MASK         0x1f
  60 #define XADC_ZYNQ_CFG_IGAP(x)           (x)
  61 
  62 #define XADC_ZYNQ_INT_CFIFO_LTH         BIT(9)
  63 #define XADC_ZYNQ_INT_DFIFO_GTH         BIT(8)
  64 #define XADC_ZYNQ_INT_ALARM_MASK        0xff
  65 #define XADC_ZYNQ_INT_ALARM_OFFSET      0
  66 
  67 #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
  68 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET       16
  69 #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
  70 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET       12
  71 #define XADC_ZYNQ_STATUS_CFIFOF         BIT(11)
  72 #define XADC_ZYNQ_STATUS_CFIFOE         BIT(10)
  73 #define XADC_ZYNQ_STATUS_DFIFOF         BIT(9)
  74 #define XADC_ZYNQ_STATUS_DFIFOE         BIT(8)
  75 #define XADC_ZYNQ_STATUS_OT             BIT(7)
  76 #define XADC_ZYNQ_STATUS_ALM(x)         BIT(x)
  77 
  78 #define XADC_ZYNQ_CTL_RESET             BIT(4)
  79 
  80 #define XADC_ZYNQ_CMD_NOP               0x00
  81 #define XADC_ZYNQ_CMD_READ              0x01
  82 #define XADC_ZYNQ_CMD_WRITE             0x02
  83 
  84 #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
  85 
  86 /* AXI register definitions */
  87 #define XADC_AXI_REG_RESET              0x00
  88 #define XADC_AXI_REG_STATUS             0x04
  89 #define XADC_AXI_REG_ALARM_STATUS       0x08
  90 #define XADC_AXI_REG_CONVST             0x0c
  91 #define XADC_AXI_REG_XADC_RESET         0x10
  92 #define XADC_AXI_REG_GIER               0x5c
  93 #define XADC_AXI_REG_IPISR              0x60
  94 #define XADC_AXI_REG_IPIER              0x68
  95 #define XADC_AXI_ADC_REG_OFFSET         0x200
  96 
  97 #define XADC_AXI_RESET_MAGIC            0xa
  98 #define XADC_AXI_GIER_ENABLE            BIT(31)
  99 
 100 #define XADC_AXI_INT_EOS                BIT(4)
 101 #define XADC_AXI_INT_ALARM_MASK         0x3c0f
 102 
 103 #define XADC_FLAGS_BUFFERED BIT(0)
 104 
 105 /*
 106  * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
 107  * not have a hardware FIFO. Which means an interrupt is generated for each
 108  * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
 109  * overloaded by the interrupts that it soft-lockups. For this reason the driver
 110  * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
 111  * but still responsive.
 112  */
 113 #define XADC_MAX_SAMPLERATE 150000
 114 
 115 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
 116         uint32_t val)
 117 {
 118         writel(val, xadc->base + reg);
 119 }
 120 
 121 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
 122         uint32_t *val)
 123 {
 124         *val = readl(xadc->base + reg);
 125 }
 126 
 127 /*
 128  * The ZYNQ interface uses two asynchronous FIFOs for communication with the
 129  * XADC. Reads and writes to the XADC register are performed by submitting a
 130  * request to the command FIFO (CFIFO), once the request has been completed the
 131  * result can be read from the data FIFO (DFIFO). The method currently used in
 132  * this driver is to submit the request for a read/write operation, then go to
 133  * sleep and wait for an interrupt that signals that a response is available in
 134  * the data FIFO.
 135  */
 136 
 137 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
 138         unsigned int n)
 139 {
 140         unsigned int i;
 141 
 142         for (i = 0; i < n; i++)
 143                 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
 144 }
 145 
 146 static void xadc_zynq_drain_fifo(struct xadc *xadc)
 147 {
 148         uint32_t status, tmp;
 149 
 150         xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 151 
 152         while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
 153                 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 154                 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
 155         }
 156 }
 157 
 158 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
 159         unsigned int val)
 160 {
 161         xadc->zynq_intmask &= ~mask;
 162         xadc->zynq_intmask |= val;
 163 
 164         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
 165                 xadc->zynq_intmask | xadc->zynq_masked_alarm);
 166 }
 167 
 168 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
 169         uint16_t val)
 170 {
 171         uint32_t cmd[1];
 172         uint32_t tmp;
 173         int ret;
 174 
 175         spin_lock_irq(&xadc->lock);
 176         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 177                         XADC_ZYNQ_INT_DFIFO_GTH);
 178 
 179         reinit_completion(&xadc->completion);
 180 
 181         cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
 182         xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
 183         xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
 184         tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
 185         tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
 186         xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 187 
 188         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
 189         spin_unlock_irq(&xadc->lock);
 190 
 191         ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 192         if (ret == 0)
 193                 ret = -EIO;
 194         else
 195                 ret = 0;
 196 
 197         xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
 198 
 199         return ret;
 200 }
 201 
 202 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
 203         uint16_t *val)
 204 {
 205         uint32_t cmd[2];
 206         uint32_t resp, tmp;
 207         int ret;
 208 
 209         cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
 210         cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
 211 
 212         spin_lock_irq(&xadc->lock);
 213         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 214                         XADC_ZYNQ_INT_DFIFO_GTH);
 215         xadc_zynq_drain_fifo(xadc);
 216         reinit_completion(&xadc->completion);
 217 
 218         xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
 219         xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
 220         tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
 221         tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
 222         xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
 223 
 224         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
 225         spin_unlock_irq(&xadc->lock);
 226         ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
 227         if (ret == 0)
 228                 ret = -EIO;
 229         if (ret < 0)
 230                 return ret;
 231 
 232         xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 233         xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
 234 
 235         *val = resp & 0xffff;
 236 
 237         return 0;
 238 }
 239 
 240 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
 241 {
 242         return ((alarm & 0x80) >> 4) |
 243                 ((alarm & 0x78) << 1) |
 244                 (alarm & 0x07);
 245 }
 246 
 247 /*
 248  * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
 249  * threshold condition go way from within the interrupt handler, this means as
 250  * soon as a threshold condition is present we would enter the interrupt handler
 251  * again and again. To work around this we mask all active thresholds interrupts
 252  * in the interrupt handler and start a timer. In this timer we poll the
 253  * interrupt status and only if the interrupt is inactive we unmask it again.
 254  */
 255 static void xadc_zynq_unmask_worker(struct work_struct *work)
 256 {
 257         struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
 258         unsigned int misc_sts, unmask;
 259 
 260         xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
 261 
 262         misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
 263 
 264         spin_lock_irq(&xadc->lock);
 265 
 266         /* Clear those bits which are not active anymore */
 267         unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
 268         xadc->zynq_masked_alarm &= misc_sts;
 269 
 270         /* Also clear those which are masked out anyway */
 271         xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
 272 
 273         /* Clear the interrupts before we unmask them */
 274         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
 275 
 276         xadc_zynq_update_intmsk(xadc, 0, 0);
 277 
 278         spin_unlock_irq(&xadc->lock);
 279 
 280         /* if still pending some alarm re-trigger the timer */
 281         if (xadc->zynq_masked_alarm) {
 282                 schedule_delayed_work(&xadc->zynq_unmask_work,
 283                                 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
 284         }
 285 
 286 }
 287 
 288 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
 289 {
 290         struct iio_dev *indio_dev = devid;
 291         struct xadc *xadc = iio_priv(indio_dev);
 292         uint32_t status;
 293 
 294         xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 295 
 296         status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
 297 
 298         if (!status)
 299                 return IRQ_NONE;
 300 
 301         spin_lock(&xadc->lock);
 302 
 303         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
 304 
 305         if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
 306                 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
 307                         XADC_ZYNQ_INT_DFIFO_GTH);
 308                 complete(&xadc->completion);
 309         }
 310 
 311         status &= XADC_ZYNQ_INT_ALARM_MASK;
 312         if (status) {
 313                 xadc->zynq_masked_alarm |= status;
 314                 /*
 315                  * mask the current event interrupt,
 316                  * unmask it when the interrupt is no more active.
 317                  */
 318                 xadc_zynq_update_intmsk(xadc, 0, 0);
 319 
 320                 xadc_handle_events(indio_dev,
 321                                 xadc_zynq_transform_alarm(status));
 322 
 323                 /* unmask the required interrupts in timer. */
 324                 schedule_delayed_work(&xadc->zynq_unmask_work,
 325                                 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
 326         }
 327         spin_unlock(&xadc->lock);
 328 
 329         return IRQ_HANDLED;
 330 }
 331 
 332 #define XADC_ZYNQ_TCK_RATE_MAX 50000000
 333 #define XADC_ZYNQ_IGAP_DEFAULT 20
 334 #define XADC_ZYNQ_PCAP_RATE_MAX 200000000
 335 
 336 static int xadc_zynq_setup(struct platform_device *pdev,
 337         struct iio_dev *indio_dev, int irq)
 338 {
 339         struct xadc *xadc = iio_priv(indio_dev);
 340         unsigned long pcap_rate;
 341         unsigned int tck_div;
 342         unsigned int div;
 343         unsigned int igap;
 344         unsigned int tck_rate;
 345         int ret;
 346 
 347         /* TODO: Figure out how to make igap and tck_rate configurable */
 348         igap = XADC_ZYNQ_IGAP_DEFAULT;
 349         tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
 350 
 351         xadc->zynq_intmask = ~0;
 352 
 353         pcap_rate = clk_get_rate(xadc->clk);
 354         if (!pcap_rate)
 355                 return -EINVAL;
 356 
 357         if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
 358                 ret = clk_set_rate(xadc->clk,
 359                                    (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
 360                 if (ret)
 361                         return ret;
 362         }
 363 
 364         if (tck_rate > pcap_rate / 2) {
 365                 div = 2;
 366         } else {
 367                 div = pcap_rate / tck_rate;
 368                 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
 369                         div++;
 370         }
 371 
 372         if (div <= 3)
 373                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
 374         else if (div <= 7)
 375                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
 376         else if (div <= 15)
 377                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
 378         else
 379                 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
 380 
 381         xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
 382         xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
 383         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
 384         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
 385         xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
 386                         XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
 387                         tck_div | XADC_ZYNQ_CFG_IGAP(igap));
 388 
 389         if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
 390                 ret = clk_set_rate(xadc->clk, pcap_rate);
 391                 if (ret)
 392                         return ret;
 393         }
 394 
 395         return 0;
 396 }
 397 
 398 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
 399 {
 400         unsigned int div;
 401         uint32_t val;
 402 
 403         xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
 404 
 405         switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
 406         case XADC_ZYNQ_CFG_TCKRATE_DIV4:
 407                 div = 4;
 408                 break;
 409         case XADC_ZYNQ_CFG_TCKRATE_DIV8:
 410                 div = 8;
 411                 break;
 412         case XADC_ZYNQ_CFG_TCKRATE_DIV16:
 413                 div = 16;
 414                 break;
 415         default:
 416                 div = 2;
 417                 break;
 418         }
 419 
 420         return clk_get_rate(xadc->clk) / div;
 421 }
 422 
 423 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
 424 {
 425         unsigned long flags;
 426         uint32_t status;
 427 
 428         /* Move OT to bit 7 */
 429         alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
 430 
 431         spin_lock_irqsave(&xadc->lock, flags);
 432 
 433         /* Clear previous interrupts if any. */
 434         xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
 435         xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
 436 
 437         xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
 438                 ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
 439 
 440         spin_unlock_irqrestore(&xadc->lock, flags);
 441 }
 442 
 443 static const struct xadc_ops xadc_zynq_ops = {
 444         .read = xadc_zynq_read_adc_reg,
 445         .write = xadc_zynq_write_adc_reg,
 446         .setup = xadc_zynq_setup,
 447         .get_dclk_rate = xadc_zynq_get_dclk_rate,
 448         .interrupt_handler = xadc_zynq_interrupt_handler,
 449         .update_alarm = xadc_zynq_update_alarm,
 450 };
 451 
 452 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
 453         uint16_t *val)
 454 {
 455         uint32_t val32;
 456 
 457         xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32);
 458         *val = val32 & 0xffff;
 459 
 460         return 0;
 461 }
 462 
 463 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
 464         uint16_t val)
 465 {
 466         xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val);
 467 
 468         return 0;
 469 }
 470 
 471 static int xadc_axi_setup(struct platform_device *pdev,
 472         struct iio_dev *indio_dev, int irq)
 473 {
 474         struct xadc *xadc = iio_priv(indio_dev);
 475 
 476         xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
 477         xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
 478 
 479         return 0;
 480 }
 481 
 482 static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
 483 {
 484         struct iio_dev *indio_dev = devid;
 485         struct xadc *xadc = iio_priv(indio_dev);
 486         uint32_t status, mask;
 487         unsigned int events;
 488 
 489         xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
 490         xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
 491         status &= mask;
 492 
 493         if (!status)
 494                 return IRQ_NONE;
 495 
 496         if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
 497                 iio_trigger_poll(xadc->trigger);
 498 
 499         if (status & XADC_AXI_INT_ALARM_MASK) {
 500                 /*
 501                  * The order of the bits in the AXI-XADC status register does
 502                  * not match the order of the bits in the XADC alarm enable
 503                  * register. xadc_handle_events() expects the events to be in
 504                  * the same order as the XADC alarm enable register.
 505                  */
 506                 events = (status & 0x000e) >> 1;
 507                 events |= (status & 0x0001) << 3;
 508                 events |= (status & 0x3c00) >> 6;
 509                 xadc_handle_events(indio_dev, events);
 510         }
 511 
 512         xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
 513 
 514         return IRQ_HANDLED;
 515 }
 516 
 517 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
 518 {
 519         uint32_t val;
 520         unsigned long flags;
 521 
 522         /*
 523          * The order of the bits in the AXI-XADC status register does not match
 524          * the order of the bits in the XADC alarm enable register. We get
 525          * passed the alarm mask in the same order as in the XADC alarm enable
 526          * register.
 527          */
 528         alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
 529                         ((alarm & 0xf0) << 6);
 530 
 531         spin_lock_irqsave(&xadc->lock, flags);
 532         xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
 533         val &= ~XADC_AXI_INT_ALARM_MASK;
 534         val |= alarm;
 535         xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
 536         spin_unlock_irqrestore(&xadc->lock, flags);
 537 }
 538 
 539 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
 540 {
 541         return clk_get_rate(xadc->clk);
 542 }
 543 
 544 static const struct xadc_ops xadc_axi_ops = {
 545         .read = xadc_axi_read_adc_reg,
 546         .write = xadc_axi_write_adc_reg,
 547         .setup = xadc_axi_setup,
 548         .get_dclk_rate = xadc_axi_get_dclk,
 549         .update_alarm = xadc_axi_update_alarm,
 550         .interrupt_handler = xadc_axi_interrupt_handler,
 551         .flags = XADC_FLAGS_BUFFERED,
 552 };
 553 
 554 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
 555         uint16_t mask, uint16_t val)
 556 {
 557         uint16_t tmp;
 558         int ret;
 559 
 560         ret = _xadc_read_adc_reg(xadc, reg, &tmp);
 561         if (ret)
 562                 return ret;
 563 
 564         return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
 565 }
 566 
 567 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
 568         uint16_t mask, uint16_t val)
 569 {
 570         int ret;
 571 
 572         mutex_lock(&xadc->mutex);
 573         ret = _xadc_update_adc_reg(xadc, reg, mask, val);
 574         mutex_unlock(&xadc->mutex);
 575 
 576         return ret;
 577 }
 578 
 579 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
 580 {
 581         return xadc->ops->get_dclk_rate(xadc);
 582 }
 583 
 584 static int xadc_update_scan_mode(struct iio_dev *indio_dev,
 585         const unsigned long *mask)
 586 {
 587         struct xadc *xadc = iio_priv(indio_dev);
 588         unsigned int n;
 589 
 590         n = bitmap_weight(mask, indio_dev->masklength);
 591 
 592         kfree(xadc->data);
 593         xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL);
 594         if (!xadc->data)
 595                 return -ENOMEM;
 596 
 597         return 0;
 598 }
 599 
 600 static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
 601 {
 602         switch (scan_index) {
 603         case 5:
 604                 return XADC_REG_VCCPINT;
 605         case 6:
 606                 return XADC_REG_VCCPAUX;
 607         case 7:
 608                 return XADC_REG_VCCO_DDR;
 609         case 8:
 610                 return XADC_REG_TEMP;
 611         case 9:
 612                 return XADC_REG_VCCINT;
 613         case 10:
 614                 return XADC_REG_VCCAUX;
 615         case 11:
 616                 return XADC_REG_VPVN;
 617         case 12:
 618                 return XADC_REG_VREFP;
 619         case 13:
 620                 return XADC_REG_VREFN;
 621         case 14:
 622                 return XADC_REG_VCCBRAM;
 623         default:
 624                 return XADC_REG_VAUX(scan_index - 16);
 625         }
 626 }
 627 
 628 static irqreturn_t xadc_trigger_handler(int irq, void *p)
 629 {
 630         struct iio_poll_func *pf = p;
 631         struct iio_dev *indio_dev = pf->indio_dev;
 632         struct xadc *xadc = iio_priv(indio_dev);
 633         unsigned int chan;
 634         int i, j;
 635 
 636         if (!xadc->data)
 637                 goto out;
 638 
 639         j = 0;
 640         for_each_set_bit(i, indio_dev->active_scan_mask,
 641                 indio_dev->masklength) {
 642                 chan = xadc_scan_index_to_channel(i);
 643                 xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
 644                 j++;
 645         }
 646 
 647         iio_push_to_buffers(indio_dev, xadc->data);
 648 
 649 out:
 650         iio_trigger_notify_done(indio_dev->trig);
 651 
 652         return IRQ_HANDLED;
 653 }
 654 
 655 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
 656 {
 657         struct xadc *xadc = iio_trigger_get_drvdata(trigger);
 658         unsigned long flags;
 659         unsigned int convst;
 660         unsigned int val;
 661         int ret = 0;
 662 
 663         mutex_lock(&xadc->mutex);
 664 
 665         if (state) {
 666                 /* Only one of the two triggers can be active at the a time. */
 667                 if (xadc->trigger != NULL) {
 668                         ret = -EBUSY;
 669                         goto err_out;
 670                 } else {
 671                         xadc->trigger = trigger;
 672                         if (trigger == xadc->convst_trigger)
 673                                 convst = XADC_CONF0_EC;
 674                         else
 675                                 convst = 0;
 676                 }
 677                 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
 678                                         convst);
 679                 if (ret)
 680                         goto err_out;
 681         } else {
 682                 xadc->trigger = NULL;
 683         }
 684 
 685         spin_lock_irqsave(&xadc->lock, flags);
 686         xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
 687         xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
 688         if (state)
 689                 val |= XADC_AXI_INT_EOS;
 690         else
 691                 val &= ~XADC_AXI_INT_EOS;
 692         xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
 693         spin_unlock_irqrestore(&xadc->lock, flags);
 694 
 695 err_out:
 696         mutex_unlock(&xadc->mutex);
 697 
 698         return ret;
 699 }
 700 
 701 static const struct iio_trigger_ops xadc_trigger_ops = {
 702         .set_trigger_state = &xadc_trigger_set_state,
 703 };
 704 
 705 static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
 706         const char *name)
 707 {
 708         struct iio_trigger *trig;
 709         int ret;
 710 
 711         trig = iio_trigger_alloc("%s%d-%s", indio_dev->name,
 712                                 indio_dev->id, name);
 713         if (trig == NULL)
 714                 return ERR_PTR(-ENOMEM);
 715 
 716         trig->dev.parent = indio_dev->dev.parent;
 717         trig->ops = &xadc_trigger_ops;
 718         iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
 719 
 720         ret = iio_trigger_register(trig);
 721         if (ret)
 722                 goto error_free_trig;
 723 
 724         return trig;
 725 
 726 error_free_trig:
 727         iio_trigger_free(trig);
 728         return ERR_PTR(ret);
 729 }
 730 
 731 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
 732 {
 733         uint16_t val;
 734 
 735         /* Powerdown the ADC-B when it is not needed. */
 736         switch (seq_mode) {
 737         case XADC_CONF1_SEQ_SIMULTANEOUS:
 738         case XADC_CONF1_SEQ_INDEPENDENT:
 739                 val = 0;
 740                 break;
 741         default:
 742                 val = XADC_CONF2_PD_ADC_B;
 743                 break;
 744         }
 745 
 746         return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
 747                 val);
 748 }
 749 
 750 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
 751 {
 752         unsigned int aux_scan_mode = scan_mode >> 16;
 753 
 754         if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
 755                 return XADC_CONF1_SEQ_SIMULTANEOUS;
 756 
 757         if ((aux_scan_mode & 0xff00) == 0 ||
 758                 (aux_scan_mode & 0x00ff) == 0)
 759                 return XADC_CONF1_SEQ_CONTINUOUS;
 760 
 761         return XADC_CONF1_SEQ_SIMULTANEOUS;
 762 }
 763 
 764 static int xadc_postdisable(struct iio_dev *indio_dev)
 765 {
 766         struct xadc *xadc = iio_priv(indio_dev);
 767         unsigned long scan_mask;
 768         int ret;
 769         int i;
 770 
 771         scan_mask = 1; /* Run calibration as part of the sequence */
 772         for (i = 0; i < indio_dev->num_channels; i++)
 773                 scan_mask |= BIT(indio_dev->channels[i].scan_index);
 774 
 775         /* Enable all channels and calibration */
 776         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
 777         if (ret)
 778                 return ret;
 779 
 780         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
 781         if (ret)
 782                 return ret;
 783 
 784         ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 785                 XADC_CONF1_SEQ_CONTINUOUS);
 786         if (ret)
 787                 return ret;
 788 
 789         return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
 790 }
 791 
 792 static int xadc_preenable(struct iio_dev *indio_dev)
 793 {
 794         struct xadc *xadc = iio_priv(indio_dev);
 795         unsigned long scan_mask;
 796         int seq_mode;
 797         int ret;
 798 
 799         ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 800                 XADC_CONF1_SEQ_DEFAULT);
 801         if (ret)
 802                 goto err;
 803 
 804         scan_mask = *indio_dev->active_scan_mask;
 805         seq_mode = xadc_get_seq_mode(xadc, scan_mask);
 806 
 807         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
 808         if (ret)
 809                 goto err;
 810 
 811         /*
 812          * In simultaneous mode the upper and lower aux channels are samples at
 813          * the same time. In this mode the upper 8 bits in the sequencer
 814          * register are don't care and the lower 8 bits control two channels
 815          * each. As such we must set the bit if either the channel in the lower
 816          * group or the upper group is enabled.
 817          */
 818         if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
 819                 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
 820 
 821         ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
 822         if (ret)
 823                 goto err;
 824 
 825         ret = xadc_power_adc_b(xadc, seq_mode);
 826         if (ret)
 827                 goto err;
 828 
 829         ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
 830                 seq_mode);
 831         if (ret)
 832                 goto err;
 833 
 834         return 0;
 835 err:
 836         xadc_postdisable(indio_dev);
 837         return ret;
 838 }
 839 
 840 static const struct iio_buffer_setup_ops xadc_buffer_ops = {
 841         .preenable = &xadc_preenable,
 842         .postenable = &iio_triggered_buffer_postenable,
 843         .predisable = &iio_triggered_buffer_predisable,
 844         .postdisable = &xadc_postdisable,
 845 };
 846 
 847 static int xadc_read_samplerate(struct xadc *xadc)
 848 {
 849         unsigned int div;
 850         uint16_t val16;
 851         int ret;
 852 
 853         ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
 854         if (ret)
 855                 return ret;
 856 
 857         div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
 858         if (div < 2)
 859                 div = 2;
 860 
 861         return xadc_get_dclk_rate(xadc) / div / 26;
 862 }
 863 
 864 static int xadc_read_raw(struct iio_dev *indio_dev,
 865         struct iio_chan_spec const *chan, int *val, int *val2, long info)
 866 {
 867         struct xadc *xadc = iio_priv(indio_dev);
 868         uint16_t val16;
 869         int ret;
 870 
 871         switch (info) {
 872         case IIO_CHAN_INFO_RAW:
 873                 if (iio_buffer_enabled(indio_dev))
 874                         return -EBUSY;
 875                 ret = xadc_read_adc_reg(xadc, chan->address, &val16);
 876                 if (ret < 0)
 877                         return ret;
 878 
 879                 val16 >>= 4;
 880                 if (chan->scan_type.sign == 'u')
 881                         *val = val16;
 882                 else
 883                         *val = sign_extend32(val16, 11);
 884 
 885                 return IIO_VAL_INT;
 886         case IIO_CHAN_INFO_SCALE:
 887                 switch (chan->type) {
 888                 case IIO_VOLTAGE:
 889                         /* V = (val * 3.0) / 4096 */
 890                         switch (chan->address) {
 891                         case XADC_REG_VCCINT:
 892                         case XADC_REG_VCCAUX:
 893                         case XADC_REG_VREFP:
 894                         case XADC_REG_VREFN:
 895                         case XADC_REG_VCCBRAM:
 896                         case XADC_REG_VCCPINT:
 897                         case XADC_REG_VCCPAUX:
 898                         case XADC_REG_VCCO_DDR:
 899                                 *val = 3000;
 900                                 break;
 901                         default:
 902                                 *val = 1000;
 903                                 break;
 904                         }
 905                         *val2 = 12;
 906                         return IIO_VAL_FRACTIONAL_LOG2;
 907                 case IIO_TEMP:
 908                         /* Temp in C = (val * 503.975) / 4096 - 273.15 */
 909                         *val = 503975;
 910                         *val2 = 12;
 911                         return IIO_VAL_FRACTIONAL_LOG2;
 912                 default:
 913                         return -EINVAL;
 914                 }
 915         case IIO_CHAN_INFO_OFFSET:
 916                 /* Only the temperature channel has an offset */
 917                 *val = -((273150 << 12) / 503975);
 918                 return IIO_VAL_INT;
 919         case IIO_CHAN_INFO_SAMP_FREQ:
 920                 ret = xadc_read_samplerate(xadc);
 921                 if (ret < 0)
 922                         return ret;
 923 
 924                 *val = ret;
 925                 return IIO_VAL_INT;
 926         default:
 927                 return -EINVAL;
 928         }
 929 }
 930 
 931 static int xadc_write_samplerate(struct xadc *xadc, int val)
 932 {
 933         unsigned long clk_rate = xadc_get_dclk_rate(xadc);
 934         unsigned int div;
 935 
 936         if (!clk_rate)
 937                 return -EINVAL;
 938 
 939         if (val <= 0)
 940                 return -EINVAL;
 941 
 942         /* Max. 150 kSPS */
 943         if (val > XADC_MAX_SAMPLERATE)
 944                 val = XADC_MAX_SAMPLERATE;
 945 
 946         val *= 26;
 947 
 948         /* Min 1MHz */
 949         if (val < 1000000)
 950                 val = 1000000;
 951 
 952         /*
 953          * We want to round down, but only if we do not exceed the 150 kSPS
 954          * limit.
 955          */
 956         div = clk_rate / val;
 957         if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
 958                 div++;
 959         if (div < 2)
 960                 div = 2;
 961         else if (div > 0xff)
 962                 div = 0xff;
 963 
 964         return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
 965                 div << XADC_CONF2_DIV_OFFSET);
 966 }
 967 
 968 static int xadc_write_raw(struct iio_dev *indio_dev,
 969         struct iio_chan_spec const *chan, int val, int val2, long info)
 970 {
 971         struct xadc *xadc = iio_priv(indio_dev);
 972 
 973         if (info != IIO_CHAN_INFO_SAMP_FREQ)
 974                 return -EINVAL;
 975 
 976         return xadc_write_samplerate(xadc, val);
 977 }
 978 
 979 static const struct iio_event_spec xadc_temp_events[] = {
 980         {
 981                 .type = IIO_EV_TYPE_THRESH,
 982                 .dir = IIO_EV_DIR_RISING,
 983                 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
 984                                 BIT(IIO_EV_INFO_VALUE) |
 985                                 BIT(IIO_EV_INFO_HYSTERESIS),
 986         },
 987 };
 988 
 989 /* Separate values for upper and lower thresholds, but only a shared enabled */
 990 static const struct iio_event_spec xadc_voltage_events[] = {
 991         {
 992                 .type = IIO_EV_TYPE_THRESH,
 993                 .dir = IIO_EV_DIR_RISING,
 994                 .mask_separate = BIT(IIO_EV_INFO_VALUE),
 995         }, {
 996                 .type = IIO_EV_TYPE_THRESH,
 997                 .dir = IIO_EV_DIR_FALLING,
 998                 .mask_separate = BIT(IIO_EV_INFO_VALUE),
 999         }, {
1000                 .type = IIO_EV_TYPE_THRESH,
1001                 .dir = IIO_EV_DIR_EITHER,
1002                 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1003         },
1004 };
1005 
1006 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \
1007         .type = IIO_TEMP, \
1008         .indexed = 1, \
1009         .channel = (_chan), \
1010         .address = (_addr), \
1011         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1012                 BIT(IIO_CHAN_INFO_SCALE) | \
1013                 BIT(IIO_CHAN_INFO_OFFSET), \
1014         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1015         .event_spec = xadc_temp_events, \
1016         .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1017         .scan_index = (_scan_index), \
1018         .scan_type = { \
1019                 .sign = 'u', \
1020                 .realbits = 12, \
1021                 .storagebits = 16, \
1022                 .shift = 4, \
1023                 .endianness = IIO_CPU, \
1024         }, \
1025 }
1026 
1027 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \
1028         .type = IIO_VOLTAGE, \
1029         .indexed = 1, \
1030         .channel = (_chan), \
1031         .address = (_addr), \
1032         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1033                 BIT(IIO_CHAN_INFO_SCALE), \
1034         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1035         .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1036         .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1037         .scan_index = (_scan_index), \
1038         .scan_type = { \
1039                 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1040                 .realbits = 12, \
1041                 .storagebits = 16, \
1042                 .shift = 4, \
1043                 .endianness = IIO_CPU, \
1044         }, \
1045         .extend_name = _ext, \
1046 }
1047 
1048 static const struct iio_chan_spec xadc_channels[] = {
1049         XADC_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1050         XADC_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1051         XADC_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1052         XADC_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1053         XADC_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1054         XADC_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1055         XADC_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1056         XADC_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1057         XADC_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1058         XADC_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1059         XADC_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1060         XADC_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1061         XADC_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1062         XADC_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1063         XADC_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1064         XADC_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1065         XADC_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1066         XADC_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1067         XADC_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1068         XADC_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1069         XADC_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1070         XADC_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1071         XADC_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1072         XADC_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1073         XADC_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1074         XADC_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1075 };
1076 
1077 static const struct iio_info xadc_info = {
1078         .read_raw = &xadc_read_raw,
1079         .write_raw = &xadc_write_raw,
1080         .read_event_config = &xadc_read_event_config,
1081         .write_event_config = &xadc_write_event_config,
1082         .read_event_value = &xadc_read_event_value,
1083         .write_event_value = &xadc_write_event_value,
1084         .update_scan_mode = &xadc_update_scan_mode,
1085 };
1086 
1087 static const struct of_device_id xadc_of_match_table[] = {
1088         { .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops },
1089         { .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops },
1090         { },
1091 };
1092 MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1093 
1094 static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
1095         unsigned int *conf)
1096 {
1097         struct xadc *xadc = iio_priv(indio_dev);
1098         struct iio_chan_spec *channels, *chan;
1099         struct device_node *chan_node, *child;
1100         unsigned int num_channels;
1101         const char *external_mux;
1102         u32 ext_mux_chan;
1103         u32 reg;
1104         int ret;
1105 
1106         *conf = 0;
1107 
1108         ret = of_property_read_string(np, "xlnx,external-mux", &external_mux);
1109         if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1110                 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1111         else if (strcasecmp(external_mux, "single") == 0)
1112                 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1113         else if (strcasecmp(external_mux, "dual") == 0)
1114                 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1115         else
1116                 return -EINVAL;
1117 
1118         if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1119                 ret = of_property_read_u32(np, "xlnx,external-mux-channel",
1120                                         &ext_mux_chan);
1121                 if (ret < 0)
1122                         return ret;
1123 
1124                 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1125                         if (ext_mux_chan == 0)
1126                                 ext_mux_chan = XADC_REG_VPVN;
1127                         else if (ext_mux_chan <= 16)
1128                                 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1129                         else
1130                                 return -EINVAL;
1131                 } else {
1132                         if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1133                                 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1134                         else
1135                                 return -EINVAL;
1136                 }
1137 
1138                 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1139         }
1140 
1141         channels = kmemdup(xadc_channels, sizeof(xadc_channels), GFP_KERNEL);
1142         if (!channels)
1143                 return -ENOMEM;
1144 
1145         num_channels = 9;
1146         chan = &channels[9];
1147 
1148         chan_node = of_get_child_by_name(np, "xlnx,channels");
1149         if (chan_node) {
1150                 for_each_child_of_node(chan_node, child) {
1151                         if (num_channels >= ARRAY_SIZE(xadc_channels)) {
1152                                 of_node_put(child);
1153                                 break;
1154                         }
1155 
1156                         ret = of_property_read_u32(child, "reg", &reg);
1157                         if (ret || reg > 16)
1158                                 continue;
1159 
1160                         if (of_property_read_bool(child, "xlnx,bipolar"))
1161                                 chan->scan_type.sign = 's';
1162 
1163                         if (reg == 0) {
1164                                 chan->scan_index = 11;
1165                                 chan->address = XADC_REG_VPVN;
1166                         } else {
1167                                 chan->scan_index = 15 + reg;
1168                                 chan->address = XADC_REG_VAUX(reg - 1);
1169                         }
1170                         num_channels++;
1171                         chan++;
1172                 }
1173         }
1174         of_node_put(chan_node);
1175 
1176         indio_dev->num_channels = num_channels;
1177         indio_dev->channels = krealloc(channels, sizeof(*channels) *
1178                                         num_channels, GFP_KERNEL);
1179         /* If we can't resize the channels array, just use the original */
1180         if (!indio_dev->channels)
1181                 indio_dev->channels = channels;
1182 
1183         return 0;
1184 }
1185 
1186 static int xadc_probe(struct platform_device *pdev)
1187 {
1188         const struct of_device_id *id;
1189         struct iio_dev *indio_dev;
1190         unsigned int bipolar_mask;
1191         struct resource *mem;
1192         unsigned int conf0;
1193         struct xadc *xadc;
1194         int ret;
1195         int irq;
1196         int i;
1197 
1198         if (!pdev->dev.of_node)
1199                 return -ENODEV;
1200 
1201         id = of_match_node(xadc_of_match_table, pdev->dev.of_node);
1202         if (!id)
1203                 return -EINVAL;
1204 
1205         irq = platform_get_irq(pdev, 0);
1206         if (irq <= 0)
1207                 return -ENXIO;
1208 
1209         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc));
1210         if (!indio_dev)
1211                 return -ENOMEM;
1212 
1213         xadc = iio_priv(indio_dev);
1214         xadc->ops = id->data;
1215         xadc->irq = irq;
1216         init_completion(&xadc->completion);
1217         mutex_init(&xadc->mutex);
1218         spin_lock_init(&xadc->lock);
1219         INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1220 
1221         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1222         xadc->base = devm_ioremap_resource(&pdev->dev, mem);
1223         if (IS_ERR(xadc->base))
1224                 return PTR_ERR(xadc->base);
1225 
1226         indio_dev->dev.parent = &pdev->dev;
1227         indio_dev->dev.of_node = pdev->dev.of_node;
1228         indio_dev->name = "xadc";
1229         indio_dev->modes = INDIO_DIRECT_MODE;
1230         indio_dev->info = &xadc_info;
1231 
1232         ret = xadc_parse_dt(indio_dev, pdev->dev.of_node, &conf0);
1233         if (ret)
1234                 goto err_device_free;
1235 
1236         if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1237                 ret = iio_triggered_buffer_setup(indio_dev,
1238                         &iio_pollfunc_store_time, &xadc_trigger_handler,
1239                         &xadc_buffer_ops);
1240                 if (ret)
1241                         goto err_device_free;
1242 
1243                 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1244                 if (IS_ERR(xadc->convst_trigger)) {
1245                         ret = PTR_ERR(xadc->convst_trigger);
1246                         goto err_triggered_buffer_cleanup;
1247                 }
1248                 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1249                         "samplerate");
1250                 if (IS_ERR(xadc->samplerate_trigger)) {
1251                         ret = PTR_ERR(xadc->samplerate_trigger);
1252                         goto err_free_convst_trigger;
1253                 }
1254         }
1255 
1256         xadc->clk = devm_clk_get(&pdev->dev, NULL);
1257         if (IS_ERR(xadc->clk)) {
1258                 ret = PTR_ERR(xadc->clk);
1259                 goto err_free_samplerate_trigger;
1260         }
1261 
1262         ret = clk_prepare_enable(xadc->clk);
1263         if (ret)
1264                 goto err_free_samplerate_trigger;
1265 
1266         /*
1267          * Make sure not to exceed the maximum samplerate since otherwise the
1268          * resulting interrupt storm will soft-lock the system.
1269          */
1270         if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1271                 ret = xadc_read_samplerate(xadc);
1272                 if (ret < 0)
1273                         goto err_free_samplerate_trigger;
1274                 if (ret > XADC_MAX_SAMPLERATE) {
1275                         ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1276                         if (ret < 0)
1277                                 goto err_free_samplerate_trigger;
1278                 }
1279         }
1280 
1281         ret = request_irq(xadc->irq, xadc->ops->interrupt_handler, 0,
1282                         dev_name(&pdev->dev), indio_dev);
1283         if (ret)
1284                 goto err_clk_disable_unprepare;
1285 
1286         ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);
1287         if (ret)
1288                 goto err_free_irq;
1289 
1290         for (i = 0; i < 16; i++)
1291                 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1292                         &xadc->threshold[i]);
1293 
1294         ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1295         if (ret)
1296                 goto err_free_irq;
1297 
1298         bipolar_mask = 0;
1299         for (i = 0; i < indio_dev->num_channels; i++) {
1300                 if (indio_dev->channels[i].scan_type.sign == 's')
1301                         bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1302         }
1303 
1304         ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1305         if (ret)
1306                 goto err_free_irq;
1307         ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1308                 bipolar_mask >> 16);
1309         if (ret)
1310                 goto err_free_irq;
1311 
1312         /* Disable all alarms */
1313         ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
1314                                   XADC_CONF1_ALARM_MASK);
1315         if (ret)
1316                 goto err_free_irq;
1317 
1318         /* Set thresholds to min/max */
1319         for (i = 0; i < 16; i++) {
1320                 /*
1321                  * Set max voltage threshold and both temperature thresholds to
1322                  * 0xffff, min voltage threshold to 0.
1323                  */
1324                 if (i % 8 < 4 || i == 7)
1325                         xadc->threshold[i] = 0xffff;
1326                 else
1327                         xadc->threshold[i] = 0;
1328                 ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1329                         xadc->threshold[i]);
1330                 if (ret)
1331                         goto err_free_irq;
1332         }
1333 
1334         /* Go to non-buffered mode */
1335         xadc_postdisable(indio_dev);
1336 
1337         ret = iio_device_register(indio_dev);
1338         if (ret)
1339                 goto err_free_irq;
1340 
1341         platform_set_drvdata(pdev, indio_dev);
1342 
1343         return 0;
1344 
1345 err_free_irq:
1346         free_irq(xadc->irq, indio_dev);
1347         cancel_delayed_work_sync(&xadc->zynq_unmask_work);
1348 err_clk_disable_unprepare:
1349         clk_disable_unprepare(xadc->clk);
1350 err_free_samplerate_trigger:
1351         if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
1352                 iio_trigger_free(xadc->samplerate_trigger);
1353 err_free_convst_trigger:
1354         if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
1355                 iio_trigger_free(xadc->convst_trigger);
1356 err_triggered_buffer_cleanup:
1357         if (xadc->ops->flags & XADC_FLAGS_BUFFERED)
1358                 iio_triggered_buffer_cleanup(indio_dev);
1359 err_device_free:
1360         kfree(indio_dev->channels);
1361 
1362         return ret;
1363 }
1364 
1365 static int xadc_remove(struct platform_device *pdev)
1366 {
1367         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1368         struct xadc *xadc = iio_priv(indio_dev);
1369 
1370         iio_device_unregister(indio_dev);
1371         if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1372                 iio_trigger_free(xadc->samplerate_trigger);
1373                 iio_trigger_free(xadc->convst_trigger);
1374                 iio_triggered_buffer_cleanup(indio_dev);
1375         }
1376         free_irq(xadc->irq, indio_dev);
1377         cancel_delayed_work_sync(&xadc->zynq_unmask_work);
1378         clk_disable_unprepare(xadc->clk);
1379         kfree(xadc->data);
1380         kfree(indio_dev->channels);
1381 
1382         return 0;
1383 }
1384 
1385 static struct platform_driver xadc_driver = {
1386         .probe = xadc_probe,
1387         .remove = xadc_remove,
1388         .driver = {
1389                 .name = "xadc",
1390                 .of_match_table = xadc_of_match_table,
1391         },
1392 };
1393 module_platform_driver(xadc_driver);
1394 
1395 MODULE_LICENSE("GPL v2");
1396 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1397 MODULE_DESCRIPTION("Xilinx XADC IIO driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/iio/adc/xilinx-xadc-core.c

DEFINITIONS
