This source file includes following definitions.
- max1027_read_single_value
- max1027_read_raw
- max1027_debugfs_reg_access
- max1027_validate_trigger
- max1027_set_trigger_state
- max1027_trigger_handler
- max1027_probe
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15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spi/spi.h>
18 #include <linux/delay.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/buffer.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
25
26 #define MAX1027_CONV_REG BIT(7)
27 #define MAX1027_SETUP_REG BIT(6)
28 #define MAX1027_AVG_REG BIT(5)
29 #define MAX1027_RST_REG BIT(4)
30
31
32 #define MAX1027_TEMP BIT(0)
33 #define MAX1027_SCAN_0_N (0x00 << 1)
34 #define MAX1027_SCAN_N_M (0x01 << 1)
35 #define MAX1027_SCAN_N (0x02 << 1)
36 #define MAX1027_NOSCAN (0x03 << 1)
37 #define MAX1027_CHAN(n) ((n) << 3)
38
39
40 #define MAX1027_UNIPOLAR 0x02
41 #define MAX1027_BIPOLAR 0x03
42 #define MAX1027_REF_MODE0 (0x00 << 2)
43 #define MAX1027_REF_MODE1 (0x01 << 2)
44 #define MAX1027_REF_MODE2 (0x02 << 2)
45 #define MAX1027_REF_MODE3 (0x03 << 2)
46 #define MAX1027_CKS_MODE0 (0x00 << 4)
47 #define MAX1027_CKS_MODE1 (0x01 << 4)
48 #define MAX1027_CKS_MODE2 (0x02 << 4)
49 #define MAX1027_CKS_MODE3 (0x03 << 4)
50
51
52 #define MAX1027_NSCAN_4 0x00
53 #define MAX1027_NSCAN_8 0x01
54 #define MAX1027_NSCAN_12 0x02
55 #define MAX1027_NSCAN_16 0x03
56 #define MAX1027_NAVG_4 (0x00 << 2)
57 #define MAX1027_NAVG_8 (0x01 << 2)
58 #define MAX1027_NAVG_16 (0x02 << 2)
59 #define MAX1027_NAVG_32 (0x03 << 2)
60 #define MAX1027_AVG_EN BIT(4)
61
62 enum max1027_id {
63 max1027,
64 max1029,
65 max1031,
66 };
67
68 static const struct spi_device_id max1027_id[] = {
69 {"max1027", max1027},
70 {"max1029", max1029},
71 {"max1031", max1031},
72 {}
73 };
74 MODULE_DEVICE_TABLE(spi, max1027_id);
75
76 #ifdef CONFIG_OF
77 static const struct of_device_id max1027_adc_dt_ids[] = {
78 { .compatible = "maxim,max1027" },
79 { .compatible = "maxim,max1029" },
80 { .compatible = "maxim,max1031" },
81 {},
82 };
83 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
84 #endif
85
86 #define MAX1027_V_CHAN(index) \
87 { \
88 .type = IIO_VOLTAGE, \
89 .indexed = 1, \
90 .channel = index, \
91 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
92 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
93 .scan_index = index + 1, \
94 .scan_type = { \
95 .sign = 'u', \
96 .realbits = 10, \
97 .storagebits = 16, \
98 .shift = 2, \
99 .endianness = IIO_BE, \
100 }, \
101 }
102
103 #define MAX1027_T_CHAN \
104 { \
105 .type = IIO_TEMP, \
106 .channel = 0, \
107 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
108 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
109 .scan_index = 0, \
110 .scan_type = { \
111 .sign = 'u', \
112 .realbits = 12, \
113 .storagebits = 16, \
114 .endianness = IIO_BE, \
115 }, \
116 }
117
118 static const struct iio_chan_spec max1027_channels[] = {
119 MAX1027_T_CHAN,
120 MAX1027_V_CHAN(0),
121 MAX1027_V_CHAN(1),
122 MAX1027_V_CHAN(2),
123 MAX1027_V_CHAN(3),
124 MAX1027_V_CHAN(4),
125 MAX1027_V_CHAN(5),
126 MAX1027_V_CHAN(6),
127 MAX1027_V_CHAN(7)
128 };
129
130 static const struct iio_chan_spec max1029_channels[] = {
131 MAX1027_T_CHAN,
132 MAX1027_V_CHAN(0),
133 MAX1027_V_CHAN(1),
134 MAX1027_V_CHAN(2),
135 MAX1027_V_CHAN(3),
136 MAX1027_V_CHAN(4),
137 MAX1027_V_CHAN(5),
138 MAX1027_V_CHAN(6),
139 MAX1027_V_CHAN(7),
140 MAX1027_V_CHAN(8),
141 MAX1027_V_CHAN(9),
142 MAX1027_V_CHAN(10),
143 MAX1027_V_CHAN(11)
144 };
145
146 static const struct iio_chan_spec max1031_channels[] = {
147 MAX1027_T_CHAN,
148 MAX1027_V_CHAN(0),
149 MAX1027_V_CHAN(1),
150 MAX1027_V_CHAN(2),
151 MAX1027_V_CHAN(3),
152 MAX1027_V_CHAN(4),
153 MAX1027_V_CHAN(5),
154 MAX1027_V_CHAN(6),
155 MAX1027_V_CHAN(7),
156 MAX1027_V_CHAN(8),
157 MAX1027_V_CHAN(9),
158 MAX1027_V_CHAN(10),
159 MAX1027_V_CHAN(11),
160 MAX1027_V_CHAN(12),
161 MAX1027_V_CHAN(13),
162 MAX1027_V_CHAN(14),
163 MAX1027_V_CHAN(15)
164 };
165
166 static const unsigned long max1027_available_scan_masks[] = {
167 0x000001ff,
168 0x00000000,
169 };
170
171 static const unsigned long max1029_available_scan_masks[] = {
172 0x00001fff,
173 0x00000000,
174 };
175
176 static const unsigned long max1031_available_scan_masks[] = {
177 0x0001ffff,
178 0x00000000,
179 };
180
181 struct max1027_chip_info {
182 const struct iio_chan_spec *channels;
183 unsigned int num_channels;
184 const unsigned long *available_scan_masks;
185 };
186
187 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
188 [max1027] = {
189 .channels = max1027_channels,
190 .num_channels = ARRAY_SIZE(max1027_channels),
191 .available_scan_masks = max1027_available_scan_masks,
192 },
193 [max1029] = {
194 .channels = max1029_channels,
195 .num_channels = ARRAY_SIZE(max1029_channels),
196 .available_scan_masks = max1029_available_scan_masks,
197 },
198 [max1031] = {
199 .channels = max1031_channels,
200 .num_channels = ARRAY_SIZE(max1031_channels),
201 .available_scan_masks = max1031_available_scan_masks,
202 },
203 };
204
205 struct max1027_state {
206 const struct max1027_chip_info *info;
207 struct spi_device *spi;
208 struct iio_trigger *trig;
209 __be16 *buffer;
210 struct mutex lock;
211
212 u8 reg ____cacheline_aligned;
213 };
214
215 static int max1027_read_single_value(struct iio_dev *indio_dev,
216 struct iio_chan_spec const *chan,
217 int *val)
218 {
219 int ret;
220 struct max1027_state *st = iio_priv(indio_dev);
221
222 if (iio_buffer_enabled(indio_dev)) {
223 dev_warn(&indio_dev->dev, "trigger mode already enabled");
224 return -EBUSY;
225 }
226
227
228 st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
229 ret = spi_write(st->spi, &st->reg, 1);
230 if (ret < 0) {
231 dev_err(&indio_dev->dev,
232 "Failed to configure setup register\n");
233 return ret;
234 }
235
236
237 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
238 MAX1027_NOSCAN;
239 if (chan->type == IIO_TEMP)
240 st->reg |= MAX1027_TEMP;
241 ret = spi_write(st->spi, &st->reg, 1);
242 if (ret < 0) {
243 dev_err(&indio_dev->dev,
244 "Failed to configure conversion register\n");
245 return ret;
246 }
247
248
249
250
251
252
253 mdelay(1);
254
255
256 ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
257 if (ret < 0)
258 return ret;
259
260 *val = be16_to_cpu(st->buffer[0]);
261
262 return IIO_VAL_INT;
263 }
264
265 static int max1027_read_raw(struct iio_dev *indio_dev,
266 struct iio_chan_spec const *chan,
267 int *val, int *val2, long mask)
268 {
269 int ret = 0;
270 struct max1027_state *st = iio_priv(indio_dev);
271
272 mutex_lock(&st->lock);
273
274 switch (mask) {
275 case IIO_CHAN_INFO_RAW:
276 ret = max1027_read_single_value(indio_dev, chan, val);
277 break;
278 case IIO_CHAN_INFO_SCALE:
279 switch (chan->type) {
280 case IIO_TEMP:
281 *val = 1;
282 *val2 = 8;
283 ret = IIO_VAL_FRACTIONAL;
284 break;
285 case IIO_VOLTAGE:
286 *val = 2500;
287 *val2 = 10;
288 ret = IIO_VAL_FRACTIONAL_LOG2;
289 break;
290 default:
291 ret = -EINVAL;
292 break;
293 }
294 break;
295 default:
296 ret = -EINVAL;
297 break;
298 }
299
300 mutex_unlock(&st->lock);
301
302 return ret;
303 }
304
305 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
306 unsigned reg, unsigned writeval,
307 unsigned *readval)
308 {
309 struct max1027_state *st = iio_priv(indio_dev);
310 u8 *val = (u8 *)st->buffer;
311
312 if (readval != NULL)
313 return -EINVAL;
314
315 *val = (u8)writeval;
316 return spi_write(st->spi, val, 1);
317 }
318
319 static int max1027_validate_trigger(struct iio_dev *indio_dev,
320 struct iio_trigger *trig)
321 {
322 struct max1027_state *st = iio_priv(indio_dev);
323
324 if (st->trig != trig)
325 return -EINVAL;
326
327 return 0;
328 }
329
330 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
331 {
332 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
333 struct max1027_state *st = iio_priv(indio_dev);
334 int ret;
335
336 if (state) {
337
338 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
339 MAX1027_REF_MODE2;
340 ret = spi_write(st->spi, &st->reg, 1);
341 if (ret < 0)
342 return ret;
343
344
345 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
346 MAX1027_SCAN_N_M | MAX1027_TEMP;
347 ret = spi_write(st->spi, &st->reg, 1);
348 if (ret < 0)
349 return ret;
350 } else {
351
352 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
353 MAX1027_REF_MODE2;
354 ret = spi_write(st->spi, &st->reg, 1);
355 if (ret < 0)
356 return ret;
357 }
358
359 return 0;
360 }
361
362 static irqreturn_t max1027_trigger_handler(int irq, void *private)
363 {
364 struct iio_poll_func *pf = private;
365 struct iio_dev *indio_dev = pf->indio_dev;
366 struct max1027_state *st = iio_priv(indio_dev);
367
368 pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
369
370
371 spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
372
373 iio_push_to_buffers(indio_dev, st->buffer);
374
375 iio_trigger_notify_done(indio_dev->trig);
376
377 return IRQ_HANDLED;
378 }
379
380 static const struct iio_trigger_ops max1027_trigger_ops = {
381 .validate_device = &iio_trigger_validate_own_device,
382 .set_trigger_state = &max1027_set_trigger_state,
383 };
384
385 static const struct iio_info max1027_info = {
386 .read_raw = &max1027_read_raw,
387 .validate_trigger = &max1027_validate_trigger,
388 .debugfs_reg_access = &max1027_debugfs_reg_access,
389 };
390
391 static int max1027_probe(struct spi_device *spi)
392 {
393 int ret;
394 struct iio_dev *indio_dev;
395 struct max1027_state *st;
396
397 pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
398
399 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
400 if (indio_dev == NULL) {
401 pr_err("Can't allocate iio device\n");
402 return -ENOMEM;
403 }
404
405 spi_set_drvdata(spi, indio_dev);
406
407 st = iio_priv(indio_dev);
408 st->spi = spi;
409 st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
410
411 mutex_init(&st->lock);
412
413 indio_dev->name = spi_get_device_id(spi)->name;
414 indio_dev->dev.parent = &spi->dev;
415 indio_dev->dev.of_node = spi->dev.of_node;
416 indio_dev->info = &max1027_info;
417 indio_dev->modes = INDIO_DIRECT_MODE;
418 indio_dev->channels = st->info->channels;
419 indio_dev->num_channels = st->info->num_channels;
420 indio_dev->available_scan_masks = st->info->available_scan_masks;
421
422 st->buffer = devm_kmalloc_array(&indio_dev->dev,
423 indio_dev->num_channels, 2,
424 GFP_KERNEL);
425 if (st->buffer == NULL) {
426 dev_err(&indio_dev->dev, "Can't allocate buffer\n");
427 return -ENOMEM;
428 }
429
430 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
431 &iio_pollfunc_store_time,
432 &max1027_trigger_handler, NULL);
433 if (ret < 0) {
434 dev_err(&indio_dev->dev, "Failed to setup buffer\n");
435 return ret;
436 }
437
438 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
439 indio_dev->name);
440 if (st->trig == NULL) {
441 ret = -ENOMEM;
442 dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n");
443 return ret;
444 }
445
446 st->trig->ops = &max1027_trigger_ops;
447 st->trig->dev.parent = &spi->dev;
448 iio_trigger_set_drvdata(st->trig, indio_dev);
449 iio_trigger_register(st->trig);
450
451 ret = devm_request_threaded_irq(&spi->dev, spi->irq,
452 iio_trigger_generic_data_rdy_poll,
453 NULL,
454 IRQF_TRIGGER_FALLING,
455 spi->dev.driver->name, st->trig);
456 if (ret < 0) {
457 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
458 return ret;
459 }
460
461
462 st->reg = MAX1027_RST_REG;
463 ret = spi_write(st->spi, &st->reg, 1);
464 if (ret < 0) {
465 dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
466 return ret;
467 }
468
469
470 st->reg = MAX1027_AVG_REG;
471 ret = spi_write(st->spi, &st->reg, 1);
472 if (ret < 0) {
473 dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
474 return ret;
475 }
476
477 return devm_iio_device_register(&spi->dev, indio_dev);
478 }
479
480 static struct spi_driver max1027_driver = {
481 .driver = {
482 .name = "max1027",
483 .of_match_table = of_match_ptr(max1027_adc_dt_ids),
484 },
485 .probe = max1027_probe,
486 .id_table = max1027_id,
487 };
488 module_spi_driver(max1027_driver);
489
490 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
491 MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
492 MODULE_LICENSE("GPL v2");