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7 #ifndef SPI_AD5624R_H_
8 #define SPI_AD5624R_H_
9
10 #define AD5624R_DAC_CHANNELS 4
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12 #define AD5624R_ADDR_DAC0 0x0
13 #define AD5624R_ADDR_DAC1 0x1
14 #define AD5624R_ADDR_DAC2 0x2
15 #define AD5624R_ADDR_DAC3 0x3
16 #define AD5624R_ADDR_ALL_DAC 0x7
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18 #define AD5624R_CMD_WRITE_INPUT_N 0x0
19 #define AD5624R_CMD_UPDATE_DAC_N 0x1
20 #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
21 #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_N 0x3
22 #define AD5624R_CMD_POWERDOWN_DAC 0x4
23 #define AD5624R_CMD_RESET 0x5
24 #define AD5624R_CMD_LDAC_SETUP 0x6
25 #define AD5624R_CMD_INTERNAL_REFER_SETUP 0x7
26
27 #define AD5624R_LDAC_PWRDN_NONE 0x0
28 #define AD5624R_LDAC_PWRDN_1K 0x1
29 #define AD5624R_LDAC_PWRDN_100K 0x2
30 #define AD5624R_LDAC_PWRDN_3STATE 0x3
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38 struct ad5624r_chip_info {
39 const struct iio_chan_spec *channels;
40 u16 int_vref_mv;
41 };
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54 struct ad5624r_state {
55 struct spi_device *us;
56 const struct ad5624r_chip_info *chip_info;
57 struct regulator *reg;
58 unsigned short vref_mv;
59 unsigned pwr_down_mask;
60 unsigned pwr_down_mode;
61 };
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69 enum ad5624r_supported_device_ids {
70 ID_AD5624R3,
71 ID_AD5644R3,
72 ID_AD5664R3,
73 ID_AD5624R5,
74 ID_AD5644R5,
75 ID_AD5664R5,
76 };
77
78 #endif