root/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3 * Copyright (C) 2012 Invensense, Inc.
   4 */
   5 #include <linux/i2c.h>
   6 #include <linux/i2c-mux.h>
   7 #include <linux/mutex.h>
   8 #include <linux/iio/iio.h>
   9 #include <linux/iio/buffer.h>
  10 #include <linux/regmap.h>
  11 #include <linux/iio/sysfs.h>
  12 #include <linux/iio/kfifo_buf.h>
  13 #include <linux/iio/trigger.h>
  14 #include <linux/iio/triggered_buffer.h>
  15 #include <linux/iio/trigger_consumer.h>
  16 #include <linux/platform_data/invensense_mpu6050.h>
  17 
  18 /**
  19  *  struct inv_mpu6050_reg_map - Notable registers.
  20  *  @sample_rate_div:   Divider applied to gyro output rate.
  21  *  @lpf:               Configures internal low pass filter.
  22  *  @accel_lpf:         Configures accelerometer low pass filter.
  23  *  @user_ctrl:         Enables/resets the FIFO.
  24  *  @fifo_en:           Determines which data will appear in FIFO.
  25  *  @gyro_config:       gyro config register.
  26  *  @accl_config:       accel config register
  27  *  @fifo_count_h:      Upper byte of FIFO count.
  28  *  @fifo_r_w:          FIFO register.
  29  *  @raw_gyro:          Address of first gyro register.
  30  *  @raw_accl:          Address of first accel register.
  31  *  @temperature:       temperature register
  32  *  @int_enable:        Interrupt enable register.
  33  *  @int_status:        Interrupt status register.
  34  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  35  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  36  *  @int_pin_cfg;       Controls interrupt pin configuration.
  37  *  @accl_offset:       Controls the accelerometer calibration offset.
  38  *  @gyro_offset:       Controls the gyroscope calibration offset.
  39  *  @i2c_if:            Controls the i2c interface
  40  */
  41 struct inv_mpu6050_reg_map {
  42         u8 sample_rate_div;
  43         u8 lpf;
  44         u8 accel_lpf;
  45         u8 user_ctrl;
  46         u8 fifo_en;
  47         u8 gyro_config;
  48         u8 accl_config;
  49         u8 fifo_count_h;
  50         u8 fifo_r_w;
  51         u8 raw_gyro;
  52         u8 raw_accl;
  53         u8 temperature;
  54         u8 int_enable;
  55         u8 int_status;
  56         u8 pwr_mgmt_1;
  57         u8 pwr_mgmt_2;
  58         u8 int_pin_cfg;
  59         u8 accl_offset;
  60         u8 gyro_offset;
  61         u8 i2c_if;
  62 };
  63 
  64 /*device enum */
  65 enum inv_devices {
  66         INV_MPU6050,
  67         INV_MPU6500,
  68         INV_MPU6515,
  69         INV_MPU6000,
  70         INV_MPU9150,
  71         INV_MPU9250,
  72         INV_MPU9255,
  73         INV_ICM20608,
  74         INV_ICM20602,
  75         INV_NUM_PARTS
  76 };
  77 
  78 /**
  79  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  80  *  @fsr:               Full scale range.
  81  *  @lpf:               Digital low pass filter frequency.
  82  *  @accl_fs:           accel full scale range.
  83  *  @accl_fifo_enable:  enable accel data output
  84  *  @gyro_fifo_enable:  enable gyro data output
  85  *  @divider:           chip sample rate divider (sample rate divider - 1)
  86  */
  87 struct inv_mpu6050_chip_config {
  88         unsigned int fsr:2;
  89         unsigned int lpf:3;
  90         unsigned int accl_fs:2;
  91         unsigned int accl_fifo_enable:1;
  92         unsigned int gyro_fifo_enable:1;
  93         u8 divider;
  94         u8 user_ctrl;
  95 };
  96 
  97 /**
  98  *  struct inv_mpu6050_hw - Other important hardware information.
  99  *  @whoami:    Self identification byte from WHO_AM_I register
 100  *  @name:      name of the chip.
 101  *  @reg:   register map of the chip.
 102  *  @config:    configuration of the chip.
 103  *  @fifo_size: size of the FIFO in bytes.
 104  *  @temp:      offset and scale to apply to raw temperature.
 105  */
 106 struct inv_mpu6050_hw {
 107         u8 whoami;
 108         u8 *name;
 109         const struct inv_mpu6050_reg_map *reg;
 110         const struct inv_mpu6050_chip_config *config;
 111         size_t fifo_size;
 112         struct {
 113                 int offset;
 114                 int scale;
 115         } temp;
 116 };
 117 
 118 /*
 119  *  struct inv_mpu6050_state - Driver state variables.
 120  *  @lock:              Chip access lock.
 121  *  @trig:              IIO trigger.
 122  *  @chip_config:       Cached attribute information.
 123  *  @reg:               Map of important registers.
 124  *  @hw:                Other hardware-specific information.
 125  *  @chip_type:         chip type.
 126  *  @plat_data:         platform data (deprecated in favor of @orientation).
 127  *  @orientation:       sensor chip orientation relative to main hardware.
 128  *  @map                regmap pointer.
 129  *  @irq                interrupt number.
 130  *  @irq_mask           the int_pin_cfg mask to configure interrupt type.
 131  *  @chip_period:       chip internal period estimation (~1kHz).
 132  *  @it_timestamp:      timestamp from previous interrupt.
 133  *  @data_timestamp:    timestamp for next data sample.
 134  *  @vddio_supply       voltage regulator for the chip.
 135  */
 136 struct inv_mpu6050_state {
 137         struct mutex lock;
 138         struct iio_trigger  *trig;
 139         struct inv_mpu6050_chip_config chip_config;
 140         const struct inv_mpu6050_reg_map *reg;
 141         const struct inv_mpu6050_hw *hw;
 142         enum   inv_devices chip_type;
 143         struct i2c_mux_core *muxc;
 144         struct i2c_client *mux_client;
 145         unsigned int powerup_count;
 146         struct inv_mpu6050_platform_data plat_data;
 147         struct iio_mount_matrix orientation;
 148         struct regmap *map;
 149         int irq;
 150         u8 irq_mask;
 151         unsigned skip_samples;
 152         s64 chip_period;
 153         s64 it_timestamp;
 154         s64 data_timestamp;
 155         struct regulator *vddio_supply;
 156 };
 157 
 158 /*register and associated bit definition*/
 159 #define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 160 #define INV_MPU6050_REG_GYRO_OFFSET         0x13
 161 
 162 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 163 #define INV_MPU6050_REG_CONFIG              0x1A
 164 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 165 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 166 
 167 #define INV_MPU6050_REG_FIFO_EN             0x23
 168 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 169 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 170 
 171 #define INV_MPU6050_REG_INT_ENABLE          0x38
 172 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 173 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 174 
 175 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 176 #define INV_MPU6050_REG_TEMPERATURE         0x41
 177 #define INV_MPU6050_REG_RAW_GYRO            0x43
 178 
 179 #define INV_MPU6050_REG_INT_STATUS          0x3A
 180 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
 181 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
 182 
 183 #define INV_MPU6050_REG_USER_CTRL           0x6A
 184 #define INV_MPU6050_BIT_FIFO_RST            0x04
 185 #define INV_MPU6050_BIT_DMP_RST             0x08
 186 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 187 #define INV_MPU6050_BIT_FIFO_EN             0x40
 188 #define INV_MPU6050_BIT_DMP_EN              0x80
 189 #define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 190 
 191 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 192 #define INV_MPU6050_BIT_H_RESET             0x80
 193 #define INV_MPU6050_BIT_SLEEP               0x40
 194 #define INV_MPU6050_BIT_CLK_MASK            0x7
 195 
 196 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 197 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 198 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 199 
 200 /* ICM20602 register */
 201 #define INV_ICM20602_REG_I2C_IF             0x70
 202 #define INV_ICM20602_BIT_I2C_IF_DIS         0x40
 203 
 204 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 205 #define INV_MPU6050_REG_FIFO_R_W            0x74
 206 
 207 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 208 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 209 
 210 /* ICM20602 FIFO samples include temperature readings */
 211 #define INV_ICM20602_BYTES_PER_TEMP_SENSOR   2
 212 
 213 /* mpu6500 registers */
 214 #define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 215 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 216 
 217 /* delay time in milliseconds */
 218 #define INV_MPU6050_POWER_UP_TIME            100
 219 #define INV_MPU6050_TEMP_UP_TIME             100
 220 #define INV_MPU6050_SENSOR_UP_TIME           30
 221 
 222 /* delay time in microseconds */
 223 #define INV_MPU6050_REG_UP_TIME_MIN          5000
 224 #define INV_MPU6050_REG_UP_TIME_MAX          10000
 225 
 226 #define INV_MPU6050_TEMP_OFFSET              12420
 227 #define INV_MPU6050_TEMP_SCALE               2941176
 228 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 229 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 230 #define INV_MPU6050_THREE_AXIS               3
 231 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 232 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 233 
 234 #define INV_MPU6500_TEMP_OFFSET              7011
 235 #define INV_MPU6500_TEMP_SCALE               2995178
 236 
 237 #define INV_ICM20608_TEMP_OFFSET             8170
 238 #define INV_ICM20608_TEMP_SCALE              3059976
 239 
 240 /* 6 + 6 round up and plus 8 */
 241 #define INV_MPU6050_OUTPUT_DATA_SIZE         24
 242 
 243 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 244 #define INV_MPU6050_ACTIVE_HIGH         0x00
 245 #define INV_MPU6050_ACTIVE_LOW          0x80
 246 /* enable level triggering */
 247 #define INV_MPU6050_LATCH_INT_EN        0x20
 248 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 249 
 250 /* Allowed timestamp period jitter in percent */
 251 #define INV_MPU6050_TS_PERIOD_JITTER    4
 252 
 253 /* init parameters */
 254 #define INV_MPU6050_INIT_FIFO_RATE           50
 255 #define INV_MPU6050_MAX_FIFO_RATE            1000
 256 #define INV_MPU6050_MIN_FIFO_RATE            4
 257 
 258 /* chip internal frequency: 1KHz */
 259 #define INV_MPU6050_INTERNAL_FREQ_HZ            1000
 260 /* return the frequency divider (chip sample rate divider + 1) */
 261 #define INV_MPU6050_FREQ_DIVIDER(st)                                    \
 262         ((st)->chip_config.divider + 1)
 263 /* chip sample rate divider to fifo rate */
 264 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)                     \
 265         ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
 266 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)                       \
 267         (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
 268 
 269 #define INV_MPU6050_REG_WHOAMI                  117
 270 
 271 #define INV_MPU6000_WHOAMI_VALUE                0x68
 272 #define INV_MPU6050_WHOAMI_VALUE                0x68
 273 #define INV_MPU6500_WHOAMI_VALUE                0x70
 274 #define INV_MPU9150_WHOAMI_VALUE                0x68
 275 #define INV_MPU9250_WHOAMI_VALUE                0x71
 276 #define INV_MPU9255_WHOAMI_VALUE                0x73
 277 #define INV_MPU6515_WHOAMI_VALUE                0x74
 278 #define INV_ICM20608_WHOAMI_VALUE               0xAF
 279 #define INV_ICM20602_WHOAMI_VALUE               0x12
 280 
 281 /* scan element definition for generic MPU6xxx devices */
 282 enum inv_mpu6050_scan {
 283         INV_MPU6050_SCAN_ACCL_X,
 284         INV_MPU6050_SCAN_ACCL_Y,
 285         INV_MPU6050_SCAN_ACCL_Z,
 286         INV_MPU6050_SCAN_GYRO_X,
 287         INV_MPU6050_SCAN_GYRO_Y,
 288         INV_MPU6050_SCAN_GYRO_Z,
 289         INV_MPU6050_SCAN_TIMESTAMP,
 290 };
 291 
 292 /* scan element definition for ICM20602, which includes temperature */
 293 enum inv_icm20602_scan {
 294         INV_ICM20602_SCAN_ACCL_X,
 295         INV_ICM20602_SCAN_ACCL_Y,
 296         INV_ICM20602_SCAN_ACCL_Z,
 297         INV_ICM20602_SCAN_TEMP,
 298         INV_ICM20602_SCAN_GYRO_X,
 299         INV_ICM20602_SCAN_GYRO_Y,
 300         INV_ICM20602_SCAN_GYRO_Z,
 301         INV_ICM20602_SCAN_TIMESTAMP,
 302 };
 303 
 304 enum inv_mpu6050_filter_e {
 305         INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 306         INV_MPU6050_FILTER_188HZ,
 307         INV_MPU6050_FILTER_98HZ,
 308         INV_MPU6050_FILTER_42HZ,
 309         INV_MPU6050_FILTER_20HZ,
 310         INV_MPU6050_FILTER_10HZ,
 311         INV_MPU6050_FILTER_5HZ,
 312         INV_MPU6050_FILTER_2100HZ_NOLPF,
 313         NUM_MPU6050_FILTER
 314 };
 315 
 316 /* IIO attribute address */
 317 enum INV_MPU6050_IIO_ATTR_ADDR {
 318         ATTR_GYRO_MATRIX,
 319         ATTR_ACCL_MATRIX,
 320 };
 321 
 322 enum inv_mpu6050_accl_fs_e {
 323         INV_MPU6050_FS_02G = 0,
 324         INV_MPU6050_FS_04G,
 325         INV_MPU6050_FS_08G,
 326         INV_MPU6050_FS_16G,
 327         NUM_ACCL_FSR
 328 };
 329 
 330 enum inv_mpu6050_fsr_e {
 331         INV_MPU6050_FSR_250DPS = 0,
 332         INV_MPU6050_FSR_500DPS,
 333         INV_MPU6050_FSR_1000DPS,
 334         INV_MPU6050_FSR_2000DPS,
 335         NUM_MPU6050_FSR
 336 };
 337 
 338 enum inv_mpu6050_clock_sel_e {
 339         INV_CLK_INTERNAL = 0,
 340         INV_CLK_PLL,
 341         NUM_CLK
 342 };
 343 
 344 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 345 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
 346 int inv_reset_fifo(struct iio_dev *indio_dev);
 347 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 348 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 349 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 350 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 351 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 352 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 353                 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 354 extern const struct dev_pm_ops inv_mpu_pmops;