This source file includes following definitions.
- kxsd9_write_scale
- kxsd9_write_raw
- kxsd9_read_raw
- kxsd9_trigger_handler
- kxsd9_buffer_preenable
- kxsd9_buffer_postdisable
- kxsd9_get_mount_matrix
- kxsd9_power_up
- kxsd9_power_down
- kxsd9_common_probe
- kxsd9_common_remove
- kxsd9_runtime_suspend
- kxsd9_runtime_resume
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14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/sysfs.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/regmap.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/iio/iio.h>
25 #include <linux/iio/sysfs.h>
26 #include <linux/iio/buffer.h>
27 #include <linux/iio/triggered_buffer.h>
28 #include <linux/iio/trigger_consumer.h>
29
30 #include "kxsd9.h"
31
32 #define KXSD9_REG_X 0x00
33 #define KXSD9_REG_Y 0x02
34 #define KXSD9_REG_Z 0x04
35 #define KXSD9_REG_AUX 0x06
36 #define KXSD9_REG_RESET 0x0a
37 #define KXSD9_REG_CTRL_C 0x0c
38
39 #define KXSD9_CTRL_C_FS_MASK 0x03
40 #define KXSD9_CTRL_C_FS_8G 0x00
41 #define KXSD9_CTRL_C_FS_6G 0x01
42 #define KXSD9_CTRL_C_FS_4G 0x02
43 #define KXSD9_CTRL_C_FS_2G 0x03
44 #define KXSD9_CTRL_C_MOT_LAT BIT(3)
45 #define KXSD9_CTRL_C_MOT_LEV BIT(4)
46 #define KXSD9_CTRL_C_LP_MASK 0xe0
47 #define KXSD9_CTRL_C_LP_NONE 0x00
48 #define KXSD9_CTRL_C_LP_2000HZC BIT(5)
49 #define KXSD9_CTRL_C_LP_2000HZB BIT(6)
50 #define KXSD9_CTRL_C_LP_2000HZA (BIT(5)|BIT(6))
51 #define KXSD9_CTRL_C_LP_1000HZ BIT(7)
52 #define KXSD9_CTRL_C_LP_500HZ (BIT(7)|BIT(5))
53 #define KXSD9_CTRL_C_LP_100HZ (BIT(7)|BIT(6))
54 #define KXSD9_CTRL_C_LP_50HZ (BIT(7)|BIT(6)|BIT(5))
55
56 #define KXSD9_REG_CTRL_B 0x0d
57
58 #define KXSD9_CTRL_B_CLK_HLD BIT(7)
59 #define KXSD9_CTRL_B_ENABLE BIT(6)
60 #define KXSD9_CTRL_B_ST BIT(5)
61
62 #define KXSD9_REG_CTRL_A 0x0e
63
64
65
66
67
68
69
70
71
72 struct kxsd9_state {
73 struct device *dev;
74 struct regmap *map;
75 struct iio_mount_matrix orientation;
76 struct regulator_bulk_data regs[2];
77 u8 scale;
78 };
79
80 #define KXSD9_SCALE_2G "0.011978"
81 #define KXSD9_SCALE_4G "0.023927"
82 #define KXSD9_SCALE_6G "0.035934"
83 #define KXSD9_SCALE_8G "0.047853"
84
85
86 static const int kxsd9_micro_scales[4] = { 47853, 35934, 23927, 11978 };
87
88 #define KXSD9_ZERO_G_OFFSET -2048
89
90
91
92
93 static const char kxsd9_reg_vdd[] = "vdd";
94 static const char kxsd9_reg_iovdd[] = "iovdd";
95
96 static int kxsd9_write_scale(struct iio_dev *indio_dev, int micro)
97 {
98 int ret, i;
99 struct kxsd9_state *st = iio_priv(indio_dev);
100 bool foundit = false;
101
102 for (i = 0; i < 4; i++)
103 if (micro == kxsd9_micro_scales[i]) {
104 foundit = true;
105 break;
106 }
107 if (!foundit)
108 return -EINVAL;
109
110 ret = regmap_update_bits(st->map,
111 KXSD9_REG_CTRL_C,
112 KXSD9_CTRL_C_FS_MASK,
113 i);
114 if (ret < 0)
115 goto error_ret;
116
117
118 st->scale = i;
119
120 error_ret:
121 return ret;
122 }
123
124 static IIO_CONST_ATTR(accel_scale_available,
125 KXSD9_SCALE_2G " "
126 KXSD9_SCALE_4G " "
127 KXSD9_SCALE_6G " "
128 KXSD9_SCALE_8G);
129
130 static struct attribute *kxsd9_attributes[] = {
131 &iio_const_attr_accel_scale_available.dev_attr.attr,
132 NULL,
133 };
134
135 static int kxsd9_write_raw(struct iio_dev *indio_dev,
136 struct iio_chan_spec const *chan,
137 int val,
138 int val2,
139 long mask)
140 {
141 int ret = -EINVAL;
142 struct kxsd9_state *st = iio_priv(indio_dev);
143
144 pm_runtime_get_sync(st->dev);
145
146 if (mask == IIO_CHAN_INFO_SCALE) {
147
148 if (val)
149 return -EINVAL;
150 ret = kxsd9_write_scale(indio_dev, val2);
151 }
152
153 pm_runtime_mark_last_busy(st->dev);
154 pm_runtime_put_autosuspend(st->dev);
155
156 return ret;
157 }
158
159 static int kxsd9_read_raw(struct iio_dev *indio_dev,
160 struct iio_chan_spec const *chan,
161 int *val, int *val2, long mask)
162 {
163 int ret = -EINVAL;
164 struct kxsd9_state *st = iio_priv(indio_dev);
165 unsigned int regval;
166 __be16 raw_val;
167 u16 nval;
168
169 pm_runtime_get_sync(st->dev);
170
171 switch (mask) {
172 case IIO_CHAN_INFO_RAW:
173 ret = regmap_bulk_read(st->map, chan->address, &raw_val,
174 sizeof(raw_val));
175 if (ret)
176 goto error_ret;
177 nval = be16_to_cpu(raw_val);
178
179 nval >>= 4;
180 *val = nval;
181 ret = IIO_VAL_INT;
182 break;
183 case IIO_CHAN_INFO_OFFSET:
184
185 *val = KXSD9_ZERO_G_OFFSET;
186 ret = IIO_VAL_INT;
187 break;
188 case IIO_CHAN_INFO_SCALE:
189 ret = regmap_read(st->map,
190 KXSD9_REG_CTRL_C,
191 ®val);
192 if (ret < 0)
193 goto error_ret;
194 *val = 0;
195 *val2 = kxsd9_micro_scales[regval & KXSD9_CTRL_C_FS_MASK];
196 ret = IIO_VAL_INT_PLUS_MICRO;
197 break;
198 }
199
200 error_ret:
201 pm_runtime_mark_last_busy(st->dev);
202 pm_runtime_put_autosuspend(st->dev);
203
204 return ret;
205 };
206
207 static irqreturn_t kxsd9_trigger_handler(int irq, void *p)
208 {
209 const struct iio_poll_func *pf = p;
210 struct iio_dev *indio_dev = pf->indio_dev;
211 struct kxsd9_state *st = iio_priv(indio_dev);
212 int ret;
213
214 __be16 hw_values[8];
215
216 ret = regmap_bulk_read(st->map,
217 KXSD9_REG_X,
218 &hw_values,
219 8);
220 if (ret) {
221 dev_err(st->dev,
222 "error reading data\n");
223 return ret;
224 }
225
226 iio_push_to_buffers_with_timestamp(indio_dev,
227 hw_values,
228 iio_get_time_ns(indio_dev));
229 iio_trigger_notify_done(indio_dev->trig);
230
231 return IRQ_HANDLED;
232 }
233
234 static int kxsd9_buffer_preenable(struct iio_dev *indio_dev)
235 {
236 struct kxsd9_state *st = iio_priv(indio_dev);
237
238 pm_runtime_get_sync(st->dev);
239
240 return 0;
241 }
242
243 static int kxsd9_buffer_postdisable(struct iio_dev *indio_dev)
244 {
245 struct kxsd9_state *st = iio_priv(indio_dev);
246
247 pm_runtime_mark_last_busy(st->dev);
248 pm_runtime_put_autosuspend(st->dev);
249
250 return 0;
251 }
252
253 static const struct iio_buffer_setup_ops kxsd9_buffer_setup_ops = {
254 .preenable = kxsd9_buffer_preenable,
255 .postenable = iio_triggered_buffer_postenable,
256 .predisable = iio_triggered_buffer_predisable,
257 .postdisable = kxsd9_buffer_postdisable,
258 };
259
260 static const struct iio_mount_matrix *
261 kxsd9_get_mount_matrix(const struct iio_dev *indio_dev,
262 const struct iio_chan_spec *chan)
263 {
264 struct kxsd9_state *st = iio_priv(indio_dev);
265
266 return &st->orientation;
267 }
268
269 static const struct iio_chan_spec_ext_info kxsd9_ext_info[] = {
270 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kxsd9_get_mount_matrix),
271 { },
272 };
273
274 #define KXSD9_ACCEL_CHAN(axis, index) \
275 { \
276 .type = IIO_ACCEL, \
277 .modified = 1, \
278 .channel2 = IIO_MOD_##axis, \
279 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
280 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
281 BIT(IIO_CHAN_INFO_OFFSET), \
282 .ext_info = kxsd9_ext_info, \
283 .address = KXSD9_REG_##axis, \
284 .scan_index = index, \
285 .scan_type = { \
286 .sign = 'u', \
287 .realbits = 12, \
288 .storagebits = 16, \
289 .shift = 4, \
290 .endianness = IIO_BE, \
291 }, \
292 }
293
294 static const struct iio_chan_spec kxsd9_channels[] = {
295 KXSD9_ACCEL_CHAN(X, 0),
296 KXSD9_ACCEL_CHAN(Y, 1),
297 KXSD9_ACCEL_CHAN(Z, 2),
298 {
299 .type = IIO_VOLTAGE,
300 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
301 .indexed = 1,
302 .address = KXSD9_REG_AUX,
303 .scan_index = 3,
304 .scan_type = {
305 .sign = 'u',
306 .realbits = 12,
307 .storagebits = 16,
308 .shift = 4,
309 .endianness = IIO_BE,
310 },
311 },
312 IIO_CHAN_SOFT_TIMESTAMP(4),
313 };
314
315 static const struct attribute_group kxsd9_attribute_group = {
316 .attrs = kxsd9_attributes,
317 };
318
319 static int kxsd9_power_up(struct kxsd9_state *st)
320 {
321 int ret;
322
323
324 ret = regulator_bulk_enable(ARRAY_SIZE(st->regs), st->regs);
325 if (ret) {
326 dev_err(st->dev, "Cannot enable regulators\n");
327 return ret;
328 }
329
330
331 ret = regmap_write(st->map,
332 KXSD9_REG_CTRL_B,
333 KXSD9_CTRL_B_ENABLE);
334 if (ret)
335 return ret;
336
337
338
339
340
341 ret = regmap_write(st->map,
342 KXSD9_REG_CTRL_C,
343 KXSD9_CTRL_C_LP_1000HZ |
344 KXSD9_CTRL_C_MOT_LEV |
345 KXSD9_CTRL_C_MOT_LAT |
346 st->scale);
347 if (ret)
348 return ret;
349
350
351
352
353
354 msleep(20);
355
356 return 0;
357 };
358
359 static int kxsd9_power_down(struct kxsd9_state *st)
360 {
361 int ret;
362
363
364
365
366
367
368
369 ret = regmap_update_bits(st->map,
370 KXSD9_REG_CTRL_B,
371 KXSD9_CTRL_B_ENABLE,
372 0);
373 if (ret)
374 return ret;
375
376
377 ret = regulator_bulk_disable(ARRAY_SIZE(st->regs), st->regs);
378 if (ret) {
379 dev_err(st->dev, "Cannot disable regulators\n");
380 return ret;
381 }
382
383 return 0;
384 }
385
386 static const struct iio_info kxsd9_info = {
387 .read_raw = &kxsd9_read_raw,
388 .write_raw = &kxsd9_write_raw,
389 .attrs = &kxsd9_attribute_group,
390 };
391
392
393 static const unsigned long kxsd9_scan_masks[] = { 0xf, 0 };
394
395 int kxsd9_common_probe(struct device *dev,
396 struct regmap *map,
397 const char *name)
398 {
399 struct iio_dev *indio_dev;
400 struct kxsd9_state *st;
401 int ret;
402
403 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
404 if (!indio_dev)
405 return -ENOMEM;
406
407 st = iio_priv(indio_dev);
408 st->dev = dev;
409 st->map = map;
410
411 indio_dev->channels = kxsd9_channels;
412 indio_dev->num_channels = ARRAY_SIZE(kxsd9_channels);
413 indio_dev->name = name;
414 indio_dev->dev.parent = dev;
415 indio_dev->info = &kxsd9_info;
416 indio_dev->modes = INDIO_DIRECT_MODE;
417 indio_dev->available_scan_masks = kxsd9_scan_masks;
418
419
420 ret = iio_read_mount_matrix(dev, "mount-matrix", &st->orientation);
421 if (ret)
422 return ret;
423
424
425 st->regs[0].supply = kxsd9_reg_vdd;
426 st->regs[1].supply = kxsd9_reg_iovdd;
427 ret = devm_regulator_bulk_get(dev,
428 ARRAY_SIZE(st->regs),
429 st->regs);
430 if (ret) {
431 dev_err(dev, "Cannot get regulators\n");
432 return ret;
433 }
434
435 st->scale = KXSD9_CTRL_C_FS_2G;
436
437 kxsd9_power_up(st);
438
439 ret = iio_triggered_buffer_setup(indio_dev,
440 iio_pollfunc_store_time,
441 kxsd9_trigger_handler,
442 &kxsd9_buffer_setup_ops);
443 if (ret) {
444 dev_err(dev, "triggered buffer setup failed\n");
445 goto err_power_down;
446 }
447
448 ret = iio_device_register(indio_dev);
449 if (ret)
450 goto err_cleanup_buffer;
451
452 dev_set_drvdata(dev, indio_dev);
453
454
455 pm_runtime_get_noresume(dev);
456 pm_runtime_set_active(dev);
457 pm_runtime_enable(dev);
458
459
460
461
462
463 pm_runtime_set_autosuspend_delay(dev, 2000);
464 pm_runtime_use_autosuspend(dev);
465 pm_runtime_put(dev);
466
467 return 0;
468
469 err_cleanup_buffer:
470 iio_triggered_buffer_cleanup(indio_dev);
471 err_power_down:
472 kxsd9_power_down(st);
473
474 return ret;
475 }
476 EXPORT_SYMBOL(kxsd9_common_probe);
477
478 int kxsd9_common_remove(struct device *dev)
479 {
480 struct iio_dev *indio_dev = dev_get_drvdata(dev);
481 struct kxsd9_state *st = iio_priv(indio_dev);
482
483 iio_triggered_buffer_cleanup(indio_dev);
484 iio_device_unregister(indio_dev);
485 pm_runtime_get_sync(dev);
486 pm_runtime_put_noidle(dev);
487 pm_runtime_disable(dev);
488 kxsd9_power_down(st);
489
490 return 0;
491 }
492 EXPORT_SYMBOL(kxsd9_common_remove);
493
494 #ifdef CONFIG_PM
495 static int kxsd9_runtime_suspend(struct device *dev)
496 {
497 struct iio_dev *indio_dev = dev_get_drvdata(dev);
498 struct kxsd9_state *st = iio_priv(indio_dev);
499
500 return kxsd9_power_down(st);
501 }
502
503 static int kxsd9_runtime_resume(struct device *dev)
504 {
505 struct iio_dev *indio_dev = dev_get_drvdata(dev);
506 struct kxsd9_state *st = iio_priv(indio_dev);
507
508 return kxsd9_power_up(st);
509 }
510 #endif
511
512 const struct dev_pm_ops kxsd9_dev_pm_ops = {
513 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
514 pm_runtime_force_resume)
515 SET_RUNTIME_PM_OPS(kxsd9_runtime_suspend,
516 kxsd9_runtime_resume, NULL)
517 };
518 EXPORT_SYMBOL(kxsd9_dev_pm_ops);
519
520 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
521 MODULE_DESCRIPTION("Kionix KXSD9 driver");
522 MODULE_LICENSE("GPL v2");