drivers/iommu/amd

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This source file includes following definitions.
match_hid_uid
get_pci_device_id
get_acpihid_device_id
get_device_id
to_pdomain
to_dma_ops_domain
alloc_dev_data
search_dev_data
clone_alias
clone_aliases
setup_aliases
find_dev_data
get_dev_data
acpihid_device_group
pci_iommuv2_capable
pdev_pri_erratum
check_device
init_iommu_group
iommu_init_device
iommu_ignore_device
iommu_uninit_device
first_pte_l7
dump_dte_entry
dump_command
amd_iommu_report_page_fault
iommu_print_event
iommu_poll_events
iommu_handle_ppr_entry
iommu_poll_ppr_log
amd_iommu_register_ga_log_notifier
iommu_poll_ga_log
amd_iommu_int_thread
amd_iommu_int_handler
wait_on_sem
copy_cmd_to_buffer
build_completion_wait
build_inv_dte
build_inv_iommu_pages
build_inv_iotlb_pages
build_inv_iommu_pasid
build_inv_iotlb_pasid
build_complete_ppr
build_inv_all
build_inv_irt
__iommu_queue_command_sync
iommu_queue_command_sync
iommu_queue_command
iommu_completion_wait
iommu_flush_dte
amd_iommu_flush_dte_all
amd_iommu_flush_tlb_all
amd_iommu_flush_tlb_domid
amd_iommu_flush_all
iommu_flush_irt
amd_iommu_flush_irt_all
iommu_flush_all_caches
device_flush_iotlb
device_flush_dte_alias
device_flush_dte
__domain_flush_pages
domain_flush_pages
domain_flush_tlb
domain_flush_tlb_pde
domain_flush_complete
domain_flush_np_cache
domain_flush_devices
free_page_list
free_pt_page
DEFINE_FREE_PT_FN
free_pagetable
increase_address_space
alloc_pte
fetch_pte
free_clear_pte
iommu_map_page
iommu_unmap_page
dma_ops_alloc_iova
dma_ops_free_iova
domain_id_alloc
domain_id_free
free_gcr3_tbl_level1
free_gcr3_tbl_level2
free_gcr3_table
dma_ops_domain_flush_tlb
iova_domain_flush_tlb
dma_ops_domain_free
dma_ops_domain_alloc
dma_ops_domain
set_dte_entry
clear_dte_entry
do_attach
do_detach
pdev_iommuv2_disable
pri_reset_while_enabled
pdev_iommuv2_enable
attach_device
detach_device
amd_iommu_add_device
amd_iommu_remove_device
amd_iommu_device_group
get_domain
update_device_table
update_domain
dir2prot
__map_single
__unmap_single
map_page
unmap_page
sg_num_pages
map_sg
unmap_sg
alloc_coherent
free_coherent
amd_iommu_dma_supported
init_reserved_iova_ranges
amd_iommu_init_api
amd_iommu_init_dma_ops
cleanup_domain
protection_domain_free
protection_domain_init
protection_domain_alloc
amd_iommu_domain_alloc
amd_iommu_domain_free
amd_iommu_detach_device
amd_iommu_attach_device
amd_iommu_map
amd_iommu_unmap
amd_iommu_iova_to_phys
amd_iommu_capable
amd_iommu_get_resv_regions
amd_iommu_put_resv_regions
amd_iommu_apply_resv_region
amd_iommu_is_attach_deferred
amd_iommu_flush_iotlb_all
amd_iommu_iotlb_sync
amd_iommu_register_ppr_notifier
amd_iommu_unregister_ppr_notifier
amd_iommu_domain_direct_map
amd_iommu_domain_enable_v2
__flush_pasid
__amd_iommu_flush_page
amd_iommu_flush_page
__amd_iommu_flush_tlb
amd_iommu_flush_tlb
__get_gcr3_pte
__set_gcr3
__clear_gcr3
amd_iommu_domain_set_gcr3
amd_iommu_domain_clear_gcr3
amd_iommu_complete_ppr
amd_iommu_get_v2_domain
amd_iommu_enable_device_erratum
amd_iommu_device_info
set_dte_irq_entry
get_irq_table
__alloc_irq_table
set_remap_table_entry
set_remap_table_entry_alias
alloc_irq_table
alloc_irq_index
modify_irte_ga
modify_irte
free_irte
irte_prepare
irte_ga_prepare
irte_activate
irte_ga_activate
irte_deactivate
irte_ga_deactivate
irte_set_affinity
irte_ga_set_affinity
irte_set_allocated
irte_ga_set_allocated
irte_is_allocated
irte_ga_is_allocated
irte_clear_allocated
irte_ga_clear_allocated
get_devid
get_ir_irq_domain
get_irq_domain
irq_remapping_prepare_irte
irq_remapping_alloc
irq_remapping_free
irq_remapping_activate
irq_remapping_deactivate
amd_iommu_activate_guest_mode
amd_iommu_deactivate_guest_mode
amd_ir_set_vcpu_affinity
amd_ir_update_irte
amd_ir_set_affinity
ir_compose_msi_msg
amd_iommu_create_irq_domain
amd_iommu_update_ga
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   4  * Author: Joerg Roedel <jroedel@suse.de>
   5  *         Leo Duran <leo.duran@amd.com>
   6  */
   7 
   8 #define pr_fmt(fmt)     "AMD-Vi: " fmt
   9 #define dev_fmt(fmt)    pr_fmt(fmt)
  10 
  11 #include <linux/ratelimit.h>
  12 #include <linux/pci.h>
  13 #include <linux/acpi.h>
  14 #include <linux/amba/bus.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pci-ats.h>
  17 #include <linux/bitmap.h>
  18 #include <linux/slab.h>
  19 #include <linux/debugfs.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dma-direct.h>
  23 #include <linux/iommu-helper.h>
  24 #include <linux/iommu.h>
  25 #include <linux/delay.h>
  26 #include <linux/amd-iommu.h>
  27 #include <linux/notifier.h>
  28 #include <linux/export.h>
  29 #include <linux/irq.h>
  30 #include <linux/msi.h>
  31 #include <linux/dma-contiguous.h>
  32 #include <linux/irqdomain.h>
  33 #include <linux/percpu.h>
  34 #include <linux/iova.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/io_apic.h>
  37 #include <asm/apic.h>
  38 #include <asm/hw_irq.h>
  39 #include <asm/msidef.h>
  40 #include <asm/proto.h>
  41 #include <asm/iommu.h>
  42 #include <asm/gart.h>
  43 #include <asm/dma.h>
  44 
  45 #include "amd_iommu_proto.h"
  46 #include "amd_iommu_types.h"
  47 #include "irq_remapping.h"
  48 
  49 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
  50 
  51 #define LOOP_TIMEOUT    100000
  52 
  53 /* IO virtual address start page frame number */
  54 #define IOVA_START_PFN          (1)
  55 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
  56 
  57 /* Reserved IOVA ranges */
  58 #define MSI_RANGE_START         (0xfee00000)
  59 #define MSI_RANGE_END           (0xfeefffff)
  60 #define HT_RANGE_START          (0xfd00000000ULL)
  61 #define HT_RANGE_END            (0xffffffffffULL)
  62 
  63 /*
  64  * This bitmap is used to advertise the page sizes our hardware support
  65  * to the IOMMU core, which will then use this information to split
  66  * physically contiguous memory regions it is mapping into page sizes
  67  * that we support.
  68  *
  69  * 512GB Pages are not supported due to a hardware bug
  70  */
  71 #define AMD_IOMMU_PGSIZES       ((~0xFFFUL) & ~(2ULL << 38))
  72 
  73 static DEFINE_SPINLOCK(pd_bitmap_lock);
  74 
  75 /* List of all available dev_data structures */
  76 static LLIST_HEAD(dev_data_list);
  77 
  78 LIST_HEAD(ioapic_map);
  79 LIST_HEAD(hpet_map);
  80 LIST_HEAD(acpihid_map);
  81 
  82 /*
  83  * Domain for untranslated devices - only allocated
  84  * if iommu=pt passed on kernel cmd line.
  85  */
  86 const struct iommu_ops amd_iommu_ops;
  87 
  88 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
  89 int amd_iommu_max_glx_val = -1;
  90 
  91 static const struct dma_map_ops amd_iommu_dma_ops;
  92 
  93 /*
  94  * general struct to manage commands send to an IOMMU
  95  */
  96 struct iommu_cmd {
  97         u32 data[4];
  98 };
  99 
 100 struct kmem_cache *amd_iommu_irq_cache;
 101 
 102 static void update_domain(struct protection_domain *domain);
 103 static int protection_domain_init(struct protection_domain *domain);
 104 static void detach_device(struct device *dev);
 105 static void iova_domain_flush_tlb(struct iova_domain *iovad);
 106 
 107 /*
 108  * Data container for a dma_ops specific protection domain
 109  */
 110 struct dma_ops_domain {
 111         /* generic protection domain information */
 112         struct protection_domain domain;
 113 
 114         /* IOVA RB-Tree */
 115         struct iova_domain iovad;
 116 };
 117 
 118 static struct iova_domain reserved_iova_ranges;
 119 static struct lock_class_key reserved_rbtree_key;
 120 
 121 /****************************************************************************
 122  *
 123  * Helper functions
 124  *
 125  ****************************************************************************/
 126 
 127 static inline int match_hid_uid(struct device *dev,
 128                                 struct acpihid_map_entry *entry)
 129 {
 130         struct acpi_device *adev = ACPI_COMPANION(dev);
 131         const char *hid, *uid;
 132 
 133         if (!adev)
 134                 return -ENODEV;
 135 
 136         hid = acpi_device_hid(adev);
 137         uid = acpi_device_uid(adev);
 138 
 139         if (!hid || !(*hid))
 140                 return -ENODEV;
 141 
 142         if (!uid || !(*uid))
 143                 return strcmp(hid, entry->hid);
 144 
 145         if (!(*entry->uid))
 146                 return strcmp(hid, entry->hid);
 147 
 148         return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
 149 }
 150 
 151 static inline u16 get_pci_device_id(struct device *dev)
 152 {
 153         struct pci_dev *pdev = to_pci_dev(dev);
 154 
 155         return pci_dev_id(pdev);
 156 }
 157 
 158 static inline int get_acpihid_device_id(struct device *dev,
 159                                         struct acpihid_map_entry **entry)
 160 {
 161         struct acpihid_map_entry *p;
 162 
 163         list_for_each_entry(p, &acpihid_map, list) {
 164                 if (!match_hid_uid(dev, p)) {
 165                         if (entry)
 166                                 *entry = p;
 167                         return p->devid;
 168                 }
 169         }
 170         return -EINVAL;
 171 }
 172 
 173 static inline int get_device_id(struct device *dev)
 174 {
 175         int devid;
 176 
 177         if (dev_is_pci(dev))
 178                 devid = get_pci_device_id(dev);
 179         else
 180                 devid = get_acpihid_device_id(dev, NULL);
 181 
 182         return devid;
 183 }
 184 
 185 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
 186 {
 187         return container_of(dom, struct protection_domain, domain);
 188 }
 189 
 190 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
 191 {
 192         BUG_ON(domain->flags != PD_DMA_OPS_MASK);
 193         return container_of(domain, struct dma_ops_domain, domain);
 194 }
 195 
 196 static struct iommu_dev_data *alloc_dev_data(u16 devid)
 197 {
 198         struct iommu_dev_data *dev_data;
 199 
 200         dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
 201         if (!dev_data)
 202                 return NULL;
 203 
 204         spin_lock_init(&dev_data->lock);
 205         dev_data->devid = devid;
 206         ratelimit_default_init(&dev_data->rs);
 207 
 208         llist_add(&dev_data->dev_data_list, &dev_data_list);
 209         return dev_data;
 210 }
 211 
 212 static struct iommu_dev_data *search_dev_data(u16 devid)
 213 {
 214         struct iommu_dev_data *dev_data;
 215         struct llist_node *node;
 216 
 217         if (llist_empty(&dev_data_list))
 218                 return NULL;
 219 
 220         node = dev_data_list.first;
 221         llist_for_each_entry(dev_data, node, dev_data_list) {
 222                 if (dev_data->devid == devid)
 223                         return dev_data;
 224         }
 225 
 226         return NULL;
 227 }
 228 
 229 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
 230 {
 231         u16 devid = pci_dev_id(pdev);
 232 
 233         if (devid == alias)
 234                 return 0;
 235 
 236         amd_iommu_rlookup_table[alias] =
 237                 amd_iommu_rlookup_table[devid];
 238         memcpy(amd_iommu_dev_table[alias].data,
 239                amd_iommu_dev_table[devid].data,
 240                sizeof(amd_iommu_dev_table[alias].data));
 241 
 242         return 0;
 243 }
 244 
 245 static void clone_aliases(struct pci_dev *pdev)
 246 {
 247         if (!pdev)
 248                 return;
 249 
 250         /*
 251          * The IVRS alias stored in the alias table may not be
 252          * part of the PCI DMA aliases if it's bus differs
 253          * from the original device.
 254          */
 255         clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
 256 
 257         pci_for_each_dma_alias(pdev, clone_alias, NULL);
 258 }
 259 
 260 static struct pci_dev *setup_aliases(struct device *dev)
 261 {
 262         struct pci_dev *pdev = to_pci_dev(dev);
 263         u16 ivrs_alias;
 264 
 265         /* For ACPI HID devices, there are no aliases */
 266         if (!dev_is_pci(dev))
 267                 return NULL;
 268 
 269         /*
 270          * Add the IVRS alias to the pci aliases if it is on the same
 271          * bus. The IVRS table may know about a quirk that we don't.
 272          */
 273         ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
 274         if (ivrs_alias != pci_dev_id(pdev) &&
 275             PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
 276                 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
 277 
 278         clone_aliases(pdev);
 279 
 280         return pdev;
 281 }
 282 
 283 static struct iommu_dev_data *find_dev_data(u16 devid)
 284 {
 285         struct iommu_dev_data *dev_data;
 286         struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
 287 
 288         dev_data = search_dev_data(devid);
 289 
 290         if (dev_data == NULL) {
 291                 dev_data = alloc_dev_data(devid);
 292                 if (!dev_data)
 293                         return NULL;
 294 
 295                 if (translation_pre_enabled(iommu))
 296                         dev_data->defer_attach = true;
 297         }
 298 
 299         return dev_data;
 300 }
 301 
 302 struct iommu_dev_data *get_dev_data(struct device *dev)
 303 {
 304         return dev->archdata.iommu;
 305 }
 306 EXPORT_SYMBOL(get_dev_data);
 307 
 308 /*
 309 * Find or create an IOMMU group for a acpihid device.
 310 */
 311 static struct iommu_group *acpihid_device_group(struct device *dev)
 312 {
 313         struct acpihid_map_entry *p, *entry = NULL;
 314         int devid;
 315 
 316         devid = get_acpihid_device_id(dev, &entry);
 317         if (devid < 0)
 318                 return ERR_PTR(devid);
 319 
 320         list_for_each_entry(p, &acpihid_map, list) {
 321                 if ((devid == p->devid) && p->group)
 322                         entry->group = p->group;
 323         }
 324 
 325         if (!entry->group)
 326                 entry->group = generic_device_group(dev);
 327         else
 328                 iommu_group_ref_get(entry->group);
 329 
 330         return entry->group;
 331 }
 332 
 333 static bool pci_iommuv2_capable(struct pci_dev *pdev)
 334 {
 335         static const int caps[] = {
 336                 PCI_EXT_CAP_ID_ATS,
 337                 PCI_EXT_CAP_ID_PRI,
 338                 PCI_EXT_CAP_ID_PASID,
 339         };
 340         int i, pos;
 341 
 342         if (pci_ats_disabled())
 343                 return false;
 344 
 345         for (i = 0; i < 3; ++i) {
 346                 pos = pci_find_ext_capability(pdev, caps[i]);
 347                 if (pos == 0)
 348                         return false;
 349         }
 350 
 351         return true;
 352 }
 353 
 354 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
 355 {
 356         struct iommu_dev_data *dev_data;
 357 
 358         dev_data = get_dev_data(&pdev->dev);
 359 
 360         return dev_data->errata & (1 << erratum) ? true : false;
 361 }
 362 
 363 /*
 364  * This function checks if the driver got a valid device from the caller to
 365  * avoid dereferencing invalid pointers.
 366  */
 367 static bool check_device(struct device *dev)
 368 {
 369         int devid;
 370 
 371         if (!dev || !dev->dma_mask)
 372                 return false;
 373 
 374         devid = get_device_id(dev);
 375         if (devid < 0)
 376                 return false;
 377 
 378         /* Out of our scope? */
 379         if (devid > amd_iommu_last_bdf)
 380                 return false;
 381 
 382         if (amd_iommu_rlookup_table[devid] == NULL)
 383                 return false;
 384 
 385         return true;
 386 }
 387 
 388 static void init_iommu_group(struct device *dev)
 389 {
 390         struct iommu_group *group;
 391 
 392         group = iommu_group_get_for_dev(dev);
 393         if (IS_ERR(group))
 394                 return;
 395 
 396         iommu_group_put(group);
 397 }
 398 
 399 static int iommu_init_device(struct device *dev)
 400 {
 401         struct iommu_dev_data *dev_data;
 402         struct amd_iommu *iommu;
 403         int devid;
 404 
 405         if (dev->archdata.iommu)
 406                 return 0;
 407 
 408         devid = get_device_id(dev);
 409         if (devid < 0)
 410                 return devid;
 411 
 412         iommu = amd_iommu_rlookup_table[devid];
 413 
 414         dev_data = find_dev_data(devid);
 415         if (!dev_data)
 416                 return -ENOMEM;
 417 
 418         dev_data->pdev = setup_aliases(dev);
 419 
 420         /*
 421          * By default we use passthrough mode for IOMMUv2 capable device.
 422          * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
 423          * invalid address), we ignore the capability for the device so
 424          * it'll be forced to go into translation mode.
 425          */
 426         if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
 427             dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
 428                 struct amd_iommu *iommu;
 429 
 430                 iommu = amd_iommu_rlookup_table[dev_data->devid];
 431                 dev_data->iommu_v2 = iommu->is_iommu_v2;
 432         }
 433 
 434         dev->archdata.iommu = dev_data;
 435 
 436         iommu_device_link(&iommu->iommu, dev);
 437 
 438         return 0;
 439 }
 440 
 441 static void iommu_ignore_device(struct device *dev)
 442 {
 443         int devid;
 444 
 445         devid = get_device_id(dev);
 446         if (devid < 0)
 447                 return;
 448 
 449         amd_iommu_rlookup_table[devid] = NULL;
 450         memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
 451 
 452         setup_aliases(dev);
 453 }
 454 
 455 static void iommu_uninit_device(struct device *dev)
 456 {
 457         struct iommu_dev_data *dev_data;
 458         struct amd_iommu *iommu;
 459         int devid;
 460 
 461         devid = get_device_id(dev);
 462         if (devid < 0)
 463                 return;
 464 
 465         iommu = amd_iommu_rlookup_table[devid];
 466 
 467         dev_data = search_dev_data(devid);
 468         if (!dev_data)
 469                 return;
 470 
 471         if (dev_data->domain)
 472                 detach_device(dev);
 473 
 474         iommu_device_unlink(&iommu->iommu, dev);
 475 
 476         iommu_group_remove_device(dev);
 477 
 478         /* Remove dma-ops */
 479         dev->dma_ops = NULL;
 480 
 481         /*
 482          * We keep dev_data around for unplugged devices and reuse it when the
 483          * device is re-plugged - not doing so would introduce a ton of races.
 484          */
 485 }
 486 
 487 /*
 488  * Helper function to get the first pte of a large mapping
 489  */
 490 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
 491                          unsigned long *count)
 492 {
 493         unsigned long pte_mask, pg_size, cnt;
 494         u64 *fpte;
 495 
 496         pg_size  = PTE_PAGE_SIZE(*pte);
 497         cnt      = PAGE_SIZE_PTE_COUNT(pg_size);
 498         pte_mask = ~((cnt << 3) - 1);
 499         fpte     = (u64 *)(((unsigned long)pte) & pte_mask);
 500 
 501         if (page_size)
 502                 *page_size = pg_size;
 503 
 504         if (count)
 505                 *count = cnt;
 506 
 507         return fpte;
 508 }
 509 
 510 /****************************************************************************
 511  *
 512  * Interrupt handling functions
 513  *
 514  ****************************************************************************/
 515 
 516 static void dump_dte_entry(u16 devid)
 517 {
 518         int i;
 519 
 520         for (i = 0; i < 4; ++i)
 521                 pr_err("DTE[%d]: %016llx\n", i,
 522                         amd_iommu_dev_table[devid].data[i]);
 523 }
 524 
 525 static void dump_command(unsigned long phys_addr)
 526 {
 527         struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
 528         int i;
 529 
 530         for (i = 0; i < 4; ++i)
 531                 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
 532 }
 533 
 534 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
 535                                         u64 address, int flags)
 536 {
 537         struct iommu_dev_data *dev_data = NULL;
 538         struct pci_dev *pdev;
 539 
 540         pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
 541                                            devid & 0xff);
 542         if (pdev)
 543                 dev_data = get_dev_data(&pdev->dev);
 544 
 545         if (dev_data && __ratelimit(&dev_data->rs)) {
 546                 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
 547                         domain_id, address, flags);
 548         } else if (printk_ratelimit()) {
 549                 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
 550                         PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
 551                         domain_id, address, flags);
 552         }
 553 
 554         if (pdev)
 555                 pci_dev_put(pdev);
 556 }
 557 
 558 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
 559 {
 560         struct device *dev = iommu->iommu.dev;
 561         int type, devid, pasid, flags, tag;
 562         volatile u32 *event = __evt;
 563         int count = 0;
 564         u64 address;
 565 
 566 retry:
 567         type    = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;
 568         devid   = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
 569         pasid   = (event[0] & EVENT_DOMID_MASK_HI) |
 570                   (event[1] & EVENT_DOMID_MASK_LO);
 571         flags   = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
 572         address = (u64)(((u64)event[3]) << 32) | event[2];
 573 
 574         if (type == 0) {
 575                 /* Did we hit the erratum? */
 576                 if (++count == LOOP_TIMEOUT) {
 577                         pr_err("No event written to event log\n");
 578                         return;
 579                 }
 580                 udelay(1);
 581                 goto retry;
 582         }
 583 
 584         if (type == EVENT_TYPE_IO_FAULT) {
 585                 amd_iommu_report_page_fault(devid, pasid, address, flags);
 586                 return;
 587         }
 588 
 589         switch (type) {
 590         case EVENT_TYPE_ILL_DEV:
 591                 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
 592                         PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
 593                         pasid, address, flags);
 594                 dump_dte_entry(devid);
 595                 break;
 596         case EVENT_TYPE_DEV_TAB_ERR:
 597                 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
 598                         "address=0x%llx flags=0x%04x]\n",
 599                         PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
 600                         address, flags);
 601                 break;
 602         case EVENT_TYPE_PAGE_TAB_ERR:
 603                 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
 604                         PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
 605                         pasid, address, flags);
 606                 break;
 607         case EVENT_TYPE_ILL_CMD:
 608                 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
 609                 dump_command(address);
 610                 break;
 611         case EVENT_TYPE_CMD_HARD_ERR:
 612                 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
 613                         address, flags);
 614                 break;
 615         case EVENT_TYPE_IOTLB_INV_TO:
 616                 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
 617                         PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
 618                         address);
 619                 break;
 620         case EVENT_TYPE_INV_DEV_REQ:
 621                 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
 622                         PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
 623                         pasid, address, flags);
 624                 break;
 625         case EVENT_TYPE_INV_PPR_REQ:
 626                 pasid = ((event[0] >> 16) & 0xFFFF)
 627                         | ((event[1] << 6) & 0xF0000);
 628                 tag = event[1] & 0x03FF;
 629                 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
 630                         PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
 631                         pasid, address, flags, tag);
 632                 break;
 633         default:
 634                 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
 635                         event[0], event[1], event[2], event[3]);
 636         }
 637 
 638         memset(__evt, 0, 4 * sizeof(u32));
 639 }
 640 
 641 static void iommu_poll_events(struct amd_iommu *iommu)
 642 {
 643         u32 head, tail;
 644 
 645         head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
 646         tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
 647 
 648         while (head != tail) {
 649                 iommu_print_event(iommu, iommu->evt_buf + head);
 650                 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
 651         }
 652 
 653         writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
 654 }
 655 
 656 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
 657 {
 658         struct amd_iommu_fault fault;
 659 
 660         if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
 661                 pr_err_ratelimited("Unknown PPR request received\n");
 662                 return;
 663         }
 664 
 665         fault.address   = raw[1];
 666         fault.pasid     = PPR_PASID(raw[0]);
 667         fault.device_id = PPR_DEVID(raw[0]);
 668         fault.tag       = PPR_TAG(raw[0]);
 669         fault.flags     = PPR_FLAGS(raw[0]);
 670 
 671         atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
 672 }
 673 
 674 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
 675 {
 676         u32 head, tail;
 677 
 678         if (iommu->ppr_log == NULL)
 679                 return;
 680 
 681         head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
 682         tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
 683 
 684         while (head != tail) {
 685                 volatile u64 *raw;
 686                 u64 entry[2];
 687                 int i;
 688 
 689                 raw = (u64 *)(iommu->ppr_log + head);
 690 
 691                 /*
 692                  * Hardware bug: Interrupt may arrive before the entry is
 693                  * written to memory. If this happens we need to wait for the
 694                  * entry to arrive.
 695                  */
 696                 for (i = 0; i < LOOP_TIMEOUT; ++i) {
 697                         if (PPR_REQ_TYPE(raw[0]) != 0)
 698                                 break;
 699                         udelay(1);
 700                 }
 701 
 702                 /* Avoid memcpy function-call overhead */
 703                 entry[0] = raw[0];
 704                 entry[1] = raw[1];
 705 
 706                 /*
 707                  * To detect the hardware bug we need to clear the entry
 708                  * back to zero.
 709                  */
 710                 raw[0] = raw[1] = 0UL;
 711 
 712                 /* Update head pointer of hardware ring-buffer */
 713                 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
 714                 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
 715 
 716                 /* Handle PPR entry */
 717                 iommu_handle_ppr_entry(iommu, entry);
 718 
 719                 /* Refresh ring-buffer information */
 720                 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
 721                 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
 722         }
 723 }
 724 
 725 #ifdef CONFIG_IRQ_REMAP
 726 static int (*iommu_ga_log_notifier)(u32);
 727 
 728 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
 729 {
 730         iommu_ga_log_notifier = notifier;
 731 
 732         return 0;
 733 }
 734 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
 735 
 736 static void iommu_poll_ga_log(struct amd_iommu *iommu)
 737 {
 738         u32 head, tail, cnt = 0;
 739 
 740         if (iommu->ga_log == NULL)
 741                 return;
 742 
 743         head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
 744         tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
 745 
 746         while (head != tail) {
 747                 volatile u64 *raw;
 748                 u64 log_entry;
 749 
 750                 raw = (u64 *)(iommu->ga_log + head);
 751                 cnt++;
 752 
 753                 /* Avoid memcpy function-call overhead */
 754                 log_entry = *raw;
 755 
 756                 /* Update head pointer of hardware ring-buffer */
 757                 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
 758                 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
 759 
 760                 /* Handle GA entry */
 761                 switch (GA_REQ_TYPE(log_entry)) {
 762                 case GA_GUEST_NR:
 763                         if (!iommu_ga_log_notifier)
 764                                 break;
 765 
 766                         pr_debug("%s: devid=%#x, ga_tag=%#x\n",
 767                                  __func__, GA_DEVID(log_entry),
 768                                  GA_TAG(log_entry));
 769 
 770                         if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
 771                                 pr_err("GA log notifier failed.\n");
 772                         break;
 773                 default:
 774                         break;
 775                 }
 776         }
 777 }
 778 #endif /* CONFIG_IRQ_REMAP */
 779 
 780 #define AMD_IOMMU_INT_MASK      \
 781         (MMIO_STATUS_EVT_INT_MASK | \
 782          MMIO_STATUS_PPR_INT_MASK | \
 783          MMIO_STATUS_GALOG_INT_MASK)
 784 
 785 irqreturn_t amd_iommu_int_thread(int irq, void *data)
 786 {
 787         struct amd_iommu *iommu = (struct amd_iommu *) data;
 788         u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
 789 
 790         while (status & AMD_IOMMU_INT_MASK) {
 791                 /* Enable EVT and PPR and GA interrupts again */
 792                 writel(AMD_IOMMU_INT_MASK,
 793                         iommu->mmio_base + MMIO_STATUS_OFFSET);
 794 
 795                 if (status & MMIO_STATUS_EVT_INT_MASK) {
 796                         pr_devel("Processing IOMMU Event Log\n");
 797                         iommu_poll_events(iommu);
 798                 }
 799 
 800                 if (status & MMIO_STATUS_PPR_INT_MASK) {
 801                         pr_devel("Processing IOMMU PPR Log\n");
 802                         iommu_poll_ppr_log(iommu);
 803                 }
 804 
 805 #ifdef CONFIG_IRQ_REMAP
 806                 if (status & MMIO_STATUS_GALOG_INT_MASK) {
 807                         pr_devel("Processing IOMMU GA Log\n");
 808                         iommu_poll_ga_log(iommu);
 809                 }
 810 #endif
 811 
 812                 /*
 813                  * Hardware bug: ERBT1312
 814                  * When re-enabling interrupt (by writing 1
 815                  * to clear the bit), the hardware might also try to set
 816                  * the interrupt bit in the event status register.
 817                  * In this scenario, the bit will be set, and disable
 818                  * subsequent interrupts.
 819                  *
 820                  * Workaround: The IOMMU driver should read back the
 821                  * status register and check if the interrupt bits are cleared.
 822                  * If not, driver will need to go through the interrupt handler
 823                  * again and re-clear the bits
 824                  */
 825                 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
 826         }
 827         return IRQ_HANDLED;
 828 }
 829 
 830 irqreturn_t amd_iommu_int_handler(int irq, void *data)
 831 {
 832         return IRQ_WAKE_THREAD;
 833 }
 834 
 835 /****************************************************************************
 836  *
 837  * IOMMU command queuing functions
 838  *
 839  ****************************************************************************/
 840 
 841 static int wait_on_sem(volatile u64 *sem)
 842 {
 843         int i = 0;
 844 
 845         while (*sem == 0 && i < LOOP_TIMEOUT) {
 846                 udelay(1);
 847                 i += 1;
 848         }
 849 
 850         if (i == LOOP_TIMEOUT) {
 851                 pr_alert("Completion-Wait loop timed out\n");
 852                 return -EIO;
 853         }
 854 
 855         return 0;
 856 }
 857 
 858 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
 859                                struct iommu_cmd *cmd)
 860 {
 861         u8 *target;
 862 
 863         target = iommu->cmd_buf + iommu->cmd_buf_tail;
 864 
 865         iommu->cmd_buf_tail += sizeof(*cmd);
 866         iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
 867 
 868         /* Copy command to buffer */
 869         memcpy(target, cmd, sizeof(*cmd));
 870 
 871         /* Tell the IOMMU about it */
 872         writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
 873 }
 874 
 875 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
 876 {
 877         u64 paddr = iommu_virt_to_phys((void *)address);
 878 
 879         WARN_ON(address & 0x7ULL);
 880 
 881         memset(cmd, 0, sizeof(*cmd));
 882         cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
 883         cmd->data[1] = upper_32_bits(paddr);
 884         cmd->data[2] = 1;
 885         CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
 886 }
 887 
 888 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
 889 {
 890         memset(cmd, 0, sizeof(*cmd));
 891         cmd->data[0] = devid;
 892         CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
 893 }
 894 
 895 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
 896                                   size_t size, u16 domid, int pde)
 897 {
 898         u64 pages;
 899         bool s;
 900 
 901         pages = iommu_num_pages(address, size, PAGE_SIZE);
 902         s     = false;
 903 
 904         if (pages > 1) {
 905                 /*
 906                  * If we have to flush more than one page, flush all
 907                  * TLB entries for this domain
 908                  */
 909                 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
 910                 s = true;
 911         }
 912 
 913         address &= PAGE_MASK;
 914 
 915         memset(cmd, 0, sizeof(*cmd));
 916         cmd->data[1] |= domid;
 917         cmd->data[2]  = lower_32_bits(address);
 918         cmd->data[3]  = upper_32_bits(address);
 919         CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
 920         if (s) /* size bit - we flush more than one 4kb page */
 921                 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
 922         if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
 923                 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
 924 }
 925 
 926 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
 927                                   u64 address, size_t size)
 928 {
 929         u64 pages;
 930         bool s;
 931 
 932         pages = iommu_num_pages(address, size, PAGE_SIZE);
 933         s     = false;
 934 
 935         if (pages > 1) {
 936                 /*
 937                  * If we have to flush more than one page, flush all
 938                  * TLB entries for this domain
 939                  */
 940                 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
 941                 s = true;
 942         }
 943 
 944         address &= PAGE_MASK;
 945 
 946         memset(cmd, 0, sizeof(*cmd));
 947         cmd->data[0]  = devid;
 948         cmd->data[0] |= (qdep & 0xff) << 24;
 949         cmd->data[1]  = devid;
 950         cmd->data[2]  = lower_32_bits(address);
 951         cmd->data[3]  = upper_32_bits(address);
 952         CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
 953         if (s)
 954                 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
 955 }
 956 
 957 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
 958                                   u64 address, bool size)
 959 {
 960         memset(cmd, 0, sizeof(*cmd));
 961 
 962         address &= ~(0xfffULL);
 963 
 964         cmd->data[0]  = pasid;
 965         cmd->data[1]  = domid;
 966         cmd->data[2]  = lower_32_bits(address);
 967         cmd->data[3]  = upper_32_bits(address);
 968         cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
 969         cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
 970         if (size)
 971                 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
 972         CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
 973 }
 974 
 975 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
 976                                   int qdep, u64 address, bool size)
 977 {
 978         memset(cmd, 0, sizeof(*cmd));
 979 
 980         address &= ~(0xfffULL);
 981 
 982         cmd->data[0]  = devid;
 983         cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
 984         cmd->data[0] |= (qdep  & 0xff) << 24;
 985         cmd->data[1]  = devid;
 986         cmd->data[1] |= (pasid & 0xff) << 16;
 987         cmd->data[2]  = lower_32_bits(address);
 988         cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
 989         cmd->data[3]  = upper_32_bits(address);
 990         if (size)
 991                 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
 992         CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
 993 }
 994 
 995 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
 996                                int status, int tag, bool gn)
 997 {
 998         memset(cmd, 0, sizeof(*cmd));
 999 
1000         cmd->data[0]  = devid;
1001         if (gn) {
1002                 cmd->data[1]  = pasid;
1003                 cmd->data[2]  = CMD_INV_IOMMU_PAGES_GN_MASK;
1004         }
1005         cmd->data[3]  = tag & 0x1ff;
1006         cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1007 
1008         CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1009 }
1010 
1011 static void build_inv_all(struct iommu_cmd *cmd)
1012 {
1013         memset(cmd, 0, sizeof(*cmd));
1014         CMD_SET_TYPE(cmd, CMD_INV_ALL);
1015 }
1016 
1017 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1018 {
1019         memset(cmd, 0, sizeof(*cmd));
1020         cmd->data[0] = devid;
1021         CMD_SET_TYPE(cmd, CMD_INV_IRT);
1022 }
1023 
1024 /*
1025  * Writes the command to the IOMMUs command buffer and informs the
1026  * hardware about the new command.
1027  */
1028 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1029                                       struct iommu_cmd *cmd,
1030                                       bool sync)
1031 {
1032         unsigned int count = 0;
1033         u32 left, next_tail;
1034 
1035         next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1036 again:
1037         left      = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1038 
1039         if (left <= 0x20) {
1040                 /* Skip udelay() the first time around */
1041                 if (count++) {
1042                         if (count == LOOP_TIMEOUT) {
1043                                 pr_err("Command buffer timeout\n");
1044                                 return -EIO;
1045                         }
1046 
1047                         udelay(1);
1048                 }
1049 
1050                 /* Update head and recheck remaining space */
1051                 iommu->cmd_buf_head = readl(iommu->mmio_base +
1052                                             MMIO_CMD_HEAD_OFFSET);
1053 
1054                 goto again;
1055         }
1056 
1057         copy_cmd_to_buffer(iommu, cmd);
1058 
1059         /* Do we need to make sure all commands are processed? */
1060         iommu->need_sync = sync;
1061 
1062         return 0;
1063 }
1064 
1065 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1066                                     struct iommu_cmd *cmd,
1067                                     bool sync)
1068 {
1069         unsigned long flags;
1070         int ret;
1071 
1072         raw_spin_lock_irqsave(&iommu->lock, flags);
1073         ret = __iommu_queue_command_sync(iommu, cmd, sync);
1074         raw_spin_unlock_irqrestore(&iommu->lock, flags);
1075 
1076         return ret;
1077 }
1078 
1079 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1080 {
1081         return iommu_queue_command_sync(iommu, cmd, true);
1082 }
1083 
1084 /*
1085  * This function queues a completion wait command into the command
1086  * buffer of an IOMMU
1087  */
1088 static int iommu_completion_wait(struct amd_iommu *iommu)
1089 {
1090         struct iommu_cmd cmd;
1091         unsigned long flags;
1092         int ret;
1093 
1094         if (!iommu->need_sync)
1095                 return 0;
1096 
1097 
1098         build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1099 
1100         raw_spin_lock_irqsave(&iommu->lock, flags);
1101 
1102         iommu->cmd_sem = 0;
1103 
1104         ret = __iommu_queue_command_sync(iommu, &cmd, false);
1105         if (ret)
1106                 goto out_unlock;
1107 
1108         ret = wait_on_sem(&iommu->cmd_sem);
1109 
1110 out_unlock:
1111         raw_spin_unlock_irqrestore(&iommu->lock, flags);
1112 
1113         return ret;
1114 }
1115 
1116 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1117 {
1118         struct iommu_cmd cmd;
1119 
1120         build_inv_dte(&cmd, devid);
1121 
1122         return iommu_queue_command(iommu, &cmd);
1123 }
1124 
1125 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1126 {
1127         u32 devid;
1128 
1129         for (devid = 0; devid <= 0xffff; ++devid)
1130                 iommu_flush_dte(iommu, devid);
1131 
1132         iommu_completion_wait(iommu);
1133 }
1134 
1135 /*
1136  * This function uses heavy locking and may disable irqs for some time. But
1137  * this is no issue because it is only called during resume.
1138  */
1139 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1140 {
1141         u32 dom_id;
1142 
1143         for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1144                 struct iommu_cmd cmd;
1145                 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1146                                       dom_id, 1);
1147                 iommu_queue_command(iommu, &cmd);
1148         }
1149 
1150         iommu_completion_wait(iommu);
1151 }
1152 
1153 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1154 {
1155         struct iommu_cmd cmd;
1156 
1157         build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1158                               dom_id, 1);
1159         iommu_queue_command(iommu, &cmd);
1160 
1161         iommu_completion_wait(iommu);
1162 }
1163 
1164 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1165 {
1166         struct iommu_cmd cmd;
1167 
1168         build_inv_all(&cmd);
1169 
1170         iommu_queue_command(iommu, &cmd);
1171         iommu_completion_wait(iommu);
1172 }
1173 
1174 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1175 {
1176         struct iommu_cmd cmd;
1177 
1178         build_inv_irt(&cmd, devid);
1179 
1180         iommu_queue_command(iommu, &cmd);
1181 }
1182 
1183 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1184 {
1185         u32 devid;
1186 
1187         for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1188                 iommu_flush_irt(iommu, devid);
1189 
1190         iommu_completion_wait(iommu);
1191 }
1192 
1193 void iommu_flush_all_caches(struct amd_iommu *iommu)
1194 {
1195         if (iommu_feature(iommu, FEATURE_IA)) {
1196                 amd_iommu_flush_all(iommu);
1197         } else {
1198                 amd_iommu_flush_dte_all(iommu);
1199                 amd_iommu_flush_irt_all(iommu);
1200                 amd_iommu_flush_tlb_all(iommu);
1201         }
1202 }
1203 
1204 /*
1205  * Command send function for flushing on-device TLB
1206  */
1207 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1208                               u64 address, size_t size)
1209 {
1210         struct amd_iommu *iommu;
1211         struct iommu_cmd cmd;
1212         int qdep;
1213 
1214         qdep     = dev_data->ats.qdep;
1215         iommu    = amd_iommu_rlookup_table[dev_data->devid];
1216 
1217         build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1218 
1219         return iommu_queue_command(iommu, &cmd);
1220 }
1221 
1222 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1223 {
1224         struct amd_iommu *iommu = data;
1225 
1226         return iommu_flush_dte(iommu, alias);
1227 }
1228 
1229 /*
1230  * Command send function for invalidating a device table entry
1231  */
1232 static int device_flush_dte(struct iommu_dev_data *dev_data)
1233 {
1234         struct amd_iommu *iommu;
1235         u16 alias;
1236         int ret;
1237 
1238         iommu = amd_iommu_rlookup_table[dev_data->devid];
1239 
1240         if (dev_data->pdev)
1241                 ret = pci_for_each_dma_alias(dev_data->pdev,
1242                                              device_flush_dte_alias, iommu);
1243         else
1244                 ret = iommu_flush_dte(iommu, dev_data->devid);
1245         if (ret)
1246                 return ret;
1247 
1248         alias = amd_iommu_alias_table[dev_data->devid];
1249         if (alias != dev_data->devid) {
1250                 ret = iommu_flush_dte(iommu, alias);
1251                 if (ret)
1252                         return ret;
1253         }
1254 
1255         if (dev_data->ats.enabled)
1256                 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1257 
1258         return ret;
1259 }
1260 
1261 /*
1262  * TLB invalidation function which is called from the mapping functions.
1263  * It invalidates a single PTE if the range to flush is within a single
1264  * page. Otherwise it flushes the whole TLB of the IOMMU.
1265  */
1266 static void __domain_flush_pages(struct protection_domain *domain,
1267                                  u64 address, size_t size, int pde)
1268 {
1269         struct iommu_dev_data *dev_data;
1270         struct iommu_cmd cmd;
1271         int ret = 0, i;
1272 
1273         build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1274 
1275         for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1276                 if (!domain->dev_iommu[i])
1277                         continue;
1278 
1279                 /*
1280                  * Devices of this domain are behind this IOMMU
1281                  * We need a TLB flush
1282                  */
1283                 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1284         }
1285 
1286         list_for_each_entry(dev_data, &domain->dev_list, list) {
1287 
1288                 if (!dev_data->ats.enabled)
1289                         continue;
1290 
1291                 ret |= device_flush_iotlb(dev_data, address, size);
1292         }
1293 
1294         WARN_ON(ret);
1295 }
1296 
1297 static void domain_flush_pages(struct protection_domain *domain,
1298                                u64 address, size_t size)
1299 {
1300         __domain_flush_pages(domain, address, size, 0);
1301 }
1302 
1303 /* Flush the whole IO/TLB for a given protection domain */
1304 static void domain_flush_tlb(struct protection_domain *domain)
1305 {
1306         __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1307 }
1308 
1309 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1310 static void domain_flush_tlb_pde(struct protection_domain *domain)
1311 {
1312         __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1313 }
1314 
1315 static void domain_flush_complete(struct protection_domain *domain)
1316 {
1317         int i;
1318 
1319         for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1320                 if (domain && !domain->dev_iommu[i])
1321                         continue;
1322 
1323                 /*
1324                  * Devices of this domain are behind this IOMMU
1325                  * We need to wait for completion of all commands.
1326                  */
1327                 iommu_completion_wait(amd_iommus[i]);
1328         }
1329 }
1330 
1331 /* Flush the not present cache if it exists */
1332 static void domain_flush_np_cache(struct protection_domain *domain,
1333                 dma_addr_t iova, size_t size)
1334 {
1335         if (unlikely(amd_iommu_np_cache)) {
1336                 unsigned long flags;
1337 
1338                 spin_lock_irqsave(&domain->lock, flags);
1339                 domain_flush_pages(domain, iova, size);
1340                 domain_flush_complete(domain);
1341                 spin_unlock_irqrestore(&domain->lock, flags);
1342         }
1343 }
1344 
1345 
1346 /*
1347  * This function flushes the DTEs for all devices in domain
1348  */
1349 static void domain_flush_devices(struct protection_domain *domain)
1350 {
1351         struct iommu_dev_data *dev_data;
1352 
1353         list_for_each_entry(dev_data, &domain->dev_list, list)
1354                 device_flush_dte(dev_data);
1355 }
1356 
1357 /****************************************************************************
1358  *
1359  * The functions below are used the create the page table mappings for
1360  * unity mapped regions.
1361  *
1362  ****************************************************************************/
1363 
1364 static void free_page_list(struct page *freelist)
1365 {
1366         while (freelist != NULL) {
1367                 unsigned long p = (unsigned long)page_address(freelist);
1368                 freelist = freelist->freelist;
1369                 free_page(p);
1370         }
1371 }
1372 
1373 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1374 {
1375         struct page *p = virt_to_page((void *)pt);
1376 
1377         p->freelist = freelist;
1378 
1379         return p;
1380 }
1381 
1382 #define DEFINE_FREE_PT_FN(LVL, FN)                                              \
1383 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist)   \
1384 {                                                                               \
1385         unsigned long p;                                                        \
1386         u64 *pt;                                                                \
1387         int i;                                                                  \
1388                                                                                 \
1389         pt = (u64 *)__pt;                                                       \
1390                                                                                 \
1391         for (i = 0; i < 512; ++i) {                                             \
1392                 /* PTE present? */                                              \
1393                 if (!IOMMU_PTE_PRESENT(pt[i]))                                  \
1394                         continue;                                               \
1395                                                                                 \
1396                 /* Large PTE? */                                                \
1397                 if (PM_PTE_LEVEL(pt[i]) == 0 ||                                 \
1398                     PM_PTE_LEVEL(pt[i]) == 7)                                   \
1399                         continue;                                               \
1400                                                                                 \
1401                 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]);                       \
1402                 freelist = FN(p, freelist);                                     \
1403         }                                                                       \
1404                                                                                 \
1405         return free_pt_page((unsigned long)pt, freelist);                       \
1406 }
1407 
1408 DEFINE_FREE_PT_FN(l2, free_pt_page)
1409 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1410 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1411 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1412 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1413 
1414 static struct page *free_sub_pt(unsigned long root, int mode,
1415                                 struct page *freelist)
1416 {
1417         switch (mode) {
1418         case PAGE_MODE_NONE:
1419         case PAGE_MODE_7_LEVEL:
1420                 break;
1421         case PAGE_MODE_1_LEVEL:
1422                 freelist = free_pt_page(root, freelist);
1423                 break;
1424         case PAGE_MODE_2_LEVEL:
1425                 freelist = free_pt_l2(root, freelist);
1426                 break;
1427         case PAGE_MODE_3_LEVEL:
1428                 freelist = free_pt_l3(root, freelist);
1429                 break;
1430         case PAGE_MODE_4_LEVEL:
1431                 freelist = free_pt_l4(root, freelist);
1432                 break;
1433         case PAGE_MODE_5_LEVEL:
1434                 freelist = free_pt_l5(root, freelist);
1435                 break;
1436         case PAGE_MODE_6_LEVEL:
1437                 freelist = free_pt_l6(root, freelist);
1438                 break;
1439         default:
1440                 BUG();
1441         }
1442 
1443         return freelist;
1444 }
1445 
1446 static void free_pagetable(struct protection_domain *domain)
1447 {
1448         unsigned long root = (unsigned long)domain->pt_root;
1449         struct page *freelist = NULL;
1450 
1451         BUG_ON(domain->mode < PAGE_MODE_NONE ||
1452                domain->mode > PAGE_MODE_6_LEVEL);
1453 
1454         freelist = free_sub_pt(root, domain->mode, freelist);
1455 
1456         free_page_list(freelist);
1457 }
1458 
1459 /*
1460  * This function is used to add another level to an IO page table. Adding
1461  * another level increases the size of the address space by 9 bits to a size up
1462  * to 64 bits.
1463  */
1464 static bool increase_address_space(struct protection_domain *domain,
1465                                    unsigned long address,
1466                                    gfp_t gfp)
1467 {
1468         unsigned long flags;
1469         bool ret = false;
1470         u64 *pte;
1471 
1472         spin_lock_irqsave(&domain->lock, flags);
1473 
1474         if (address <= PM_LEVEL_SIZE(domain->mode) ||
1475             WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1476                 goto out;
1477 
1478         pte = (void *)get_zeroed_page(gfp);
1479         if (!pte)
1480                 goto out;
1481 
1482         *pte             = PM_LEVEL_PDE(domain->mode,
1483                                         iommu_virt_to_phys(domain->pt_root));
1484         domain->pt_root  = pte;
1485         domain->mode    += 1;
1486 
1487         ret = true;
1488 
1489 out:
1490         spin_unlock_irqrestore(&domain->lock, flags);
1491 
1492         return ret;
1493 }
1494 
1495 static u64 *alloc_pte(struct protection_domain *domain,
1496                       unsigned long address,
1497                       unsigned long page_size,
1498                       u64 **pte_page,
1499                       gfp_t gfp,
1500                       bool *updated)
1501 {
1502         int level, end_lvl;
1503         u64 *pte, *page;
1504 
1505         BUG_ON(!is_power_of_2(page_size));
1506 
1507         while (address > PM_LEVEL_SIZE(domain->mode))
1508                 *updated = increase_address_space(domain, address, gfp) || *updated;
1509 
1510         level   = domain->mode - 1;
1511         pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1512         address = PAGE_SIZE_ALIGN(address, page_size);
1513         end_lvl = PAGE_SIZE_LEVEL(page_size);
1514 
1515         while (level > end_lvl) {
1516                 u64 __pte, __npte;
1517                 int pte_level;
1518 
1519                 __pte     = *pte;
1520                 pte_level = PM_PTE_LEVEL(__pte);
1521 
1522                 /*
1523                  * If we replace a series of large PTEs, we need
1524                  * to tear down all of them.
1525                  */
1526                 if (IOMMU_PTE_PRESENT(__pte) &&
1527                     pte_level == PAGE_MODE_7_LEVEL) {
1528                         unsigned long count, i;
1529                         u64 *lpte;
1530 
1531                         lpte = first_pte_l7(pte, NULL, &count);
1532 
1533                         /*
1534                          * Unmap the replicated PTEs that still match the
1535                          * original large mapping
1536                          */
1537                         for (i = 0; i < count; ++i)
1538                                 cmpxchg64(&lpte[i], __pte, 0ULL);
1539 
1540                         *updated = true;
1541                         continue;
1542                 }
1543 
1544                 if (!IOMMU_PTE_PRESENT(__pte) ||
1545                     pte_level == PAGE_MODE_NONE) {
1546                         page = (u64 *)get_zeroed_page(gfp);
1547 
1548                         if (!page)
1549                                 return NULL;
1550 
1551                         __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1552 
1553                         /* pte could have been changed somewhere. */
1554                         if (cmpxchg64(pte, __pte, __npte) != __pte)
1555                                 free_page((unsigned long)page);
1556                         else if (IOMMU_PTE_PRESENT(__pte))
1557                                 *updated = true;
1558 
1559                         continue;
1560                 }
1561 
1562                 /* No level skipping support yet */
1563                 if (pte_level != level)
1564                         return NULL;
1565 
1566                 level -= 1;
1567 
1568                 pte = IOMMU_PTE_PAGE(__pte);
1569 
1570                 if (pte_page && level == end_lvl)
1571                         *pte_page = pte;
1572 
1573                 pte = &pte[PM_LEVEL_INDEX(level, address)];
1574         }
1575 
1576         return pte;
1577 }
1578 
1579 /*
1580  * This function checks if there is a PTE for a given dma address. If
1581  * there is one, it returns the pointer to it.
1582  */
1583 static u64 *fetch_pte(struct protection_domain *domain,
1584                       unsigned long address,
1585                       unsigned long *page_size)
1586 {
1587         int level;
1588         u64 *pte;
1589 
1590         *page_size = 0;
1591 
1592         if (address > PM_LEVEL_SIZE(domain->mode))
1593                 return NULL;
1594 
1595         level      =  domain->mode - 1;
1596         pte        = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1597         *page_size =  PTE_LEVEL_PAGE_SIZE(level);
1598 
1599         while (level > 0) {
1600 
1601                 /* Not Present */
1602                 if (!IOMMU_PTE_PRESENT(*pte))
1603                         return NULL;
1604 
1605                 /* Large PTE */
1606                 if (PM_PTE_LEVEL(*pte) == 7 ||
1607                     PM_PTE_LEVEL(*pte) == 0)
1608                         break;
1609 
1610                 /* No level skipping support yet */
1611                 if (PM_PTE_LEVEL(*pte) != level)
1612                         return NULL;
1613 
1614                 level -= 1;
1615 
1616                 /* Walk to the next level */
1617                 pte        = IOMMU_PTE_PAGE(*pte);
1618                 pte        = &pte[PM_LEVEL_INDEX(level, address)];
1619                 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1620         }
1621 
1622         /*
1623          * If we have a series of large PTEs, make
1624          * sure to return a pointer to the first one.
1625          */
1626         if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1627                 pte = first_pte_l7(pte, page_size, NULL);
1628 
1629         return pte;
1630 }
1631 
1632 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1633 {
1634         unsigned long pt;
1635         int mode;
1636 
1637         while (cmpxchg64(pte, pteval, 0) != pteval) {
1638                 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1639                 pteval = *pte;
1640         }
1641 
1642         if (!IOMMU_PTE_PRESENT(pteval))
1643                 return freelist;
1644 
1645         pt   = (unsigned long)IOMMU_PTE_PAGE(pteval);
1646         mode = IOMMU_PTE_MODE(pteval);
1647 
1648         return free_sub_pt(pt, mode, freelist);
1649 }
1650 
1651 /*
1652  * Generic mapping functions. It maps a physical address into a DMA
1653  * address space. It allocates the page table pages if necessary.
1654  * In the future it can be extended to a generic mapping function
1655  * supporting all features of AMD IOMMU page tables like level skipping
1656  * and full 64 bit address spaces.
1657  */
1658 static int iommu_map_page(struct protection_domain *dom,
1659                           unsigned long bus_addr,
1660                           unsigned long phys_addr,
1661                           unsigned long page_size,
1662                           int prot,
1663                           gfp_t gfp)
1664 {
1665         struct page *freelist = NULL;
1666         bool updated = false;
1667         u64 __pte, *pte;
1668         int ret, i, count;
1669 
1670         BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1671         BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1672 
1673         ret = -EINVAL;
1674         if (!(prot & IOMMU_PROT_MASK))
1675                 goto out;
1676 
1677         count = PAGE_SIZE_PTE_COUNT(page_size);
1678         pte   = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1679 
1680         ret = -ENOMEM;
1681         if (!pte)
1682                 goto out;
1683 
1684         for (i = 0; i < count; ++i)
1685                 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1686 
1687         if (freelist != NULL)
1688                 updated = true;
1689 
1690         if (count > 1) {
1691                 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1692                 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1693         } else
1694                 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1695 
1696         if (prot & IOMMU_PROT_IR)
1697                 __pte |= IOMMU_PTE_IR;
1698         if (prot & IOMMU_PROT_IW)
1699                 __pte |= IOMMU_PTE_IW;
1700 
1701         for (i = 0; i < count; ++i)
1702                 pte[i] = __pte;
1703 
1704         ret = 0;
1705 
1706 out:
1707         if (updated) {
1708                 unsigned long flags;
1709 
1710                 spin_lock_irqsave(&dom->lock, flags);
1711                 update_domain(dom);
1712                 spin_unlock_irqrestore(&dom->lock, flags);
1713         }
1714 
1715         /* Everything flushed out, free pages now */
1716         free_page_list(freelist);
1717 
1718         return ret;
1719 }
1720 
1721 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1722                                       unsigned long bus_addr,
1723                                       unsigned long page_size)
1724 {
1725         unsigned long long unmapped;
1726         unsigned long unmap_size;
1727         u64 *pte;
1728 
1729         BUG_ON(!is_power_of_2(page_size));
1730 
1731         unmapped = 0;
1732 
1733         while (unmapped < page_size) {
1734 
1735                 pte = fetch_pte(dom, bus_addr, &unmap_size);
1736 
1737                 if (pte) {
1738                         int i, count;
1739 
1740                         count = PAGE_SIZE_PTE_COUNT(unmap_size);
1741                         for (i = 0; i < count; i++)
1742                                 pte[i] = 0ULL;
1743                 }
1744 
1745                 bus_addr  = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1746                 unmapped += unmap_size;
1747         }
1748 
1749         BUG_ON(unmapped && !is_power_of_2(unmapped));
1750 
1751         return unmapped;
1752 }
1753 
1754 /****************************************************************************
1755  *
1756  * The next functions belong to the address allocator for the dma_ops
1757  * interface functions.
1758  *
1759  ****************************************************************************/
1760 
1761 
1762 static unsigned long dma_ops_alloc_iova(struct device *dev,
1763                                         struct dma_ops_domain *dma_dom,
1764                                         unsigned int pages, u64 dma_mask)
1765 {
1766         unsigned long pfn = 0;
1767 
1768         pages = __roundup_pow_of_two(pages);
1769 
1770         if (dma_mask > DMA_BIT_MASK(32))
1771                 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1772                                       IOVA_PFN(DMA_BIT_MASK(32)), false);
1773 
1774         if (!pfn)
1775                 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1776                                       IOVA_PFN(dma_mask), true);
1777 
1778         return (pfn << PAGE_SHIFT);
1779 }
1780 
1781 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1782                               unsigned long address,
1783                               unsigned int pages)
1784 {
1785         pages = __roundup_pow_of_two(pages);
1786         address >>= PAGE_SHIFT;
1787 
1788         free_iova_fast(&dma_dom->iovad, address, pages);
1789 }
1790 
1791 /****************************************************************************
1792  *
1793  * The next functions belong to the domain allocation. A domain is
1794  * allocated for every IOMMU as the default domain. If device isolation
1795  * is enabled, every device get its own domain. The most important thing
1796  * about domains is the page table mapping the DMA address space they
1797  * contain.
1798  *
1799  ****************************************************************************/
1800 
1801 static u16 domain_id_alloc(void)
1802 {
1803         int id;
1804 
1805         spin_lock(&pd_bitmap_lock);
1806         id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1807         BUG_ON(id == 0);
1808         if (id > 0 && id < MAX_DOMAIN_ID)
1809                 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1810         else
1811                 id = 0;
1812         spin_unlock(&pd_bitmap_lock);
1813 
1814         return id;
1815 }
1816 
1817 static void domain_id_free(int id)
1818 {
1819         spin_lock(&pd_bitmap_lock);
1820         if (id > 0 && id < MAX_DOMAIN_ID)
1821                 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1822         spin_unlock(&pd_bitmap_lock);
1823 }
1824 
1825 static void free_gcr3_tbl_level1(u64 *tbl)
1826 {
1827         u64 *ptr;
1828         int i;
1829 
1830         for (i = 0; i < 512; ++i) {
1831                 if (!(tbl[i] & GCR3_VALID))
1832                         continue;
1833 
1834                 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1835 
1836                 free_page((unsigned long)ptr);
1837         }
1838 }
1839 
1840 static void free_gcr3_tbl_level2(u64 *tbl)
1841 {
1842         u64 *ptr;
1843         int i;
1844 
1845         for (i = 0; i < 512; ++i) {
1846                 if (!(tbl[i] & GCR3_VALID))
1847                         continue;
1848 
1849                 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1850 
1851                 free_gcr3_tbl_level1(ptr);
1852         }
1853 }
1854 
1855 static void free_gcr3_table(struct protection_domain *domain)
1856 {
1857         if (domain->glx == 2)
1858                 free_gcr3_tbl_level2(domain->gcr3_tbl);
1859         else if (domain->glx == 1)
1860                 free_gcr3_tbl_level1(domain->gcr3_tbl);
1861         else
1862                 BUG_ON(domain->glx != 0);
1863 
1864         free_page((unsigned long)domain->gcr3_tbl);
1865 }
1866 
1867 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1868 {
1869         unsigned long flags;
1870 
1871         spin_lock_irqsave(&dom->domain.lock, flags);
1872         domain_flush_tlb(&dom->domain);
1873         domain_flush_complete(&dom->domain);
1874         spin_unlock_irqrestore(&dom->domain.lock, flags);
1875 }
1876 
1877 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1878 {
1879         struct dma_ops_domain *dom;
1880 
1881         dom = container_of(iovad, struct dma_ops_domain, iovad);
1882 
1883         dma_ops_domain_flush_tlb(dom);
1884 }
1885 
1886 /*
1887  * Free a domain, only used if something went wrong in the
1888  * allocation path and we need to free an already allocated page table
1889  */
1890 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1891 {
1892         if (!dom)
1893                 return;
1894 
1895         put_iova_domain(&dom->iovad);
1896 
1897         free_pagetable(&dom->domain);
1898 
1899         if (dom->domain.id)
1900                 domain_id_free(dom->domain.id);
1901 
1902         kfree(dom);
1903 }
1904 
1905 /*
1906  * Allocates a new protection domain usable for the dma_ops functions.
1907  * It also initializes the page table and the address allocator data
1908  * structures required for the dma_ops interface
1909  */
1910 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1911 {
1912         struct dma_ops_domain *dma_dom;
1913 
1914         dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1915         if (!dma_dom)
1916                 return NULL;
1917 
1918         if (protection_domain_init(&dma_dom->domain))
1919                 goto free_dma_dom;
1920 
1921         dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1922         dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1923         dma_dom->domain.flags = PD_DMA_OPS_MASK;
1924         if (!dma_dom->domain.pt_root)
1925                 goto free_dma_dom;
1926 
1927         init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1928 
1929         if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1930                 goto free_dma_dom;
1931 
1932         /* Initialize reserved ranges */
1933         copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1934 
1935         return dma_dom;
1936 
1937 free_dma_dom:
1938         dma_ops_domain_free(dma_dom);
1939 
1940         return NULL;
1941 }
1942 
1943 /*
1944  * little helper function to check whether a given protection domain is a
1945  * dma_ops domain
1946  */
1947 static bool dma_ops_domain(struct protection_domain *domain)
1948 {
1949         return domain->flags & PD_DMA_OPS_MASK;
1950 }
1951 
1952 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1953                           bool ats, bool ppr)
1954 {
1955         u64 pte_root = 0;
1956         u64 flags = 0;
1957         u32 old_domid;
1958 
1959         if (domain->mode != PAGE_MODE_NONE)
1960                 pte_root = iommu_virt_to_phys(domain->pt_root);
1961 
1962         pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1963                     << DEV_ENTRY_MODE_SHIFT;
1964         pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1965 
1966         flags = amd_iommu_dev_table[devid].data[1];
1967 
1968         if (ats)
1969                 flags |= DTE_FLAG_IOTLB;
1970 
1971         if (ppr) {
1972                 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1973 
1974                 if (iommu_feature(iommu, FEATURE_EPHSUP))
1975                         pte_root |= 1ULL << DEV_ENTRY_PPR;
1976         }
1977 
1978         if (domain->flags & PD_IOMMUV2_MASK) {
1979                 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1980                 u64 glx  = domain->glx;
1981                 u64 tmp;
1982 
1983                 pte_root |= DTE_FLAG_GV;
1984                 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1985 
1986                 /* First mask out possible old values for GCR3 table */
1987                 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1988                 flags    &= ~tmp;
1989 
1990                 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1991                 flags    &= ~tmp;
1992 
1993                 /* Encode GCR3 table into DTE */
1994                 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1995                 pte_root |= tmp;
1996 
1997                 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1998                 flags    |= tmp;
1999 
2000                 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2001                 flags    |= tmp;
2002         }
2003 
2004         flags &= ~DEV_DOMID_MASK;
2005         flags |= domain->id;
2006 
2007         old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
2008         amd_iommu_dev_table[devid].data[1]  = flags;
2009         amd_iommu_dev_table[devid].data[0]  = pte_root;
2010 
2011         /*
2012          * A kdump kernel might be replacing a domain ID that was copied from
2013          * the previous kernel--if so, it needs to flush the translation cache
2014          * entries for the old domain ID that is being overwritten
2015          */
2016         if (old_domid) {
2017                 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2018 
2019                 amd_iommu_flush_tlb_domid(iommu, old_domid);
2020         }
2021 }
2022 
2023 static void clear_dte_entry(u16 devid)
2024 {
2025         /* remove entry from the device table seen by the hardware */
2026         amd_iommu_dev_table[devid].data[0]  = DTE_FLAG_V | DTE_FLAG_TV;
2027         amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2028 
2029         amd_iommu_apply_erratum_63(devid);
2030 }
2031 
2032 static void do_attach(struct iommu_dev_data *dev_data,
2033                       struct protection_domain *domain)
2034 {
2035         struct amd_iommu *iommu;
2036         bool ats;
2037 
2038         iommu = amd_iommu_rlookup_table[dev_data->devid];
2039         ats   = dev_data->ats.enabled;
2040 
2041         /* Update data structures */
2042         dev_data->domain = domain;
2043         list_add(&dev_data->list, &domain->dev_list);
2044 
2045         /* Do reference counting */
2046         domain->dev_iommu[iommu->index] += 1;
2047         domain->dev_cnt                 += 1;
2048 
2049         /* Update device table */
2050         set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
2051         clone_aliases(dev_data->pdev);
2052 
2053         device_flush_dte(dev_data);
2054 }
2055 
2056 static void do_detach(struct iommu_dev_data *dev_data)
2057 {
2058         struct protection_domain *domain = dev_data->domain;
2059         struct amd_iommu *iommu;
2060 
2061         iommu = amd_iommu_rlookup_table[dev_data->devid];
2062 
2063         /* Update data structures */
2064         dev_data->domain = NULL;
2065         list_del(&dev_data->list);
2066         clear_dte_entry(dev_data->devid);
2067         clone_aliases(dev_data->pdev);
2068 
2069         /* Flush the DTE entry */
2070         device_flush_dte(dev_data);
2071 
2072         /* Flush IOTLB */
2073         domain_flush_tlb_pde(domain);
2074 
2075         /* Wait for the flushes to finish */
2076         domain_flush_complete(domain);
2077 
2078         /* decrease reference counters - needs to happen after the flushes */
2079         domain->dev_iommu[iommu->index] -= 1;
2080         domain->dev_cnt                 -= 1;
2081 }
2082 
2083 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2084 {
2085         pci_disable_ats(pdev);
2086         pci_disable_pri(pdev);
2087         pci_disable_pasid(pdev);
2088 }
2089 
2090 /* FIXME: Change generic reset-function to do the same */
2091 static int pri_reset_while_enabled(struct pci_dev *pdev)
2092 {
2093         u16 control;
2094         int pos;
2095 
2096         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2097         if (!pos)
2098                 return -EINVAL;
2099 
2100         pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2101         control |= PCI_PRI_CTRL_RESET;
2102         pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2103 
2104         return 0;
2105 }
2106 
2107 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2108 {
2109         bool reset_enable;
2110         int reqs, ret;
2111 
2112         /* FIXME: Hardcode number of outstanding requests for now */
2113         reqs = 32;
2114         if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2115                 reqs = 1;
2116         reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2117 
2118         /* Only allow access to user-accessible pages */
2119         ret = pci_enable_pasid(pdev, 0);
2120         if (ret)
2121                 goto out_err;
2122 
2123         /* First reset the PRI state of the device */
2124         ret = pci_reset_pri(pdev);
2125         if (ret)
2126                 goto out_err;
2127 
2128         /* Enable PRI */
2129         ret = pci_enable_pri(pdev, reqs);
2130         if (ret)
2131                 goto out_err;
2132 
2133         if (reset_enable) {
2134                 ret = pri_reset_while_enabled(pdev);
2135                 if (ret)
2136                         goto out_err;
2137         }
2138 
2139         ret = pci_enable_ats(pdev, PAGE_SHIFT);
2140         if (ret)
2141                 goto out_err;
2142 
2143         return 0;
2144 
2145 out_err:
2146         pci_disable_pri(pdev);
2147         pci_disable_pasid(pdev);
2148 
2149         return ret;
2150 }
2151 
2152 /*
2153  * If a device is not yet associated with a domain, this function makes the
2154  * device visible in the domain
2155  */
2156 static int attach_device(struct device *dev,
2157                          struct protection_domain *domain)
2158 {
2159         struct pci_dev *pdev;
2160         struct iommu_dev_data *dev_data;
2161         unsigned long flags;
2162         int ret;
2163 
2164         spin_lock_irqsave(&domain->lock, flags);
2165 
2166         dev_data = get_dev_data(dev);
2167 
2168         spin_lock(&dev_data->lock);
2169 
2170         ret = -EBUSY;
2171         if (dev_data->domain != NULL)
2172                 goto out;
2173 
2174         if (!dev_is_pci(dev))
2175                 goto skip_ats_check;
2176 
2177         pdev = to_pci_dev(dev);
2178         if (domain->flags & PD_IOMMUV2_MASK) {
2179                 ret = -EINVAL;
2180                 if (!dev_data->passthrough)
2181                         goto out;
2182 
2183                 if (dev_data->iommu_v2) {
2184                         if (pdev_iommuv2_enable(pdev) != 0)
2185                                 goto out;
2186 
2187                         dev_data->ats.enabled = true;
2188                         dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
2189                         dev_data->pri_tlp     = pci_prg_resp_pasid_required(pdev);
2190                 }
2191         } else if (amd_iommu_iotlb_sup &&
2192                    pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2193                 dev_data->ats.enabled = true;
2194                 dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
2195         }
2196 
2197 skip_ats_check:
2198         ret = 0;
2199 
2200         do_attach(dev_data, domain);
2201 
2202         /*
2203          * We might boot into a crash-kernel here. The crashed kernel
2204          * left the caches in the IOMMU dirty. So we have to flush
2205          * here to evict all dirty stuff.
2206          */
2207         domain_flush_tlb_pde(domain);
2208 
2209         domain_flush_complete(domain);
2210 
2211 out:
2212         spin_unlock(&dev_data->lock);
2213 
2214         spin_unlock_irqrestore(&domain->lock, flags);
2215 
2216         return ret;
2217 }
2218 
2219 /*
2220  * Removes a device from a protection domain (with devtable_lock held)
2221  */
2222 static void detach_device(struct device *dev)
2223 {
2224         struct protection_domain *domain;
2225         struct iommu_dev_data *dev_data;
2226         unsigned long flags;
2227 
2228         dev_data = get_dev_data(dev);
2229         domain   = dev_data->domain;
2230 
2231         spin_lock_irqsave(&domain->lock, flags);
2232 
2233         spin_lock(&dev_data->lock);
2234 
2235         /*
2236          * First check if the device is still attached. It might already
2237          * be detached from its domain because the generic
2238          * iommu_detach_group code detached it and we try again here in
2239          * our alias handling.
2240          */
2241         if (WARN_ON(!dev_data->domain))
2242                 goto out;
2243 
2244         do_detach(dev_data);
2245 
2246         if (!dev_is_pci(dev))
2247                 goto out;
2248 
2249         if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2250                 pdev_iommuv2_disable(to_pci_dev(dev));
2251         else if (dev_data->ats.enabled)
2252                 pci_disable_ats(to_pci_dev(dev));
2253 
2254         dev_data->ats.enabled = false;
2255 
2256 out:
2257         spin_unlock(&dev_data->lock);
2258 
2259         spin_unlock_irqrestore(&domain->lock, flags);
2260 }
2261 
2262 static int amd_iommu_add_device(struct device *dev)
2263 {
2264         struct iommu_dev_data *dev_data;
2265         struct iommu_domain *domain;
2266         struct amd_iommu *iommu;
2267         int ret, devid;
2268 
2269         if (!check_device(dev) || get_dev_data(dev))
2270                 return 0;
2271 
2272         devid = get_device_id(dev);
2273         if (devid < 0)
2274                 return devid;
2275 
2276         iommu = amd_iommu_rlookup_table[devid];
2277 
2278         ret = iommu_init_device(dev);
2279         if (ret) {
2280                 if (ret != -ENOTSUPP)
2281                         dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2282 
2283                 iommu_ignore_device(dev);
2284                 dev->dma_ops = NULL;
2285                 goto out;
2286         }
2287         init_iommu_group(dev);
2288 
2289         dev_data = get_dev_data(dev);
2290 
2291         BUG_ON(!dev_data);
2292 
2293         if (dev_data->iommu_v2)
2294                 iommu_request_dm_for_dev(dev);
2295 
2296         /* Domains are initialized for this device - have a look what we ended up with */
2297         domain = iommu_get_domain_for_dev(dev);
2298         if (domain->type == IOMMU_DOMAIN_IDENTITY)
2299                 dev_data->passthrough = true;
2300         else
2301                 dev->dma_ops = &amd_iommu_dma_ops;
2302 
2303 out:
2304         iommu_completion_wait(iommu);
2305 
2306         return 0;
2307 }
2308 
2309 static void amd_iommu_remove_device(struct device *dev)
2310 {
2311         struct amd_iommu *iommu;
2312         int devid;
2313 
2314         if (!check_device(dev))
2315                 return;
2316 
2317         devid = get_device_id(dev);
2318         if (devid < 0)
2319                 return;
2320 
2321         iommu = amd_iommu_rlookup_table[devid];
2322 
2323         iommu_uninit_device(dev);
2324         iommu_completion_wait(iommu);
2325 }
2326 
2327 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2328 {
2329         if (dev_is_pci(dev))
2330                 return pci_device_group(dev);
2331 
2332         return acpihid_device_group(dev);
2333 }
2334 
2335 /*****************************************************************************
2336  *
2337  * The next functions belong to the dma_ops mapping/unmapping code.
2338  *
2339  *****************************************************************************/
2340 
2341 /*
2342  * In the dma_ops path we only have the struct device. This function
2343  * finds the corresponding IOMMU, the protection domain and the
2344  * requestor id for a given device.
2345  * If the device is not yet associated with a domain this is also done
2346  * in this function.
2347  */
2348 static struct protection_domain *get_domain(struct device *dev)
2349 {
2350         struct protection_domain *domain;
2351         struct iommu_domain *io_domain;
2352 
2353         if (!check_device(dev))
2354                 return ERR_PTR(-EINVAL);
2355 
2356         domain = get_dev_data(dev)->domain;
2357         if (domain == NULL && get_dev_data(dev)->defer_attach) {
2358                 get_dev_data(dev)->defer_attach = false;
2359                 io_domain = iommu_get_domain_for_dev(dev);
2360                 domain = to_pdomain(io_domain);
2361                 attach_device(dev, domain);
2362         }
2363         if (domain == NULL)
2364                 return ERR_PTR(-EBUSY);
2365 
2366         if (!dma_ops_domain(domain))
2367                 return ERR_PTR(-EBUSY);
2368 
2369         return domain;
2370 }
2371 
2372 static void update_device_table(struct protection_domain *domain)
2373 {
2374         struct iommu_dev_data *dev_data;
2375 
2376         list_for_each_entry(dev_data, &domain->dev_list, list) {
2377                 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2378                               dev_data->iommu_v2);
2379                 clone_aliases(dev_data->pdev);
2380         }
2381 }
2382 
2383 static void update_domain(struct protection_domain *domain)
2384 {
2385         update_device_table(domain);
2386 
2387         domain_flush_devices(domain);
2388         domain_flush_tlb_pde(domain);
2389         domain_flush_complete(domain);
2390 }
2391 
2392 static int dir2prot(enum dma_data_direction direction)
2393 {
2394         if (direction == DMA_TO_DEVICE)
2395                 return IOMMU_PROT_IR;
2396         else if (direction == DMA_FROM_DEVICE)
2397                 return IOMMU_PROT_IW;
2398         else if (direction == DMA_BIDIRECTIONAL)
2399                 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2400         else
2401                 return 0;
2402 }
2403 
2404 /*
2405  * This function contains common code for mapping of a physically
2406  * contiguous memory region into DMA address space. It is used by all
2407  * mapping functions provided with this IOMMU driver.
2408  * Must be called with the domain lock held.
2409  */
2410 static dma_addr_t __map_single(struct device *dev,
2411                                struct dma_ops_domain *dma_dom,
2412                                phys_addr_t paddr,
2413                                size_t size,
2414                                enum dma_data_direction direction,
2415                                u64 dma_mask)
2416 {
2417         dma_addr_t offset = paddr & ~PAGE_MASK;
2418         dma_addr_t address, start, ret;
2419         unsigned long flags;
2420         unsigned int pages;
2421         int prot = 0;
2422         int i;
2423 
2424         pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2425         paddr &= PAGE_MASK;
2426 
2427         address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2428         if (!address)
2429                 goto out;
2430 
2431         prot = dir2prot(direction);
2432 
2433         start = address;
2434         for (i = 0; i < pages; ++i) {
2435                 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2436                                      PAGE_SIZE, prot, GFP_ATOMIC);
2437                 if (ret)
2438                         goto out_unmap;
2439 
2440                 paddr += PAGE_SIZE;
2441                 start += PAGE_SIZE;
2442         }
2443         address += offset;
2444 
2445         domain_flush_np_cache(&dma_dom->domain, address, size);
2446 
2447 out:
2448         return address;
2449 
2450 out_unmap:
2451 
2452         for (--i; i >= 0; --i) {
2453                 start -= PAGE_SIZE;
2454                 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2455         }
2456 
2457         spin_lock_irqsave(&dma_dom->domain.lock, flags);
2458         domain_flush_tlb(&dma_dom->domain);
2459         domain_flush_complete(&dma_dom->domain);
2460         spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2461 
2462         dma_ops_free_iova(dma_dom, address, pages);
2463 
2464         return DMA_MAPPING_ERROR;
2465 }
2466 
2467 /*
2468  * Does the reverse of the __map_single function. Must be called with
2469  * the domain lock held too
2470  */
2471 static void __unmap_single(struct dma_ops_domain *dma_dom,
2472                            dma_addr_t dma_addr,
2473                            size_t size,
2474                            int dir)
2475 {
2476         dma_addr_t i, start;
2477         unsigned int pages;
2478 
2479         pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2480         dma_addr &= PAGE_MASK;
2481         start = dma_addr;
2482 
2483         for (i = 0; i < pages; ++i) {
2484                 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2485                 start += PAGE_SIZE;
2486         }
2487 
2488         if (amd_iommu_unmap_flush) {
2489                 unsigned long flags;
2490 
2491                 spin_lock_irqsave(&dma_dom->domain.lock, flags);
2492                 domain_flush_tlb(&dma_dom->domain);
2493                 domain_flush_complete(&dma_dom->domain);
2494                 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2495                 dma_ops_free_iova(dma_dom, dma_addr, pages);
2496         } else {
2497                 pages = __roundup_pow_of_two(pages);
2498                 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2499         }
2500 }
2501 
2502 /*
2503  * The exported map_single function for dma_ops.
2504  */
2505 static dma_addr_t map_page(struct device *dev, struct page *page,
2506                            unsigned long offset, size_t size,
2507                            enum dma_data_direction dir,
2508                            unsigned long attrs)
2509 {
2510         phys_addr_t paddr = page_to_phys(page) + offset;
2511         struct protection_domain *domain;
2512         struct dma_ops_domain *dma_dom;
2513         u64 dma_mask;
2514 
2515         domain = get_domain(dev);
2516         if (PTR_ERR(domain) == -EINVAL)
2517                 return (dma_addr_t)paddr;
2518         else if (IS_ERR(domain))
2519                 return DMA_MAPPING_ERROR;
2520 
2521         dma_mask = *dev->dma_mask;
2522         dma_dom = to_dma_ops_domain(domain);
2523 
2524         return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2525 }
2526 
2527 /*
2528  * The exported unmap_single function for dma_ops.
2529  */
2530 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2531                        enum dma_data_direction dir, unsigned long attrs)
2532 {
2533         struct protection_domain *domain;
2534         struct dma_ops_domain *dma_dom;
2535 
2536         domain = get_domain(dev);
2537         if (IS_ERR(domain))
2538                 return;
2539 
2540         dma_dom = to_dma_ops_domain(domain);
2541 
2542         __unmap_single(dma_dom, dma_addr, size, dir);
2543 }
2544 
2545 static int sg_num_pages(struct device *dev,
2546                         struct scatterlist *sglist,
2547                         int nelems)
2548 {
2549         unsigned long mask, boundary_size;
2550         struct scatterlist *s;
2551         int i, npages = 0;
2552 
2553         mask          = dma_get_seg_boundary(dev);
2554         boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2555                                    1UL << (BITS_PER_LONG - PAGE_SHIFT);
2556 
2557         for_each_sg(sglist, s, nelems, i) {
2558                 int p, n;
2559 
2560                 s->dma_address = npages << PAGE_SHIFT;
2561                 p = npages % boundary_size;
2562                 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2563                 if (p + n > boundary_size)
2564                         npages += boundary_size - p;
2565                 npages += n;
2566         }
2567 
2568         return npages;
2569 }
2570 
2571 /*
2572  * The exported map_sg function for dma_ops (handles scatter-gather
2573  * lists).
2574  */
2575 static int map_sg(struct device *dev, struct scatterlist *sglist,
2576                   int nelems, enum dma_data_direction direction,
2577                   unsigned long attrs)
2578 {
2579         int mapped_pages = 0, npages = 0, prot = 0, i;
2580         struct protection_domain *domain;
2581         struct dma_ops_domain *dma_dom;
2582         struct scatterlist *s;
2583         unsigned long address;
2584         u64 dma_mask;
2585         int ret;
2586 
2587         domain = get_domain(dev);
2588         if (IS_ERR(domain))
2589                 return 0;
2590 
2591         dma_dom  = to_dma_ops_domain(domain);
2592         dma_mask = *dev->dma_mask;
2593 
2594         npages = sg_num_pages(dev, sglist, nelems);
2595 
2596         address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2597         if (!address)
2598                 goto out_err;
2599 
2600         prot = dir2prot(direction);
2601 
2602         /* Map all sg entries */
2603         for_each_sg(sglist, s, nelems, i) {
2604                 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2605 
2606                 for (j = 0; j < pages; ++j) {
2607                         unsigned long bus_addr, phys_addr;
2608 
2609                         bus_addr  = address + s->dma_address + (j << PAGE_SHIFT);
2610                         phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2611                         ret = iommu_map_page(domain, bus_addr, phys_addr,
2612                                              PAGE_SIZE, prot,
2613                                              GFP_ATOMIC | __GFP_NOWARN);
2614                         if (ret)
2615                                 goto out_unmap;
2616 
2617                         mapped_pages += 1;
2618                 }
2619         }
2620 
2621         /* Everything is mapped - write the right values into s->dma_address */
2622         for_each_sg(sglist, s, nelems, i) {
2623                 /*
2624                  * Add in the remaining piece of the scatter-gather offset that
2625                  * was masked out when we were determining the physical address
2626                  * via (sg_phys(s) & PAGE_MASK) earlier.
2627                  */
2628                 s->dma_address += address + (s->offset & ~PAGE_MASK);
2629                 s->dma_length   = s->length;
2630         }
2631 
2632         if (s)
2633                 domain_flush_np_cache(domain, s->dma_address, s->dma_length);
2634 
2635         return nelems;
2636 
2637 out_unmap:
2638         dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2639                 npages, ret);
2640 
2641         for_each_sg(sglist, s, nelems, i) {
2642                 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2643 
2644                 for (j = 0; j < pages; ++j) {
2645                         unsigned long bus_addr;
2646 
2647                         bus_addr  = address + s->dma_address + (j << PAGE_SHIFT);
2648                         iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2649 
2650                         if (--mapped_pages == 0)
2651                                 goto out_free_iova;
2652                 }
2653         }
2654 
2655 out_free_iova:
2656         free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2657 
2658 out_err:
2659         return 0;
2660 }
2661 
2662 /*
2663  * The exported map_sg function for dma_ops (handles scatter-gather
2664  * lists).
2665  */
2666 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2667                      int nelems, enum dma_data_direction dir,
2668                      unsigned long attrs)
2669 {
2670         struct protection_domain *domain;
2671         struct dma_ops_domain *dma_dom;
2672         unsigned long startaddr;
2673         int npages;
2674 
2675         domain = get_domain(dev);
2676         if (IS_ERR(domain))
2677                 return;
2678 
2679         startaddr = sg_dma_address(sglist) & PAGE_MASK;
2680         dma_dom   = to_dma_ops_domain(domain);
2681         npages    = sg_num_pages(dev, sglist, nelems);
2682 
2683         __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2684 }
2685 
2686 /*
2687  * The exported alloc_coherent function for dma_ops.
2688  */
2689 static void *alloc_coherent(struct device *dev, size_t size,
2690                             dma_addr_t *dma_addr, gfp_t flag,
2691                             unsigned long attrs)
2692 {
2693         u64 dma_mask = dev->coherent_dma_mask;
2694         struct protection_domain *domain;
2695         struct dma_ops_domain *dma_dom;
2696         struct page *page;
2697 
2698         domain = get_domain(dev);
2699         if (PTR_ERR(domain) == -EINVAL) {
2700                 page = alloc_pages(flag, get_order(size));
2701                 *dma_addr = page_to_phys(page);
2702                 return page_address(page);
2703         } else if (IS_ERR(domain))
2704                 return NULL;
2705 
2706         dma_dom   = to_dma_ops_domain(domain);
2707         size      = PAGE_ALIGN(size);
2708         dma_mask  = dev->coherent_dma_mask;
2709         flag     &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2710         flag     |= __GFP_ZERO;
2711 
2712         page = alloc_pages(flag | __GFP_NOWARN,  get_order(size));
2713         if (!page) {
2714                 if (!gfpflags_allow_blocking(flag))
2715                         return NULL;
2716 
2717                 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2718                                         get_order(size), flag & __GFP_NOWARN);
2719                 if (!page)
2720                         return NULL;
2721         }
2722 
2723         if (!dma_mask)
2724                 dma_mask = *dev->dma_mask;
2725 
2726         *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2727                                  size, DMA_BIDIRECTIONAL, dma_mask);
2728 
2729         if (*dma_addr == DMA_MAPPING_ERROR)
2730                 goto out_free;
2731 
2732         return page_address(page);
2733 
2734 out_free:
2735 
2736         if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2737                 __free_pages(page, get_order(size));
2738 
2739         return NULL;
2740 }
2741 
2742 /*
2743  * The exported free_coherent function for dma_ops.
2744  */
2745 static void free_coherent(struct device *dev, size_t size,
2746                           void *virt_addr, dma_addr_t dma_addr,
2747                           unsigned long attrs)
2748 {
2749         struct protection_domain *domain;
2750         struct dma_ops_domain *dma_dom;
2751         struct page *page;
2752 
2753         page = virt_to_page(virt_addr);
2754         size = PAGE_ALIGN(size);
2755 
2756         domain = get_domain(dev);
2757         if (IS_ERR(domain))
2758                 goto free_mem;
2759 
2760         dma_dom = to_dma_ops_domain(domain);
2761 
2762         __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2763 
2764 free_mem:
2765         if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2766                 __free_pages(page, get_order(size));
2767 }
2768 
2769 /*
2770  * This function is called by the DMA layer to find out if we can handle a
2771  * particular device. It is part of the dma_ops.
2772  */
2773 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2774 {
2775         if (!dma_direct_supported(dev, mask))
2776                 return 0;
2777         return check_device(dev);
2778 }
2779 
2780 static const struct dma_map_ops amd_iommu_dma_ops = {
2781         .alloc          = alloc_coherent,
2782         .free           = free_coherent,
2783         .map_page       = map_page,
2784         .unmap_page     = unmap_page,
2785         .map_sg         = map_sg,
2786         .unmap_sg       = unmap_sg,
2787         .dma_supported  = amd_iommu_dma_supported,
2788         .mmap           = dma_common_mmap,
2789         .get_sgtable    = dma_common_get_sgtable,
2790 };
2791 
2792 static int init_reserved_iova_ranges(void)
2793 {
2794         struct pci_dev *pdev = NULL;
2795         struct iova *val;
2796 
2797         init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2798 
2799         lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2800                           &reserved_rbtree_key);
2801 
2802         /* MSI memory range */
2803         val = reserve_iova(&reserved_iova_ranges,
2804                            IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2805         if (!val) {
2806                 pr_err("Reserving MSI range failed\n");
2807                 return -ENOMEM;
2808         }
2809 
2810         /* HT memory range */
2811         val = reserve_iova(&reserved_iova_ranges,
2812                            IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2813         if (!val) {
2814                 pr_err("Reserving HT range failed\n");
2815                 return -ENOMEM;
2816         }
2817 
2818         /*
2819          * Memory used for PCI resources
2820          * FIXME: Check whether we can reserve the PCI-hole completly
2821          */
2822         for_each_pci_dev(pdev) {
2823                 int i;
2824 
2825                 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2826                         struct resource *r = &pdev->resource[i];
2827 
2828                         if (!(r->flags & IORESOURCE_MEM))
2829                                 continue;
2830 
2831                         val = reserve_iova(&reserved_iova_ranges,
2832                                            IOVA_PFN(r->start),
2833                                            IOVA_PFN(r->end));
2834                         if (!val) {
2835                                 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2836                                 return -ENOMEM;
2837                         }
2838                 }
2839         }
2840 
2841         return 0;
2842 }
2843 
2844 int __init amd_iommu_init_api(void)
2845 {
2846         int ret, err = 0;
2847 
2848         ret = iova_cache_get();
2849         if (ret)
2850                 return ret;
2851 
2852         ret = init_reserved_iova_ranges();
2853         if (ret)
2854                 return ret;
2855 
2856         err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2857         if (err)
2858                 return err;
2859 #ifdef CONFIG_ARM_AMBA
2860         err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2861         if (err)
2862                 return err;
2863 #endif
2864         err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2865         if (err)
2866                 return err;
2867 
2868         return 0;
2869 }
2870 
2871 int __init amd_iommu_init_dma_ops(void)
2872 {
2873         swiotlb        = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2874         iommu_detected = 1;
2875 
2876         if (amd_iommu_unmap_flush)
2877                 pr_info("IO/TLB flush on unmap enabled\n");
2878         else
2879                 pr_info("Lazy IO/TLB flushing enabled\n");
2880 
2881         return 0;
2882 
2883 }
2884 
2885 /*****************************************************************************
2886  *
2887  * The following functions belong to the exported interface of AMD IOMMU
2888  *
2889  * This interface allows access to lower level functions of the IOMMU
2890  * like protection domain handling and assignement of devices to domains
2891  * which is not possible with the dma_ops interface.
2892  *
2893  *****************************************************************************/
2894 
2895 static void cleanup_domain(struct protection_domain *domain)
2896 {
2897         struct iommu_dev_data *entry;
2898         unsigned long flags;
2899 
2900         spin_lock_irqsave(&domain->lock, flags);
2901 
2902         while (!list_empty(&domain->dev_list)) {
2903                 entry = list_first_entry(&domain->dev_list,
2904                                          struct iommu_dev_data, list);
2905                 BUG_ON(!entry->domain);
2906                 do_detach(entry);
2907         }
2908 
2909         spin_unlock_irqrestore(&domain->lock, flags);
2910 }
2911 
2912 static void protection_domain_free(struct protection_domain *domain)
2913 {
2914         if (!domain)
2915                 return;
2916 
2917         if (domain->id)
2918                 domain_id_free(domain->id);
2919 
2920         kfree(domain);
2921 }
2922 
2923 static int protection_domain_init(struct protection_domain *domain)
2924 {
2925         spin_lock_init(&domain->lock);
2926         mutex_init(&domain->api_lock);
2927         domain->id = domain_id_alloc();
2928         if (!domain->id)
2929                 return -ENOMEM;
2930         INIT_LIST_HEAD(&domain->dev_list);
2931 
2932         return 0;
2933 }
2934 
2935 static struct protection_domain *protection_domain_alloc(void)
2936 {
2937         struct protection_domain *domain;
2938 
2939         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2940         if (!domain)
2941                 return NULL;
2942 
2943         if (protection_domain_init(domain))
2944                 goto out_err;
2945 
2946         return domain;
2947 
2948 out_err:
2949         kfree(domain);
2950 
2951         return NULL;
2952 }
2953 
2954 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2955 {
2956         struct protection_domain *pdomain;
2957         struct dma_ops_domain *dma_domain;
2958 
2959         switch (type) {
2960         case IOMMU_DOMAIN_UNMANAGED:
2961                 pdomain = protection_domain_alloc();
2962                 if (!pdomain)
2963                         return NULL;
2964 
2965                 pdomain->mode    = PAGE_MODE_3_LEVEL;
2966                 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2967                 if (!pdomain->pt_root) {
2968                         protection_domain_free(pdomain);
2969                         return NULL;
2970                 }
2971 
2972                 pdomain->domain.geometry.aperture_start = 0;
2973                 pdomain->domain.geometry.aperture_end   = ~0ULL;
2974                 pdomain->domain.geometry.force_aperture = true;
2975 
2976                 break;
2977         case IOMMU_DOMAIN_DMA:
2978                 dma_domain = dma_ops_domain_alloc();
2979                 if (!dma_domain) {
2980                         pr_err("Failed to allocate\n");
2981                         return NULL;
2982                 }
2983                 pdomain = &dma_domain->domain;
2984                 break;
2985         case IOMMU_DOMAIN_IDENTITY:
2986                 pdomain = protection_domain_alloc();
2987                 if (!pdomain)
2988                         return NULL;
2989 
2990                 pdomain->mode = PAGE_MODE_NONE;
2991                 break;
2992         default:
2993                 return NULL;
2994         }
2995 
2996         return &pdomain->domain;
2997 }
2998 
2999 static void amd_iommu_domain_free(struct iommu_domain *dom)
3000 {
3001         struct protection_domain *domain;
3002         struct dma_ops_domain *dma_dom;
3003 
3004         domain = to_pdomain(dom);
3005 
3006         if (domain->dev_cnt > 0)
3007                 cleanup_domain(domain);
3008 
3009         BUG_ON(domain->dev_cnt != 0);
3010 
3011         if (!dom)
3012                 return;
3013 
3014         switch (dom->type) {
3015         case IOMMU_DOMAIN_DMA:
3016                 /* Now release the domain */
3017                 dma_dom = to_dma_ops_domain(domain);
3018                 dma_ops_domain_free(dma_dom);
3019                 break;
3020         default:
3021                 if (domain->mode != PAGE_MODE_NONE)
3022                         free_pagetable(domain);
3023 
3024                 if (domain->flags & PD_IOMMUV2_MASK)
3025                         free_gcr3_table(domain);
3026 
3027                 protection_domain_free(domain);
3028                 break;
3029         }
3030 }
3031 
3032 static void amd_iommu_detach_device(struct iommu_domain *dom,
3033                                     struct device *dev)
3034 {
3035         struct iommu_dev_data *dev_data = dev->archdata.iommu;
3036         struct amd_iommu *iommu;
3037         int devid;
3038 
3039         if (!check_device(dev))
3040                 return;
3041 
3042         devid = get_device_id(dev);
3043         if (devid < 0)
3044                 return;
3045 
3046         if (dev_data->domain != NULL)
3047                 detach_device(dev);
3048 
3049         iommu = amd_iommu_rlookup_table[devid];
3050         if (!iommu)
3051                 return;
3052 
3053 #ifdef CONFIG_IRQ_REMAP
3054         if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3055             (dom->type == IOMMU_DOMAIN_UNMANAGED))
3056                 dev_data->use_vapic = 0;
3057 #endif
3058 
3059         iommu_completion_wait(iommu);
3060 }
3061 
3062 static int amd_iommu_attach_device(struct iommu_domain *dom,
3063                                    struct device *dev)
3064 {
3065         struct protection_domain *domain = to_pdomain(dom);
3066         struct iommu_dev_data *dev_data;
3067         struct amd_iommu *iommu;
3068         int ret;
3069 
3070         if (!check_device(dev))
3071                 return -EINVAL;
3072 
3073         dev_data = dev->archdata.iommu;
3074 
3075         iommu = amd_iommu_rlookup_table[dev_data->devid];
3076         if (!iommu)
3077                 return -EINVAL;
3078 
3079         if (dev_data->domain)
3080                 detach_device(dev);
3081 
3082         ret = attach_device(dev, domain);
3083 
3084 #ifdef CONFIG_IRQ_REMAP
3085         if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3086                 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3087                         dev_data->use_vapic = 1;
3088                 else
3089                         dev_data->use_vapic = 0;
3090         }
3091 #endif
3092 
3093         iommu_completion_wait(iommu);
3094 
3095         return ret;
3096 }
3097 
3098 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3099                          phys_addr_t paddr, size_t page_size, int iommu_prot)
3100 {
3101         struct protection_domain *domain = to_pdomain(dom);
3102         int prot = 0;
3103         int ret;
3104 
3105         if (domain->mode == PAGE_MODE_NONE)
3106                 return -EINVAL;
3107 
3108         if (iommu_prot & IOMMU_READ)
3109                 prot |= IOMMU_PROT_IR;
3110         if (iommu_prot & IOMMU_WRITE)
3111                 prot |= IOMMU_PROT_IW;
3112 
3113         mutex_lock(&domain->api_lock);
3114         ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3115         mutex_unlock(&domain->api_lock);
3116 
3117         domain_flush_np_cache(domain, iova, page_size);
3118 
3119         return ret;
3120 }
3121 
3122 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3123                               size_t page_size,
3124                               struct iommu_iotlb_gather *gather)
3125 {
3126         struct protection_domain *domain = to_pdomain(dom);
3127         size_t unmap_size;
3128 
3129         if (domain->mode == PAGE_MODE_NONE)
3130                 return 0;
3131 
3132         mutex_lock(&domain->api_lock);
3133         unmap_size = iommu_unmap_page(domain, iova, page_size);
3134         mutex_unlock(&domain->api_lock);
3135 
3136         return unmap_size;
3137 }
3138 
3139 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3140                                           dma_addr_t iova)
3141 {
3142         struct protection_domain *domain = to_pdomain(dom);
3143         unsigned long offset_mask, pte_pgsize;
3144         u64 *pte, __pte;
3145 
3146         if (domain->mode == PAGE_MODE_NONE)
3147                 return iova;
3148 
3149         pte = fetch_pte(domain, iova, &pte_pgsize);
3150 
3151         if (!pte || !IOMMU_PTE_PRESENT(*pte))
3152                 return 0;
3153 
3154         offset_mask = pte_pgsize - 1;
3155         __pte       = __sme_clr(*pte & PM_ADDR_MASK);
3156 
3157         return (__pte & ~offset_mask) | (iova & offset_mask);
3158 }
3159 
3160 static bool amd_iommu_capable(enum iommu_cap cap)
3161 {
3162         switch (cap) {
3163         case IOMMU_CAP_CACHE_COHERENCY:
3164                 return true;
3165         case IOMMU_CAP_INTR_REMAP:
3166                 return (irq_remapping_enabled == 1);
3167         case IOMMU_CAP_NOEXEC:
3168                 return false;
3169         default:
3170                 break;
3171         }
3172 
3173         return false;
3174 }
3175 
3176 static void amd_iommu_get_resv_regions(struct device *dev,
3177                                        struct list_head *head)
3178 {
3179         struct iommu_resv_region *region;
3180         struct unity_map_entry *entry;
3181         int devid;
3182 
3183         devid = get_device_id(dev);
3184         if (devid < 0)
3185                 return;
3186 
3187         list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3188                 int type, prot = 0;
3189                 size_t length;
3190 
3191                 if (devid < entry->devid_start || devid > entry->devid_end)
3192                         continue;
3193 
3194                 type   = IOMMU_RESV_DIRECT;
3195                 length = entry->address_end - entry->address_start;
3196                 if (entry->prot & IOMMU_PROT_IR)
3197                         prot |= IOMMU_READ;
3198                 if (entry->prot & IOMMU_PROT_IW)
3199                         prot |= IOMMU_WRITE;
3200                 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3201                         /* Exclusion range */
3202                         type = IOMMU_RESV_RESERVED;
3203 
3204                 region = iommu_alloc_resv_region(entry->address_start,
3205                                                  length, prot, type);
3206                 if (!region) {
3207                         dev_err(dev, "Out of memory allocating dm-regions\n");
3208                         return;
3209                 }
3210                 list_add_tail(&region->list, head);
3211         }
3212 
3213         region = iommu_alloc_resv_region(MSI_RANGE_START,
3214                                          MSI_RANGE_END - MSI_RANGE_START + 1,
3215                                          0, IOMMU_RESV_MSI);
3216         if (!region)
3217                 return;
3218         list_add_tail(&region->list, head);
3219 
3220         region = iommu_alloc_resv_region(HT_RANGE_START,
3221                                          HT_RANGE_END - HT_RANGE_START + 1,
3222                                          0, IOMMU_RESV_RESERVED);
3223         if (!region)
3224                 return;
3225         list_add_tail(&region->list, head);
3226 }
3227 
3228 static void amd_iommu_put_resv_regions(struct device *dev,
3229                                      struct list_head *head)
3230 {
3231         struct iommu_resv_region *entry, *next;
3232 
3233         list_for_each_entry_safe(entry, next, head, list)
3234                 kfree(entry);
3235 }
3236 
3237 static void amd_iommu_apply_resv_region(struct device *dev,
3238                                       struct iommu_domain *domain,
3239                                       struct iommu_resv_region *region)
3240 {
3241         struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3242         unsigned long start, end;
3243 
3244         start = IOVA_PFN(region->start);
3245         end   = IOVA_PFN(region->start + region->length - 1);
3246 
3247         WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3248 }
3249 
3250 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3251                                          struct device *dev)
3252 {
3253         struct iommu_dev_data *dev_data = dev->archdata.iommu;
3254         return dev_data->defer_attach;
3255 }
3256 
3257 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3258 {
3259         struct protection_domain *dom = to_pdomain(domain);
3260         unsigned long flags;
3261 
3262         spin_lock_irqsave(&dom->lock, flags);
3263         domain_flush_tlb_pde(dom);
3264         domain_flush_complete(dom);
3265         spin_unlock_irqrestore(&dom->lock, flags);
3266 }
3267 
3268 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
3269                                  struct iommu_iotlb_gather *gather)
3270 {
3271         amd_iommu_flush_iotlb_all(domain);
3272 }
3273 
3274 const struct iommu_ops amd_iommu_ops = {
3275         .capable = amd_iommu_capable,
3276         .domain_alloc = amd_iommu_domain_alloc,
3277         .domain_free  = amd_iommu_domain_free,
3278         .attach_dev = amd_iommu_attach_device,
3279         .detach_dev = amd_iommu_detach_device,
3280         .map = amd_iommu_map,
3281         .unmap = amd_iommu_unmap,
3282         .iova_to_phys = amd_iommu_iova_to_phys,
3283         .add_device = amd_iommu_add_device,
3284         .remove_device = amd_iommu_remove_device,
3285         .device_group = amd_iommu_device_group,
3286         .get_resv_regions = amd_iommu_get_resv_regions,
3287         .put_resv_regions = amd_iommu_put_resv_regions,
3288         .apply_resv_region = amd_iommu_apply_resv_region,
3289         .is_attach_deferred = amd_iommu_is_attach_deferred,
3290         .pgsize_bitmap  = AMD_IOMMU_PGSIZES,
3291         .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3292         .iotlb_sync = amd_iommu_iotlb_sync,
3293 };
3294 
3295 /*****************************************************************************
3296  *
3297  * The next functions do a basic initialization of IOMMU for pass through
3298  * mode
3299  *
3300  * In passthrough mode the IOMMU is initialized and enabled but not used for
3301  * DMA-API translation.
3302  *
3303  *****************************************************************************/
3304 
3305 /* IOMMUv2 specific functions */
3306 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3307 {
3308         return atomic_notifier_chain_register(&ppr_notifier, nb);
3309 }
3310 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3311 
3312 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3313 {
3314         return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3315 }
3316 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3317 
3318 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3319 {
3320         struct protection_domain *domain = to_pdomain(dom);
3321         unsigned long flags;
3322 
3323         spin_lock_irqsave(&domain->lock, flags);
3324 
3325         /* Update data structure */
3326         domain->mode    = PAGE_MODE_NONE;
3327 
3328         /* Make changes visible to IOMMUs */
3329         update_domain(domain);
3330 
3331         /* Page-table is not visible to IOMMU anymore, so free it */
3332         free_pagetable(domain);
3333 
3334         spin_unlock_irqrestore(&domain->lock, flags);
3335 }
3336 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3337 
3338 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3339 {
3340         struct protection_domain *domain = to_pdomain(dom);
3341         unsigned long flags;
3342         int levels, ret;
3343 
3344         if (pasids <= 0 || pasids > (PASID_MASK + 1))
3345                 return -EINVAL;
3346 
3347         /* Number of GCR3 table levels required */
3348         for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3349                 levels += 1;
3350 
3351         if (levels > amd_iommu_max_glx_val)
3352                 return -EINVAL;
3353 
3354         spin_lock_irqsave(&domain->lock, flags);
3355 
3356         /*
3357          * Save us all sanity checks whether devices already in the
3358          * domain support IOMMUv2. Just force that the domain has no
3359          * devices attached when it is switched into IOMMUv2 mode.
3360          */
3361         ret = -EBUSY;
3362         if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3363                 goto out;
3364 
3365         ret = -ENOMEM;
3366         domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3367         if (domain->gcr3_tbl == NULL)
3368                 goto out;
3369 
3370         domain->glx      = levels;
3371         domain->flags   |= PD_IOMMUV2_MASK;
3372 
3373         update_domain(domain);
3374 
3375         ret = 0;
3376 
3377 out:
3378         spin_unlock_irqrestore(&domain->lock, flags);
3379 
3380         return ret;
3381 }
3382 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3383 
3384 static int __flush_pasid(struct protection_domain *domain, int pasid,
3385                          u64 address, bool size)
3386 {
3387         struct iommu_dev_data *dev_data;
3388         struct iommu_cmd cmd;
3389         int i, ret;
3390 
3391         if (!(domain->flags & PD_IOMMUV2_MASK))
3392                 return -EINVAL;
3393 
3394         build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3395 
3396         /*
3397          * IOMMU TLB needs to be flushed before Device TLB to
3398          * prevent device TLB refill from IOMMU TLB
3399          */
3400         for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3401                 if (domain->dev_iommu[i] == 0)
3402                         continue;
3403 
3404                 ret = iommu_queue_command(amd_iommus[i], &cmd);
3405                 if (ret != 0)
3406                         goto out;
3407         }
3408 
3409         /* Wait until IOMMU TLB flushes are complete */
3410         domain_flush_complete(domain);
3411 
3412         /* Now flush device TLBs */
3413         list_for_each_entry(dev_data, &domain->dev_list, list) {
3414                 struct amd_iommu *iommu;
3415                 int qdep;
3416 
3417                 /*
3418                    There might be non-IOMMUv2 capable devices in an IOMMUv2
3419                  * domain.
3420                  */
3421                 if (!dev_data->ats.enabled)
3422                         continue;
3423 
3424                 qdep  = dev_data->ats.qdep;
3425                 iommu = amd_iommu_rlookup_table[dev_data->devid];
3426 
3427                 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3428                                       qdep, address, size);
3429 
3430                 ret = iommu_queue_command(iommu, &cmd);
3431                 if (ret != 0)
3432                         goto out;
3433         }
3434 
3435         /* Wait until all device TLBs are flushed */
3436         domain_flush_complete(domain);
3437 
3438         ret = 0;
3439 
3440 out:
3441 
3442         return ret;
3443 }
3444 
3445 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3446                                   u64 address)
3447 {
3448         return __flush_pasid(domain, pasid, address, false);
3449 }
3450 
3451 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3452                          u64 address)
3453 {
3454         struct protection_domain *domain = to_pdomain(dom);
3455         unsigned long flags;
3456         int ret;
3457 
3458         spin_lock_irqsave(&domain->lock, flags);
3459         ret = __amd_iommu_flush_page(domain, pasid, address);
3460         spin_unlock_irqrestore(&domain->lock, flags);
3461 
3462         return ret;
3463 }
3464 EXPORT_SYMBOL(amd_iommu_flush_page);
3465 
3466 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3467 {
3468         return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3469                              true);
3470 }
3471 
3472 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3473 {
3474         struct protection_domain *domain = to_pdomain(dom);
3475         unsigned long flags;
3476         int ret;
3477 
3478         spin_lock_irqsave(&domain->lock, flags);
3479         ret = __amd_iommu_flush_tlb(domain, pasid);
3480         spin_unlock_irqrestore(&domain->lock, flags);
3481 
3482         return ret;
3483 }
3484 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3485 
3486 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3487 {
3488         int index;
3489         u64 *pte;
3490 
3491         while (true) {
3492 
3493                 index = (pasid >> (9 * level)) & 0x1ff;
3494                 pte   = &root[index];
3495 
3496                 if (level == 0)
3497                         break;
3498 
3499                 if (!(*pte & GCR3_VALID)) {
3500                         if (!alloc)
3501                                 return NULL;
3502 
3503                         root = (void *)get_zeroed_page(GFP_ATOMIC);
3504                         if (root == NULL)
3505                                 return NULL;
3506 
3507                         *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3508                 }
3509 
3510                 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3511 
3512                 level -= 1;
3513         }
3514 
3515         return pte;
3516 }
3517 
3518 static int __set_gcr3(struct protection_domain *domain, int pasid,
3519                       unsigned long cr3)
3520 {
3521         u64 *pte;
3522 
3523         if (domain->mode != PAGE_MODE_NONE)
3524                 return -EINVAL;
3525 
3526         pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3527         if (pte == NULL)
3528                 return -ENOMEM;
3529 
3530         *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3531 
3532         return __amd_iommu_flush_tlb(domain, pasid);
3533 }
3534 
3535 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3536 {
3537         u64 *pte;
3538 
3539         if (domain->mode != PAGE_MODE_NONE)
3540                 return -EINVAL;
3541 
3542         pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3543         if (pte == NULL)
3544                 return 0;
3545 
3546         *pte = 0;
3547 
3548         return __amd_iommu_flush_tlb(domain, pasid);
3549 }
3550 
3551 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3552                               unsigned long cr3)
3553 {
3554         struct protection_domain *domain = to_pdomain(dom);
3555         unsigned long flags;
3556         int ret;
3557 
3558         spin_lock_irqsave(&domain->lock, flags);
3559         ret = __set_gcr3(domain, pasid, cr3);
3560         spin_unlock_irqrestore(&domain->lock, flags);
3561 
3562         return ret;
3563 }
3564 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3565 
3566 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3567 {
3568         struct protection_domain *domain = to_pdomain(dom);
3569         unsigned long flags;
3570         int ret;
3571 
3572         spin_lock_irqsave(&domain->lock, flags);
3573         ret = __clear_gcr3(domain, pasid);
3574         spin_unlock_irqrestore(&domain->lock, flags);
3575 
3576         return ret;
3577 }
3578 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3579 
3580 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3581                            int status, int tag)
3582 {
3583         struct iommu_dev_data *dev_data;
3584         struct amd_iommu *iommu;
3585         struct iommu_cmd cmd;
3586 
3587         dev_data = get_dev_data(&pdev->dev);
3588         iommu    = amd_iommu_rlookup_table[dev_data->devid];
3589 
3590         build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3591                            tag, dev_data->pri_tlp);
3592 
3593         return iommu_queue_command(iommu, &cmd);
3594 }
3595 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3596 
3597 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3598 {
3599         struct protection_domain *pdomain;
3600 
3601         pdomain = get_domain(&pdev->dev);
3602         if (IS_ERR(pdomain))
3603                 return NULL;
3604 
3605         /* Only return IOMMUv2 domains */
3606         if (!(pdomain->flags & PD_IOMMUV2_MASK))
3607                 return NULL;
3608 
3609         return &pdomain->domain;
3610 }
3611 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3612 
3613 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3614 {
3615         struct iommu_dev_data *dev_data;
3616 
3617         if (!amd_iommu_v2_supported())
3618                 return;
3619 
3620         dev_data = get_dev_data(&pdev->dev);
3621         dev_data->errata |= (1 << erratum);
3622 }
3623 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3624 
3625 int amd_iommu_device_info(struct pci_dev *pdev,
3626                           struct amd_iommu_device_info *info)
3627 {
3628         int max_pasids;
3629         int pos;
3630 
3631         if (pdev == NULL || info == NULL)
3632                 return -EINVAL;
3633 
3634         if (!amd_iommu_v2_supported())
3635                 return -EINVAL;
3636 
3637         memset(info, 0, sizeof(*info));
3638 
3639         if (!pci_ats_disabled()) {
3640                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3641                 if (pos)
3642                         info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3643         }
3644 
3645         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3646         if (pos)
3647                 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3648 
3649         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3650         if (pos) {
3651                 int features;
3652 
3653                 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3654                 max_pasids = min(max_pasids, (1 << 20));
3655 
3656                 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3657                 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3658 
3659                 features = pci_pasid_features(pdev);
3660                 if (features & PCI_PASID_CAP_EXEC)
3661                         info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3662                 if (features & PCI_PASID_CAP_PRIV)
3663                         info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3664         }
3665 
3666         return 0;
3667 }
3668 EXPORT_SYMBOL(amd_iommu_device_info);
3669 
3670 #ifdef CONFIG_IRQ_REMAP
3671 
3672 /*****************************************************************************
3673  *
3674  * Interrupt Remapping Implementation
3675  *
3676  *****************************************************************************/
3677 
3678 static struct irq_chip amd_ir_chip;
3679 static DEFINE_SPINLOCK(iommu_table_lock);
3680 
3681 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3682 {
3683         u64 dte;
3684 
3685         dte     = amd_iommu_dev_table[devid].data[2];
3686         dte     &= ~DTE_IRQ_PHYS_ADDR_MASK;
3687         dte     |= iommu_virt_to_phys(table->table);
3688         dte     |= DTE_IRQ_REMAP_INTCTL;
3689         dte     |= DTE_IRQ_TABLE_LEN;
3690         dte     |= DTE_IRQ_REMAP_ENABLE;
3691 
3692         amd_iommu_dev_table[devid].data[2] = dte;
3693 }
3694 
3695 static struct irq_remap_table *get_irq_table(u16 devid)
3696 {
3697         struct irq_remap_table *table;
3698 
3699         if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3700                       "%s: no iommu for devid %x\n", __func__, devid))
3701                 return NULL;
3702 
3703         table = irq_lookup_table[devid];
3704         if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3705                 return NULL;
3706 
3707         return table;
3708 }
3709 
3710 static struct irq_remap_table *__alloc_irq_table(void)
3711 {
3712         struct irq_remap_table *table;
3713 
3714         table = kzalloc(sizeof(*table), GFP_KERNEL);
3715         if (!table)
3716                 return NULL;
3717 
3718         table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3719         if (!table->table) {
3720                 kfree(table);
3721                 return NULL;
3722         }
3723         raw_spin_lock_init(&table->lock);
3724 
3725         if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3726                 memset(table->table, 0,
3727                        MAX_IRQS_PER_TABLE * sizeof(u32));
3728         else
3729                 memset(table->table, 0,
3730                        (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3731         return table;
3732 }
3733 
3734 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3735                                   struct irq_remap_table *table)
3736 {
3737         irq_lookup_table[devid] = table;
3738         set_dte_irq_entry(devid, table);
3739         iommu_flush_dte(iommu, devid);
3740 }
3741 
3742 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3743                                        void *data)
3744 {
3745         struct irq_remap_table *table = data;
3746 
3747         irq_lookup_table[alias] = table;
3748         set_dte_irq_entry(alias, table);
3749 
3750         iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3751 
3752         return 0;
3753 }
3754 
3755 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3756 {
3757         struct irq_remap_table *table = NULL;
3758         struct irq_remap_table *new_table = NULL;
3759         struct amd_iommu *iommu;
3760         unsigned long flags;
3761         u16 alias;
3762 
3763         spin_lock_irqsave(&iommu_table_lock, flags);
3764 
3765         iommu = amd_iommu_rlookup_table[devid];
3766         if (!iommu)
3767                 goto out_unlock;
3768 
3769         table = irq_lookup_table[devid];
3770         if (table)
3771                 goto out_unlock;
3772 
3773         alias = amd_iommu_alias_table[devid];
3774         table = irq_lookup_table[alias];
3775         if (table) {
3776                 set_remap_table_entry(iommu, devid, table);
3777                 goto out_wait;
3778         }
3779         spin_unlock_irqrestore(&iommu_table_lock, flags);
3780 
3781         /* Nothing there yet, allocate new irq remapping table */
3782         new_table = __alloc_irq_table();
3783         if (!new_table)
3784                 return NULL;
3785 
3786         spin_lock_irqsave(&iommu_table_lock, flags);
3787 
3788         table = irq_lookup_table[devid];
3789         if (table)
3790                 goto out_unlock;
3791 
3792         table = irq_lookup_table[alias];
3793         if (table) {
3794                 set_remap_table_entry(iommu, devid, table);
3795                 goto out_wait;
3796         }
3797 
3798         table = new_table;
3799         new_table = NULL;
3800 
3801         if (pdev)
3802                 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3803                                        table);
3804         else
3805                 set_remap_table_entry(iommu, devid, table);
3806 
3807         if (devid != alias)
3808                 set_remap_table_entry(iommu, alias, table);
3809 
3810 out_wait:
3811         iommu_completion_wait(iommu);
3812 
3813 out_unlock:
3814         spin_unlock_irqrestore(&iommu_table_lock, flags);
3815 
3816         if (new_table) {
3817                 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3818                 kfree(new_table);
3819         }
3820         return table;
3821 }
3822 
3823 static int alloc_irq_index(u16 devid, int count, bool align,
3824                            struct pci_dev *pdev)
3825 {
3826         struct irq_remap_table *table;
3827         int index, c, alignment = 1;
3828         unsigned long flags;
3829         struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3830 
3831         if (!iommu)
3832                 return -ENODEV;
3833 
3834         table = alloc_irq_table(devid, pdev);
3835         if (!table)
3836                 return -ENODEV;
3837 
3838         if (align)
3839                 alignment = roundup_pow_of_two(count);
3840 
3841         raw_spin_lock_irqsave(&table->lock, flags);
3842 
3843         /* Scan table for free entries */
3844         for (index = ALIGN(table->min_index, alignment), c = 0;
3845              index < MAX_IRQS_PER_TABLE;) {
3846                 if (!iommu->irte_ops->is_allocated(table, index)) {
3847                         c += 1;
3848                 } else {
3849                         c     = 0;
3850                         index = ALIGN(index + 1, alignment);
3851                         continue;
3852                 }
3853 
3854                 if (c == count) {
3855                         for (; c != 0; --c)
3856                                 iommu->irte_ops->set_allocated(table, index - c + 1);
3857 
3858                         index -= count - 1;
3859                         goto out;
3860                 }
3861 
3862                 index++;
3863         }
3864 
3865         index = -ENOSPC;
3866 
3867 out:
3868         raw_spin_unlock_irqrestore(&table->lock, flags);
3869 
3870         return index;
3871 }
3872 
3873 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3874                           struct amd_ir_data *data)
3875 {
3876         struct irq_remap_table *table;
3877         struct amd_iommu *iommu;
3878         unsigned long flags;
3879         struct irte_ga *entry;
3880 
3881         iommu = amd_iommu_rlookup_table[devid];
3882         if (iommu == NULL)
3883                 return -EINVAL;
3884 
3885         table = get_irq_table(devid);
3886         if (!table)
3887                 return -ENOMEM;
3888 
3889         raw_spin_lock_irqsave(&table->lock, flags);
3890 
3891         entry = (struct irte_ga *)table->table;
3892         entry = &entry[index];
3893         entry->lo.fields_remap.valid = 0;
3894         entry->hi.val = irte->hi.val;
3895         entry->lo.val = irte->lo.val;
3896         entry->lo.fields_remap.valid = 1;
3897         if (data)
3898                 data->ref = entry;
3899 
3900         raw_spin_unlock_irqrestore(&table->lock, flags);
3901 
3902         iommu_flush_irt(iommu, devid);
3903         iommu_completion_wait(iommu);
3904 
3905         return 0;
3906 }
3907 
3908 static int modify_irte(u16 devid, int index, union irte *irte)
3909 {
3910         struct irq_remap_table *table;
3911         struct amd_iommu *iommu;
3912         unsigned long flags;
3913 
3914         iommu = amd_iommu_rlookup_table[devid];
3915         if (iommu == NULL)
3916                 return -EINVAL;
3917 
3918         table = get_irq_table(devid);
3919         if (!table)
3920                 return -ENOMEM;
3921 
3922         raw_spin_lock_irqsave(&table->lock, flags);
3923         table->table[index] = irte->val;
3924         raw_spin_unlock_irqrestore(&table->lock, flags);
3925 
3926         iommu_flush_irt(iommu, devid);
3927         iommu_completion_wait(iommu);
3928 
3929         return 0;
3930 }
3931 
3932 static void free_irte(u16 devid, int index)
3933 {
3934         struct irq_remap_table *table;
3935         struct amd_iommu *iommu;
3936         unsigned long flags;
3937 
3938         iommu = amd_iommu_rlookup_table[devid];
3939         if (iommu == NULL)
3940                 return;
3941 
3942         table = get_irq_table(devid);
3943         if (!table)
3944                 return;
3945 
3946         raw_spin_lock_irqsave(&table->lock, flags);
3947         iommu->irte_ops->clear_allocated(table, index);
3948         raw_spin_unlock_irqrestore(&table->lock, flags);
3949 
3950         iommu_flush_irt(iommu, devid);
3951         iommu_completion_wait(iommu);
3952 }
3953 
3954 static void irte_prepare(void *entry,
3955                          u32 delivery_mode, u32 dest_mode,
3956                          u8 vector, u32 dest_apicid, int devid)
3957 {
3958         union irte *irte = (union irte *) entry;
3959 
3960         irte->val                = 0;
3961         irte->fields.vector      = vector;
3962         irte->fields.int_type    = delivery_mode;
3963         irte->fields.destination = dest_apicid;
3964         irte->fields.dm          = dest_mode;
3965         irte->fields.valid       = 1;
3966 }
3967 
3968 static void irte_ga_prepare(void *entry,
3969                             u32 delivery_mode, u32 dest_mode,
3970                             u8 vector, u32 dest_apicid, int devid)
3971 {
3972         struct irte_ga *irte = (struct irte_ga *) entry;
3973 
3974         irte->lo.val                      = 0;
3975         irte->hi.val                      = 0;
3976         irte->lo.fields_remap.int_type    = delivery_mode;
3977         irte->lo.fields_remap.dm          = dest_mode;
3978         irte->hi.fields.vector            = vector;
3979         irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3980         irte->hi.fields.destination       = APICID_TO_IRTE_DEST_HI(dest_apicid);
3981         irte->lo.fields_remap.valid       = 1;
3982 }
3983 
3984 static void irte_activate(void *entry, u16 devid, u16 index)
3985 {
3986         union irte *irte = (union irte *) entry;
3987 
3988         irte->fields.valid = 1;
3989         modify_irte(devid, index, irte);
3990 }
3991 
3992 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3993 {
3994         struct irte_ga *irte = (struct irte_ga *) entry;
3995 
3996         irte->lo.fields_remap.valid = 1;
3997         modify_irte_ga(devid, index, irte, NULL);
3998 }
3999 
4000 static void irte_deactivate(void *entry, u16 devid, u16 index)
4001 {
4002         union irte *irte = (union irte *) entry;
4003 
4004         irte->fields.valid = 0;
4005         modify_irte(devid, index, irte);
4006 }
4007 
4008 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
4009 {
4010         struct irte_ga *irte = (struct irte_ga *) entry;
4011 
4012         irte->lo.fields_remap.valid = 0;
4013         modify_irte_ga(devid, index, irte, NULL);
4014 }
4015 
4016 static void irte_set_affinity(void *entry, u16 devid, u16 index,
4017                               u8 vector, u32 dest_apicid)
4018 {
4019         union irte *irte = (union irte *) entry;
4020 
4021         irte->fields.vector = vector;
4022         irte->fields.destination = dest_apicid;
4023         modify_irte(devid, index, irte);
4024 }
4025 
4026 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
4027                                  u8 vector, u32 dest_apicid)
4028 {
4029         struct irte_ga *irte = (struct irte_ga *) entry;
4030 
4031         if (!irte->lo.fields_remap.guest_mode) {
4032                 irte->hi.fields.vector = vector;
4033                 irte->lo.fields_remap.destination =
4034                                         APICID_TO_IRTE_DEST_LO(dest_apicid);
4035                 irte->hi.fields.destination =
4036                                         APICID_TO_IRTE_DEST_HI(dest_apicid);
4037                 modify_irte_ga(devid, index, irte, NULL);
4038         }
4039 }
4040 
4041 #define IRTE_ALLOCATED (~1U)
4042 static void irte_set_allocated(struct irq_remap_table *table, int index)
4043 {
4044         table->table[index] = IRTE_ALLOCATED;
4045 }
4046 
4047 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4048 {
4049         struct irte_ga *ptr = (struct irte_ga *)table->table;
4050         struct irte_ga *irte = &ptr[index];
4051 
4052         memset(&irte->lo.val, 0, sizeof(u64));
4053         memset(&irte->hi.val, 0, sizeof(u64));
4054         irte->hi.fields.vector = 0xff;
4055 }
4056 
4057 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4058 {
4059         union irte *ptr = (union irte *)table->table;
4060         union irte *irte = &ptr[index];
4061 
4062         return irte->val != 0;
4063 }
4064 
4065 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4066 {
4067         struct irte_ga *ptr = (struct irte_ga *)table->table;
4068         struct irte_ga *irte = &ptr[index];
4069 
4070         return irte->hi.fields.vector != 0;
4071 }
4072 
4073 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4074 {
4075         table->table[index] = 0;
4076 }
4077 
4078 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4079 {
4080         struct irte_ga *ptr = (struct irte_ga *)table->table;
4081         struct irte_ga *irte = &ptr[index];
4082 
4083         memset(&irte->lo.val, 0, sizeof(u64));
4084         memset(&irte->hi.val, 0, sizeof(u64));
4085 }
4086 
4087 static int get_devid(struct irq_alloc_info *info)
4088 {
4089         int devid = -1;
4090 
4091         switch (info->type) {
4092         case X86_IRQ_ALLOC_TYPE_IOAPIC:
4093                 devid     = get_ioapic_devid(info->ioapic_id);
4094                 break;
4095         case X86_IRQ_ALLOC_TYPE_HPET:
4096                 devid     = get_hpet_devid(info->hpet_id);
4097                 break;
4098         case X86_IRQ_ALLOC_TYPE_MSI:
4099         case X86_IRQ_ALLOC_TYPE_MSIX:
4100                 devid = get_device_id(&info->msi_dev->dev);
4101                 break;
4102         default:
4103                 BUG_ON(1);
4104                 break;
4105         }
4106 
4107         return devid;
4108 }
4109 
4110 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4111 {
4112         struct amd_iommu *iommu;
4113         int devid;
4114 
4115         if (!info)
4116                 return NULL;
4117 
4118         devid = get_devid(info);
4119         if (devid >= 0) {
4120                 iommu = amd_iommu_rlookup_table[devid];
4121                 if (iommu)
4122                         return iommu->ir_domain;
4123         }
4124 
4125         return NULL;
4126 }
4127 
4128 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4129 {
4130         struct amd_iommu *iommu;
4131         int devid;
4132 
4133         if (!info)
4134                 return NULL;
4135 
4136         switch (info->type) {
4137         case X86_IRQ_ALLOC_TYPE_MSI:
4138         case X86_IRQ_ALLOC_TYPE_MSIX:
4139                 devid = get_device_id(&info->msi_dev->dev);
4140                 if (devid < 0)
4141                         return NULL;
4142 
4143                 iommu = amd_iommu_rlookup_table[devid];
4144                 if (iommu)
4145                         return iommu->msi_domain;
4146                 break;
4147         default:
4148                 break;
4149         }
4150 
4151         return NULL;
4152 }
4153 
4154 struct irq_remap_ops amd_iommu_irq_ops = {
4155         .prepare                = amd_iommu_prepare,
4156         .enable                 = amd_iommu_enable,
4157         .disable                = amd_iommu_disable,
4158         .reenable               = amd_iommu_reenable,
4159         .enable_faulting        = amd_iommu_enable_faulting,
4160         .get_ir_irq_domain      = get_ir_irq_domain,
4161         .get_irq_domain         = get_irq_domain,
4162 };
4163 
4164 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4165                                        struct irq_cfg *irq_cfg,
4166                                        struct irq_alloc_info *info,
4167                                        int devid, int index, int sub_handle)
4168 {
4169         struct irq_2_irte *irte_info = &data->irq_2_irte;
4170         struct msi_msg *msg = &data->msi_entry;
4171         struct IO_APIC_route_entry *entry;
4172         struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4173 
4174         if (!iommu)
4175                 return;
4176 
4177         data->irq_2_irte.devid = devid;
4178         data->irq_2_irte.index = index + sub_handle;
4179         iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4180                                  apic->irq_dest_mode, irq_cfg->vector,
4181                                  irq_cfg->dest_apicid, devid);
4182 
4183         switch (info->type) {
4184         case X86_IRQ_ALLOC_TYPE_IOAPIC:
4185                 /* Setup IOAPIC entry */
4186                 entry = info->ioapic_entry;
4187                 info->ioapic_entry = NULL;
4188                 memset(entry, 0, sizeof(*entry));
4189                 entry->vector        = index;
4190                 entry->mask          = 0;
4191                 entry->trigger       = info->ioapic_trigger;
4192                 entry->polarity      = info->ioapic_polarity;
4193                 /* Mask level triggered irqs. */
4194                 if (info->ioapic_trigger)
4195                         entry->mask = 1;
4196                 break;
4197 
4198         case X86_IRQ_ALLOC_TYPE_HPET:
4199         case X86_IRQ_ALLOC_TYPE_MSI:
4200         case X86_IRQ_ALLOC_TYPE_MSIX:
4201                 msg->address_hi = MSI_ADDR_BASE_HI;
4202                 msg->address_lo = MSI_ADDR_BASE_LO;
4203                 msg->data = irte_info->index;
4204                 break;
4205 
4206         default:
4207                 BUG_ON(1);
4208                 break;
4209         }
4210 }
4211 
4212 struct amd_irte_ops irte_32_ops = {
4213         .prepare = irte_prepare,
4214         .activate = irte_activate,
4215         .deactivate = irte_deactivate,
4216         .set_affinity = irte_set_affinity,
4217         .set_allocated = irte_set_allocated,
4218         .is_allocated = irte_is_allocated,
4219         .clear_allocated = irte_clear_allocated,
4220 };
4221 
4222 struct amd_irte_ops irte_128_ops = {
4223         .prepare = irte_ga_prepare,
4224         .activate = irte_ga_activate,
4225         .deactivate = irte_ga_deactivate,
4226         .set_affinity = irte_ga_set_affinity,
4227         .set_allocated = irte_ga_set_allocated,
4228         .is_allocated = irte_ga_is_allocated,
4229         .clear_allocated = irte_ga_clear_allocated,
4230 };
4231 
4232 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4233                                unsigned int nr_irqs, void *arg)
4234 {
4235         struct irq_alloc_info *info = arg;
4236         struct irq_data *irq_data;
4237         struct amd_ir_data *data = NULL;
4238         struct irq_cfg *cfg;
4239         int i, ret, devid;
4240         int index;
4241 
4242         if (!info)
4243                 return -EINVAL;
4244         if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4245             info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4246                 return -EINVAL;
4247 
4248         /*
4249          * With IRQ remapping enabled, don't need contiguous CPU vectors
4250          * to support multiple MSI interrupts.
4251          */
4252         if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4253                 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4254 
4255         devid = get_devid(info);
4256         if (devid < 0)
4257                 return -EINVAL;
4258 
4259         ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4260         if (ret < 0)
4261                 return ret;
4262 
4263         if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4264                 struct irq_remap_table *table;
4265                 struct amd_iommu *iommu;
4266 
4267                 table = alloc_irq_table(devid, NULL);
4268                 if (table) {
4269                         if (!table->min_index) {
4270                                 /*
4271                                  * Keep the first 32 indexes free for IOAPIC
4272                                  * interrupts.
4273                                  */
4274                                 table->min_index = 32;
4275                                 iommu = amd_iommu_rlookup_table[devid];
4276                                 for (i = 0; i < 32; ++i)
4277                                         iommu->irte_ops->set_allocated(table, i);
4278                         }
4279                         WARN_ON(table->min_index != 32);
4280                         index = info->ioapic_pin;
4281                 } else {
4282                         index = -ENOMEM;
4283                 }
4284         } else if (info->type == X86_IRQ_ALLOC_TYPE_MSI ||
4285                    info->type == X86_IRQ_ALLOC_TYPE_MSIX) {
4286                 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4287 
4288                 index = alloc_irq_index(devid, nr_irqs, align, info->msi_dev);
4289         } else {
4290                 index = alloc_irq_index(devid, nr_irqs, false, NULL);
4291         }
4292 
4293         if (index < 0) {
4294                 pr_warn("Failed to allocate IRTE\n");
4295                 ret = index;
4296                 goto out_free_parent;
4297         }
4298 
4299         for (i = 0; i < nr_irqs; i++) {
4300                 irq_data = irq_domain_get_irq_data(domain, virq + i);
4301                 cfg = irqd_cfg(irq_data);
4302                 if (!irq_data || !cfg) {
4303                         ret = -EINVAL;
4304                         goto out_free_data;
4305                 }
4306 
4307                 ret = -ENOMEM;
4308                 data = kzalloc(sizeof(*data), GFP_KERNEL);
4309                 if (!data)
4310                         goto out_free_data;
4311 
4312                 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4313                         data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4314                 else
4315                         data->entry = kzalloc(sizeof(struct irte_ga),
4316                                                      GFP_KERNEL);
4317                 if (!data->entry) {
4318                         kfree(data);
4319                         goto out_free_data;
4320                 }
4321 
4322                 irq_data->hwirq = (devid << 16) + i;
4323                 irq_data->chip_data = data;
4324                 irq_data->chip = &amd_ir_chip;
4325                 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4326                 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4327         }
4328 
4329         return 0;
4330 
4331 out_free_data:
4332         for (i--; i >= 0; i--) {
4333                 irq_data = irq_domain_get_irq_data(domain, virq + i);
4334                 if (irq_data)
4335                         kfree(irq_data->chip_data);
4336         }
4337         for (i = 0; i < nr_irqs; i++)
4338                 free_irte(devid, index + i);
4339 out_free_parent:
4340         irq_domain_free_irqs_common(domain, virq, nr_irqs);
4341         return ret;
4342 }
4343 
4344 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4345                                unsigned int nr_irqs)
4346 {
4347         struct irq_2_irte *irte_info;
4348         struct irq_data *irq_data;
4349         struct amd_ir_data *data;
4350         int i;
4351 
4352         for (i = 0; i < nr_irqs; i++) {
4353                 irq_data = irq_domain_get_irq_data(domain, virq  + i);
4354                 if (irq_data && irq_data->chip_data) {
4355                         data = irq_data->chip_data;
4356                         irte_info = &data->irq_2_irte;
4357                         free_irte(irte_info->devid, irte_info->index);
4358                         kfree(data->entry);
4359                         kfree(data);
4360                 }
4361         }
4362         irq_domain_free_irqs_common(domain, virq, nr_irqs);
4363 }
4364 
4365 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4366                                struct amd_ir_data *ir_data,
4367                                struct irq_2_irte *irte_info,
4368                                struct irq_cfg *cfg);
4369 
4370 static int irq_remapping_activate(struct irq_domain *domain,
4371                                   struct irq_data *irq_data, bool reserve)
4372 {
4373         struct amd_ir_data *data = irq_data->chip_data;
4374         struct irq_2_irte *irte_info = &data->irq_2_irte;
4375         struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4376         struct irq_cfg *cfg = irqd_cfg(irq_data);
4377 
4378         if (!iommu)
4379                 return 0;
4380 
4381         iommu->irte_ops->activate(data->entry, irte_info->devid,
4382                                   irte_info->index);
4383         amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4384         return 0;
4385 }
4386 
4387 static void irq_remapping_deactivate(struct irq_domain *domain,
4388                                      struct irq_data *irq_data)
4389 {
4390         struct amd_ir_data *data = irq_data->chip_data;
4391         struct irq_2_irte *irte_info = &data->irq_2_irte;
4392         struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4393 
4394         if (iommu)
4395                 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4396                                             irte_info->index);
4397 }
4398 
4399 static const struct irq_domain_ops amd_ir_domain_ops = {
4400         .alloc = irq_remapping_alloc,
4401         .free = irq_remapping_free,
4402         .activate = irq_remapping_activate,
4403         .deactivate = irq_remapping_deactivate,
4404 };
4405 
4406 int amd_iommu_activate_guest_mode(void *data)
4407 {
4408         struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4409         struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4410 
4411         if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4412             !entry || entry->lo.fields_vapic.guest_mode)
4413                 return 0;
4414 
4415         entry->lo.val = 0;
4416         entry->hi.val = 0;
4417 
4418         entry->lo.fields_vapic.guest_mode  = 1;
4419         entry->lo.fields_vapic.ga_log_intr = 1;
4420         entry->hi.fields.ga_root_ptr       = ir_data->ga_root_ptr;
4421         entry->hi.fields.vector            = ir_data->ga_vector;
4422         entry->lo.fields_vapic.ga_tag      = ir_data->ga_tag;
4423 
4424         return modify_irte_ga(ir_data->irq_2_irte.devid,
4425                               ir_data->irq_2_irte.index, entry, ir_data);
4426 }
4427 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
4428 
4429 int amd_iommu_deactivate_guest_mode(void *data)
4430 {
4431         struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4432         struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4433         struct irq_cfg *cfg = ir_data->cfg;
4434 
4435         if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4436             !entry || !entry->lo.fields_vapic.guest_mode)
4437                 return 0;
4438 
4439         entry->lo.val = 0;
4440         entry->hi.val = 0;
4441 
4442         entry->lo.fields_remap.dm          = apic->irq_dest_mode;
4443         entry->lo.fields_remap.int_type    = apic->irq_delivery_mode;
4444         entry->hi.fields.vector            = cfg->vector;
4445         entry->lo.fields_remap.destination =
4446                                 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4447         entry->hi.fields.destination =
4448                                 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4449 
4450         return modify_irte_ga(ir_data->irq_2_irte.devid,
4451                               ir_data->irq_2_irte.index, entry, ir_data);
4452 }
4453 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
4454 
4455 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4456 {
4457         int ret;
4458         struct amd_iommu *iommu;
4459         struct amd_iommu_pi_data *pi_data = vcpu_info;
4460         struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4461         struct amd_ir_data *ir_data = data->chip_data;
4462         struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4463         struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4464 
4465         /* Note:
4466          * This device has never been set up for guest mode.
4467          * we should not modify the IRTE
4468          */
4469         if (!dev_data || !dev_data->use_vapic)
4470                 return 0;
4471 
4472         ir_data->cfg = irqd_cfg(data);
4473         pi_data->ir_data = ir_data;
4474 
4475         /* Note:
4476          * SVM tries to set up for VAPIC mode, but we are in
4477          * legacy mode. So, we force legacy mode instead.
4478          */
4479         if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4480                 pr_debug("%s: Fall back to using intr legacy remap\n",
4481                          __func__);
4482                 pi_data->is_guest_mode = false;
4483         }
4484 
4485         iommu = amd_iommu_rlookup_table[irte_info->devid];
4486         if (iommu == NULL)
4487                 return -EINVAL;
4488 
4489         pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4490         if (pi_data->is_guest_mode) {
4491                 ir_data->ga_root_ptr = (pi_data->base >> 12);
4492                 ir_data->ga_vector = vcpu_pi_info->vector;
4493                 ir_data->ga_tag = pi_data->ga_tag;
4494                 ret = amd_iommu_activate_guest_mode(ir_data);
4495                 if (!ret)
4496                         ir_data->cached_ga_tag = pi_data->ga_tag;
4497         } else {
4498                 ret = amd_iommu_deactivate_guest_mode(ir_data);
4499 
4500                 /*
4501                  * This communicates the ga_tag back to the caller
4502                  * so that it can do all the necessary clean up.
4503                  */
4504                 if (!ret)
4505                         ir_data->cached_ga_tag = 0;
4506         }
4507 
4508         return ret;
4509 }
4510 
4511 
4512 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4513                                struct amd_ir_data *ir_data,
4514                                struct irq_2_irte *irte_info,
4515                                struct irq_cfg *cfg)
4516 {
4517 
4518         /*
4519          * Atomically updates the IRTE with the new destination, vector
4520          * and flushes the interrupt entry cache.
4521          */
4522         iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4523                                       irte_info->index, cfg->vector,
4524                                       cfg->dest_apicid);
4525 }
4526 
4527 static int amd_ir_set_affinity(struct irq_data *data,
4528                                const struct cpumask *mask, bool force)
4529 {
4530         struct amd_ir_data *ir_data = data->chip_data;
4531         struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4532         struct irq_cfg *cfg = irqd_cfg(data);
4533         struct irq_data *parent = data->parent_data;
4534         struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4535         int ret;
4536 
4537         if (!iommu)
4538                 return -ENODEV;
4539 
4540         ret = parent->chip->irq_set_affinity(parent, mask, force);
4541         if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4542                 return ret;
4543 
4544         amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4545         /*
4546          * After this point, all the interrupts will start arriving
4547          * at the new destination. So, time to cleanup the previous
4548          * vector allocation.
4549          */
4550         send_cleanup_vector(cfg);
4551 
4552         return IRQ_SET_MASK_OK_DONE;
4553 }
4554 
4555 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4556 {
4557         struct amd_ir_data *ir_data = irq_data->chip_data;
4558 
4559         *msg = ir_data->msi_entry;
4560 }
4561 
4562 static struct irq_chip amd_ir_chip = {
4563         .name                   = "AMD-IR",
4564         .irq_ack                = apic_ack_irq,
4565         .irq_set_affinity       = amd_ir_set_affinity,
4566         .irq_set_vcpu_affinity  = amd_ir_set_vcpu_affinity,
4567         .irq_compose_msi_msg    = ir_compose_msi_msg,
4568 };
4569 
4570 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4571 {
4572         struct fwnode_handle *fn;
4573 
4574         fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4575         if (!fn)
4576                 return -ENOMEM;
4577         iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4578         irq_domain_free_fwnode(fn);
4579         if (!iommu->ir_domain)
4580                 return -ENOMEM;
4581 
4582         iommu->ir_domain->parent = arch_get_ir_parent_domain();
4583         iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4584                                                              "AMD-IR-MSI",
4585                                                              iommu->index);
4586         return 0;
4587 }
4588 
4589 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4590 {
4591         unsigned long flags;
4592         struct amd_iommu *iommu;
4593         struct irq_remap_table *table;
4594         struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4595         int devid = ir_data->irq_2_irte.devid;
4596         struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4597         struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4598 
4599         if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4600             !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4601                 return 0;
4602 
4603         iommu = amd_iommu_rlookup_table[devid];
4604         if (!iommu)
4605                 return -ENODEV;
4606 
4607         table = get_irq_table(devid);
4608         if (!table)
4609                 return -ENODEV;
4610 
4611         raw_spin_lock_irqsave(&table->lock, flags);
4612 
4613         if (ref->lo.fields_vapic.guest_mode) {
4614                 if (cpu >= 0) {
4615                         ref->lo.fields_vapic.destination =
4616                                                 APICID_TO_IRTE_DEST_LO(cpu);
4617                         ref->hi.fields.destination =
4618                                                 APICID_TO_IRTE_DEST_HI(cpu);
4619                 }
4620                 ref->lo.fields_vapic.is_run = is_run;
4621                 barrier();
4622         }
4623 
4624         raw_spin_unlock_irqrestore(&table->lock, flags);
4625 
4626         iommu_flush_irt(iommu, devid);
4627         iommu_completion_wait(iommu);
4628         return 0;
4629 }
4630 EXPORT_SYMBOL(amd_iommu_update_ga);
4631 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/iommu/amd_iommu.c

DEFINITIONS
