1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4
5 #ifndef MSM_IOMMU_H
6 #define MSM_IOMMU_H
7
8 #include <linux/interrupt.h>
9 #include <linux/iommu.h>
10 #include <linux/clk.h>
11
12 /* Sharability attributes of MSM IOMMU mappings */
13 #define MSM_IOMMU_ATTR_NON_SH 0x0
14 #define MSM_IOMMU_ATTR_SH 0x4
15
16 /* Cacheability attributes of MSM IOMMU mappings */
17 #define MSM_IOMMU_ATTR_NONCACHED 0x0
18 #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
19 #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
20 #define MSM_IOMMU_ATTR_CACHED_WT 0x3
21
22 /* Mask for the cache policy attribute */
23 #define MSM_IOMMU_CP_MASK 0x03
24
25 /* Maximum number of Machine IDs that we are allowing to be mapped to the same
26 * context bank. The number of MIDs mapped to the same CB does not affect
27 * performance, but there is a practical limit on how many distinct MIDs may
28 * be present. These mappings are typically determined at design time and are
29 * not expected to change at run time.
30 */
31 #define MAX_NUM_MIDS 32
32
33 /* Maximum number of context banks that can be present in IOMMU */
34 #define IOMMU_MAX_CBS 128
35
36 /**
37 * struct msm_iommu_dev - a single IOMMU hardware instance
38 * ncb Number of context banks present on this IOMMU HW instance
39 * dev: IOMMU device
40 * irq: Interrupt number
41 * clk: The bus clock for this IOMMU hardware instance
42 * pclk: The clock for the IOMMU bus interconnect
43 * dev_node: list head in qcom_iommu_device_list
44 * dom_node: list head for domain
45 * ctx_list: list of 'struct msm_iommu_ctx_dev'
46 * context_map: Bitmap to track allocated context banks
47 */
48 struct msm_iommu_dev {
49 void __iomem *base;
50 int ncb;
51 struct device *dev;
52 int irq;
53 struct clk *clk;
54 struct clk *pclk;
55 struct list_head dev_node;
56 struct list_head dom_node;
57 struct list_head ctx_list;
58 DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
59
60 struct iommu_device iommu;
61 };
62
63 /**
64 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
65 * of_node node ptr of client device
66 * num Index of this context bank within the hardware
67 * mids List of Machine IDs that are to be mapped into this context
68 * bank, terminated by -1. The MID is a set of signals on the
69 * AXI bus that identifies the function associated with a specific
70 * memory request. (See ARM spec).
71 * num_mids Total number of mids
72 * node list head in ctx_list
73 */
74 struct msm_iommu_ctx_dev {
75 struct device_node *of_node;
76 int num;
77 int mids[MAX_NUM_MIDS];
78 int num_mids;
79 struct list_head list;
80 };
81
82 /*
83 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
84 * interrupt is not supported in the API yet, but this will print an error
85 * message and dump useful IOMMU registers.
86 */
87 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
88
89 #endif