1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * linux/drivers/usb/gadget/pxa27x_udc.h
4 * Intel PXA27x on-chip full speed USB device controller
5 *
6 * Inspired by original driver by Frank Becker, David Brownell, and others.
7 * Copyright (C) 2008 Robert Jarzmik
8 */
9
10 #ifndef __LINUX_USB_GADGET_PXA27X_H
11 #define __LINUX_USB_GADGET_PXA27X_H
12
13 #include <linux/types.h>
14 #include <linux/spinlock.h>
15 #include <linux/io.h>
16 #include <linux/usb/otg.h>
17
18 /*
19 * Register definitions
20 */
21 /* Offsets */
22 #define UDCCR 0x0000 /* UDC Control Register */
23 #define UDCICR0 0x0004 /* UDC Interrupt Control Register0 */
24 #define UDCICR1 0x0008 /* UDC Interrupt Control Register1 */
25 #define UDCISR0 0x000C /* UDC Interrupt Status Register 0 */
26 #define UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */
27 #define UDCFNR 0x0014 /* UDC Frame Number Register */
28 #define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */
29 #define UP2OCR 0x0020 /* USB Port 2 Output Control register */
30 #define UP3OCR 0x0024 /* USB Port 3 Output Control register */
31 #define UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */
32 #define UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */
33 #define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */
34 #define UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */
35
36 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
37 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
38 Protocol Port Support */
39 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
40 Support */
41 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
42 Enable */
43 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
44 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
45 #define UDCCR_ACN_S 11
46 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
47 #define UDCCR_AIN_S 8
48 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
49 Setting Number */
50 #define UDCCR_AAISN_S 5
51 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
52 Configuration */
53 #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
54 Error */
55 #define UDCCR_UDR (1 << 2) /* UDC Resume */
56 #define UDCCR_UDA (1 << 1) /* UDC Active */
57 #define UDCCR_UDE (1 << 0) /* UDC Enable */
58
59 #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
60 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
61 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
62 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
63 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
64 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
65 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
66 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
67 #define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
68
69 #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
70 #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
71 #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
72 #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
73 #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
74 #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
75 #define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
76
77 #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
78 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt
79 Rising Edge Interrupt Enable */
80 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt
81 Falling Edge Interrupt Enable */
82 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
83 Interrupt Enable */
84 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
85 Interrupt Enable */
86 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
87 Interrupt Enable */
88 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
89 Interrupt Enable */
90 #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
91 Interrupt Enable */
92 #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
93 Interrupt Enable */
94 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
95 Edge Interrupt Enable */
96 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
97 Edge Interrupt Enable */
98 #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
99 Interrupt Enable */
100 #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
101 Interrupt Enable */
102
103 /* Host Port 2 field bits */
104 #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
105 #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
106 /* Transceiver enablers */
107 #define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */
108 #define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */
109 #define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */
110 #define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */
111 #define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */
112 #define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */
113 #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
114 #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
115 #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
116 #define UP2OCR_HXS (1 << 16) /* Transceiver Output Select */
117 #define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */
118 #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
119
120 #define UDCCSR0_ACM (1 << 9) /* Ack Control Mode */
121 #define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */
122 #define UDCCSR0_SA (1 << 7) /* Setup Active */
123 #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
124 #define UDCCSR0_FST (1 << 5) /* Force Stall */
125 #define UDCCSR0_SST (1 << 4) /* Sent Stall */
126 #define UDCCSR0_DME (1 << 3) /* DMA Enable */
127 #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
128 #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
129 #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
130
131 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */
132 #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
133 #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
134 #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
135 #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
136 #define UDCCSR_FST (1 << 5) /* Force STALL */
137 #define UDCCSR_SST (1 << 4) /* Sent STALL */
138 #define UDCCSR_DME (1 << 3) /* DMA Enable */
139 #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
140 #define UDCCSR_PC (1 << 1) /* Packet Complete */
141 #define UDCCSR_FS (1 << 0) /* FIFO needs service */
142
143 #define UDCCONR_CN (0x03 << 25) /* Configuration Number */
144 #define UDCCONR_CN_S 25
145 #define UDCCONR_IN (0x07 << 22) /* Interface Number */
146 #define UDCCONR_IN_S 22
147 #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
148 #define UDCCONR_AISN_S 19
149 #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
150 #define UDCCONR_EN_S 15
151 #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
152 #define UDCCONR_ET_S 13
153 #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
154 #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
155 #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
156 #define UDCCONR_ET_NU (0x00 << 13) /* Not used */
157 #define UDCCONR_ED (1 << 12) /* Endpoint Direction */
158 #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
159 #define UDCCONR_MPS_S 2
160 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
161 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */
162
163 #define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE)
164 #define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST)
165 #define UDC_FNR_MASK (0x7ff)
166 #define UDC_BCR_MASK (0x3ff)
167
168 /*
169 * UDCCR = UDC Endpoint Configuration Registers
170 * UDCCSR = UDC Control/Status Register for this EP
171 * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo)
172 * UDCDR = UDC Endpoint Data Register (the fifo)
173 */
174 #define ofs_UDCCR(ep) (UDCCRn(ep->idx))
175 #define ofs_UDCCSR(ep) (UDCCSRn(ep->idx))
176 #define ofs_UDCBCR(ep) (UDCBCRn(ep->idx))
177 #define ofs_UDCDR(ep) (UDCDRn(ep->idx))
178
179 /* Register access macros */
180 #define udc_ep_readl(ep, reg) \
181 __raw_readl((ep)->dev->regs + ofs_##reg(ep))
182 #define udc_ep_writel(ep, reg, value) \
183 __raw_writel((value), ep->dev->regs + ofs_##reg(ep))
184 #define udc_ep_readb(ep, reg) \
185 __raw_readb((ep)->dev->regs + ofs_##reg(ep))
186 #define udc_ep_writeb(ep, reg, value) \
187 __raw_writeb((value), ep->dev->regs + ofs_##reg(ep))
188 #define udc_readl(dev, reg) \
189 __raw_readl((dev)->regs + (reg))
190 #define udc_writel(udc, reg, value) \
191 __raw_writel((value), (udc)->regs + (reg))
192
193 #define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME)
194 #define UDCCISR0_EP_MASK ~0
195 #define UDCCISR1_EP_MASK 0xffff
196 #define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)
197
198 #define EPIDX(ep) (ep->idx)
199 #define EPADDR(ep) (ep->addr)
200 #define EPXFERTYPE(ep) (ep->type)
201 #define EPNAME(ep) (ep->name)
202 #define is_ep0(ep) (!ep->idx)
203 #define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)
204
205 /*
206 * Endpoint definitions
207 *
208 * Once enabled, pxa endpoint configuration is freezed, and cannot change
209 * unless a reset happens or the udc is disabled.
210 * Therefore, we must define all pxa potential endpoint definitions needed for
211 * all gadget and set them up before the udc is enabled.
212 *
213 * As the architecture chosen is fully static, meaning the pxa endpoint
214 * configurations are set up once and for all, we must provide a way to match
215 * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget
216 * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt)
217 * criteria, while the pxa architecture requires that.
218 *
219 * The solution is to define several pxa endpoints matching one usb_ep. Ex:
220 * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when
221 * the udc talks on (config=3, interface=0, alt=0)
222 * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when
223 * the udc talks on (config=3, interface=0, alt=1)
224 * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when
225 * the udc talks on (config=2, interface=0, alt=0)
226 *
227 * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...)
228 */
229
230 /*
231 * Endpoint definition helpers
232 */
233 #define USB_EP_DEF(addr, bname, dir, type, maxpkt, ctype, cdir) \
234 { .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, \
235 .caps = USB_EP_CAPS(ctype, cdir), }, \
236 .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \
237 .bmAttributes = USB_ENDPOINT_XFER_ ## type, \
238 .wMaxPacketSize = maxpkt, }, \
239 .dev = &memory \
240 }
241 #define USB_EP_BULK(addr, bname, dir, cdir) \
242 USB_EP_DEF(addr, bname, dir, BULK, BULK_FIFO_SIZE, \
243 USB_EP_CAPS_TYPE_BULK, cdir)
244 #define USB_EP_ISO(addr, bname, dir, cdir) \
245 USB_EP_DEF(addr, bname, dir, ISOC, ISO_FIFO_SIZE, \
246 USB_EP_CAPS_TYPE_ISO, cdir)
247 #define USB_EP_INT(addr, bname, dir, cdir) \
248 USB_EP_DEF(addr, bname, dir, INT, INT_FIFO_SIZE, \
249 USB_EP_CAPS_TYPE_INT, cdir)
250 #define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1, \
251 USB_EP_CAPS_DIR_IN)
252 #define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0, \
253 USB_EP_CAPS_DIR_OUT)
254 #define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1, \
255 USB_EP_CAPS_DIR_IN)
256 #define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0, \
257 USB_EP_CAPS_DIR_OUT)
258 #define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1, \
259 USB_EP_CAPS_DIR_IN)
260 #define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, CONTROL, EP0_FIFO_SIZE, \
261 USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)
262
263 #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \
264 { \
265 .dev = &memory, \
266 .name = "ep" #_idx, \
267 .idx = _idx, .enabled = 0, \
268 .dir_in = dir, .addr = _addr, \
269 .config = _config, .interface = iface, .alternate = altset, \
270 .type = _type, .fifo_size = maxpkt, \
271 }
272 #define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \
273 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
274 config, iface, alt)
275 #define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \
276 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
277 config, iface, alt)
278 #define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \
279 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
280 config, iface, alt)
281 #define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a)
282 #define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a)
283 #define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a)
284 #define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a)
285 #define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a)
286 #define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)
287
288 struct pxa27x_udc;
289
290 struct stats {
291 unsigned long in_ops;
292 unsigned long out_ops;
293 unsigned long in_bytes;
294 unsigned long out_bytes;
295 unsigned long irqs;
296 };
297
298 /**
299 * struct udc_usb_ep - container of each usb_ep structure
300 * @usb_ep: usb endpoint
301 * @desc: usb descriptor, especially type and address
302 * @dev: udc managing this endpoint
303 * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call)
304 */
305 struct udc_usb_ep {
306 struct usb_ep usb_ep;
307 struct usb_endpoint_descriptor desc;
308 struct pxa_udc *dev;
309 struct pxa_ep *pxa_ep;
310 };
311
312 /**
313 * struct pxa_ep - pxa endpoint
314 * @dev: udc device
315 * @queue: requests queue
316 * @lock: lock to pxa_ep data (queues and stats)
317 * @enabled: true when endpoint enabled (not stopped by gadget layer)
318 * @in_handle_ep: number of recursions of handle_ep() function
319 * Prevents deadlocks or infinite recursions of types :
320 * irq->handle_ep()->req_done()->req.complete()->pxa_ep_queue()->handle_ep()
321 * or
322 * pxa_ep_queue()->handle_ep()->req_done()->req.complete()->pxa_ep_queue()
323 * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX)
324 * @name: endpoint name (for trace/debug purpose)
325 * @dir_in: 1 if IN endpoint, 0 if OUT endpoint
326 * @addr: usb endpoint number
327 * @config: configuration in which this endpoint is active
328 * @interface: interface in which this endpoint is active
329 * @alternate: altsetting in which this endpoitn is active
330 * @fifo_size: max packet size in the endpoint fifo
331 * @type: endpoint type (bulk, iso, int, ...)
332 * @udccsr_value: save register of UDCCSR0 for suspend/resume
333 * @udccr_value: save register of UDCCR for suspend/resume
334 * @stats: endpoint statistics
335 *
336 * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned
337 * (cares about config/interface/altsetting, thus placing needless limits on
338 * device capability) and full of implementation bugs forcing it to be set up
339 * for use more or less like a pxa255.
340 *
341 * As we define the pxa_ep statically, we must guess all needed pxa_ep for all
342 * gadget which may work with this udc driver.
343 */
344 struct pxa_ep {
345 struct pxa_udc *dev;
346
347 struct list_head queue;
348 spinlock_t lock; /* Protects this structure */
349 /* (queues, stats) */
350 unsigned enabled:1;
351 unsigned in_handle_ep:1;
352
353 unsigned idx:5;
354 char *name;
355
356 /*
357 * Specific pxa endpoint data, needed for hardware initialization
358 */
359 unsigned dir_in:1;
360 unsigned addr:4;
361 unsigned config:2;
362 unsigned interface:3;
363 unsigned alternate:3;
364 unsigned fifo_size;
365 unsigned type;
366
367 #ifdef CONFIG_PM
368 u32 udccsr_value;
369 u32 udccr_value;
370 #endif
371 struct stats stats;
372 };
373
374 /**
375 * struct pxa27x_request - container of each usb_request structure
376 * @req: usb request
377 * @udc_usb_ep: usb endpoint the request was submitted on
378 * @in_use: sanity check if request already queued on an pxa_ep
379 * @queue: linked list of requests, linked on pxa_ep->queue
380 */
381 struct pxa27x_request {
382 struct usb_request req;
383 struct udc_usb_ep *udc_usb_ep;
384 unsigned in_use:1;
385 struct list_head queue;
386 };
387
388 enum ep0_state {
389 WAIT_FOR_SETUP,
390 SETUP_STAGE,
391 IN_DATA_STAGE,
392 OUT_DATA_STAGE,
393 IN_STATUS_STAGE,
394 OUT_STATUS_STAGE,
395 STALL,
396 WAIT_ACK_SET_CONF_INTERF
397 };
398
399 static char *ep0_state_name[] = {
400 "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE",
401 "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL",
402 "WAIT_ACK_SET_CONF_INTERF"
403 };
404 #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
405
406 #define EP0_FIFO_SIZE 16U
407 #define BULK_FIFO_SIZE 64U
408 #define ISO_FIFO_SIZE 256U
409 #define INT_FIFO_SIZE 16U
410
411 struct udc_stats {
412 unsigned long irqs_reset;
413 unsigned long irqs_suspend;
414 unsigned long irqs_resume;
415 unsigned long irqs_reconfig;
416 };
417
418 #define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */
419 #define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */
420
421 /**
422 * struct pxa_udc - udc structure
423 * @regs: mapped IO space
424 * @irq: udc irq
425 * @clk: udc clock
426 * @usb_gadget: udc gadget structure
427 * @driver: bound gadget (zero, g_ether, g_mass_storage, ...)
428 * @dev: device
429 * @udc_command: machine specific function to activate D+ pullup
430 * @gpiod: gpio descriptor of gpio for D+ pullup (or NULL if none)
431 * @transceiver: external transceiver to handle vbus sense and D+ pullup
432 * @ep0state: control endpoint state machine state
433 * @stats: statistics on udc usage
434 * @udc_usb_ep: array of usb endpoints offered by the gadget
435 * @pxa_ep: array of pxa available endpoints
436 * @enabled: UDC was enabled by a previous udc_enable()
437 * @pullup_on: if pullup resistor connected to D+ pin
438 * @pullup_resume: if pullup resistor should be connected to D+ pin on resume
439 * @config: UDC active configuration
440 * @last_interface: UDC interface of the last SET_INTERFACE host request
441 * @last_alternate: UDC altsetting of the last SET_INTERFACE host request
442 * @udccsr0: save of udccsr0 in case of suspend
443 * @debugfs_root: root entry of debug filesystem
444 * @debugfs_state: debugfs entry for "udcstate"
445 * @debugfs_queues: debugfs entry for "queues"
446 * @debugfs_eps: debugfs entry for "epstate"
447 */
448 struct pxa_udc {
449 void __iomem *regs;
450 int irq;
451 struct clk *clk;
452
453 struct usb_gadget gadget;
454 struct usb_gadget_driver *driver;
455 struct device *dev;
456 void (*udc_command)(int);
457 struct gpio_desc *gpiod;
458 struct usb_phy *transceiver;
459
460 enum ep0_state ep0state;
461 struct udc_stats stats;
462
463 struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS];
464 struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS];
465
466 unsigned enabled:1;
467 unsigned pullup_on:1;
468 unsigned pullup_resume:1;
469 unsigned vbus_sensed:1;
470 unsigned config:2;
471 unsigned last_interface:3;
472 unsigned last_alternate:3;
473
474 #ifdef CONFIG_PM
475 unsigned udccsr0;
476 #endif
477 #ifdef CONFIG_USB_GADGET_DEBUG_FS
478 struct dentry *debugfs_root;
479 #endif
480 };
481 #define to_pxa(g) (container_of((g), struct pxa_udc, gadget))
482
483 static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
484 {
485 return container_of(gadget, struct pxa_udc, gadget);
486 }
487
488 /*
489 * Debugging/message support
490 */
491 #define ep_dbg(ep, fmt, arg...) \
492 dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
493 #define ep_vdbg(ep, fmt, arg...) \
494 dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
495 #define ep_err(ep, fmt, arg...) \
496 dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
497 #define ep_info(ep, fmt, arg...) \
498 dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
499 #define ep_warn(ep, fmt, arg...) \
500 dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
501
502 #endif /* __LINUX_USB_GADGET_PXA27X_H */