This source file includes following definitions.
- net2272_reg_addr
- net2272_write
- net2272_read
- net2272_ep_write
- net2272_ep_read
- allow_status
- set_halt
- clear_halt
- set_fifo_bytecount
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9 #ifndef __NET2272_H__
10 #define __NET2272_H__
11
12
13 #define REGADDRPTR 0x00
14 #define REGDATA 0x01
15 #define IRQSTAT0 0x02
16 #define ENDPOINT_0_INTERRUPT 0
17 #define ENDPOINT_A_INTERRUPT 1
18 #define ENDPOINT_B_INTERRUPT 2
19 #define ENDPOINT_C_INTERRUPT 3
20 #define VIRTUALIZED_ENDPOINT_INTERRUPT 4
21 #define SETUP_PACKET_INTERRUPT 5
22 #define DMA_DONE_INTERRUPT 6
23 #define SOF_INTERRUPT 7
24 #define IRQSTAT1 0x03
25 #define CONTROL_STATUS_INTERRUPT 1
26 #define VBUS_INTERRUPT 2
27 #define SUSPEND_REQUEST_INTERRUPT 3
28 #define SUSPEND_REQUEST_CHANGE_INTERRUPT 4
29 #define RESUME_INTERRUPT 5
30 #define ROOT_PORT_RESET_INTERRUPT 6
31 #define RESET_STATUS 7
32 #define PAGESEL 0x04
33 #define DMAREQ 0x1c
34 #define DMA_ENDPOINT_SELECT 0
35 #define DREQ_POLARITY 1
36 #define DACK_POLARITY 2
37 #define EOT_POLARITY 3
38 #define DMA_CONTROL_DACK 4
39 #define DMA_REQUEST_ENABLE 5
40 #define DMA_REQUEST 6
41 #define DMA_BUFFER_VALID 7
42 #define SCRATCH 0x1d
43 #define IRQENB0 0x20
44 #define ENDPOINT_0_INTERRUPT_ENABLE 0
45 #define ENDPOINT_A_INTERRUPT_ENABLE 1
46 #define ENDPOINT_B_INTERRUPT_ENABLE 2
47 #define ENDPOINT_C_INTERRUPT_ENABLE 3
48 #define VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE 4
49 #define SETUP_PACKET_INTERRUPT_ENABLE 5
50 #define DMA_DONE_INTERRUPT_ENABLE 6
51 #define SOF_INTERRUPT_ENABLE 7
52 #define IRQENB1 0x21
53 #define VBUS_INTERRUPT_ENABLE 2
54 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
55 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 4
56 #define RESUME_INTERRUPT_ENABLE 5
57 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 6
58 #define LOCCTL 0x22
59 #define DATA_WIDTH 0
60 #define LOCAL_CLOCK_OUTPUT 1
61 #define LOCAL_CLOCK_OUTPUT_OFF 0
62 #define LOCAL_CLOCK_OUTPUT_3_75MHZ 1
63 #define LOCAL_CLOCK_OUTPUT_7_5MHZ 2
64 #define LOCAL_CLOCK_OUTPUT_15MHZ 3
65 #define LOCAL_CLOCK_OUTPUT_30MHZ 4
66 #define LOCAL_CLOCK_OUTPUT_60MHZ 5
67 #define DMA_SPLIT_BUS_MODE 4
68 #define BYTE_SWAP 5
69 #define BUFFER_CONFIGURATION 6
70 #define BUFFER_CONFIGURATION_EPA512_EPB512 0
71 #define BUFFER_CONFIGURATION_EPA1024_EPB512 1
72 #define BUFFER_CONFIGURATION_EPA1024_EPB1024 2
73 #define BUFFER_CONFIGURATION_EPA1024DB 3
74 #define CHIPREV_LEGACY 0x23
75 #define NET2270_LEGACY_REV 0x40
76 #define LOCCTL1 0x24
77 #define DMA_MODE 0
78 #define SLOW_DREQ 0
79 #define FAST_DREQ 1
80 #define BURST_MODE 2
81 #define DMA_DACK_ENABLE 2
82 #define CHIPREV_2272 0x25
83 #define CHIPREV_NET2272_R1 0x10
84 #define CHIPREV_NET2272_R1A 0x11
85
86 #define USBCTL0 0x18
87 #define IO_WAKEUP_ENABLE 1
88 #define USB_DETECT_ENABLE 3
89 #define USB_ROOT_PORT_WAKEUP_ENABLE 5
90 #define USBCTL1 0x19
91 #define VBUS_PIN 0
92 #define USB_FULL_SPEED 1
93 #define USB_HIGH_SPEED 2
94 #define GENERATE_RESUME 3
95 #define VIRTUAL_ENDPOINT_ENABLE 4
96 #define FRAME0 0x1a
97 #define FRAME1 0x1b
98 #define OURADDR 0x30
99 #define FORCE_IMMEDIATE 7
100 #define USBDIAG 0x31
101 #define FORCE_TRANSMIT_CRC_ERROR 0
102 #define PREVENT_TRANSMIT_BIT_STUFF 1
103 #define FORCE_RECEIVE_ERROR 2
104 #define FAST_TIMES 4
105 #define USBTEST 0x32
106 #define TEST_MODE_SELECT 0
107 #define NORMAL_OPERATION 0
108 #define TEST_J 1
109 #define TEST_K 2
110 #define TEST_SE0_NAK 3
111 #define TEST_PACKET 4
112 #define TEST_FORCE_ENABLE 5
113 #define XCVRDIAG 0x33
114 #define FORCE_FULL_SPEED 2
115 #define FORCE_HIGH_SPEED 3
116 #define OPMODE 4
117 #define NORMAL_OPERATION 0
118 #define NON_DRIVING 1
119 #define DISABLE_BITSTUFF_AND_NRZI_ENCODE 2
120 #define LINESTATE 6
121 #define SE0_STATE 0
122 #define J_STATE 1
123 #define K_STATE 2
124 #define SE1_STATE 3
125 #define VIRTOUT0 0x34
126 #define VIRTOUT1 0x35
127 #define VIRTIN0 0x36
128 #define VIRTIN1 0x37
129 #define SETUP0 0x40
130 #define SETUP1 0x41
131 #define SETUP2 0x42
132 #define SETUP3 0x43
133 #define SETUP4 0x44
134 #define SETUP5 0x45
135 #define SETUP6 0x46
136 #define SETUP7 0x47
137
138 #define EP_DATA 0x05
139 #define EP_STAT0 0x06
140 #define DATA_IN_TOKEN_INTERRUPT 0
141 #define DATA_OUT_TOKEN_INTERRUPT 1
142 #define DATA_PACKET_TRANSMITTED_INTERRUPT 2
143 #define DATA_PACKET_RECEIVED_INTERRUPT 3
144 #define SHORT_PACKET_TRANSFERRED_INTERRUPT 4
145 #define NAK_OUT_PACKETS 5
146 #define BUFFER_EMPTY 6
147 #define BUFFER_FULL 7
148 #define EP_STAT1 0x07
149 #define TIMEOUT 0
150 #define USB_OUT_ACK_SENT 1
151 #define USB_OUT_NAK_SENT 2
152 #define USB_IN_ACK_RCVD 3
153 #define USB_IN_NAK_SENT 4
154 #define USB_STALL_SENT 5
155 #define LOCAL_OUT_ZLP 6
156 #define BUFFER_FLUSH 7
157 #define EP_TRANSFER0 0x08
158 #define EP_TRANSFER1 0x09
159 #define EP_TRANSFER2 0x0a
160 #define EP_IRQENB 0x0b
161 #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0
162 #define DATA_OUT_TOKEN_INTERRUPT_ENABLE 1
163 #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2
164 #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3
165 #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 4
166 #define EP_AVAIL0 0x0c
167 #define EP_AVAIL1 0x0d
168 #define EP_RSPCLR 0x0e
169 #define EP_RSPSET 0x0f
170 #define ENDPOINT_HALT 0
171 #define ENDPOINT_TOGGLE 1
172 #define NAK_OUT_PACKETS_MODE 2
173 #define CONTROL_STATUS_PHASE_HANDSHAKE 3
174 #define INTERRUPT_MODE 4
175 #define AUTOVALIDATE 5
176 #define HIDE_STATUS_PHASE 6
177 #define ALT_NAK_OUT_PACKETS 7
178 #define EP_MAXPKT0 0x28
179 #define EP_MAXPKT1 0x29
180 #define ADDITIONAL_TRANSACTION_OPPORTUNITIES 3
181 #define NONE_ADDITIONAL_TRANSACTION 0
182 #define ONE_ADDITIONAL_TRANSACTION 1
183 #define TWO_ADDITIONAL_TRANSACTION 2
184 #define EP_CFG 0x2a
185 #define ENDPOINT_NUMBER 0
186 #define ENDPOINT_DIRECTION 4
187 #define ENDPOINT_TYPE 5
188 #define ENDPOINT_ENABLE 7
189 #define EP_HBW 0x2b
190 #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 0
191 #define DATA0_PID 0
192 #define DATA1_PID 1
193 #define DATA2_PID 2
194 #define MDATA_PID 3
195 #define EP_BUFF_STATES 0x2c
196 #define BUFFER_A_STATE 0
197 #define BUFFER_B_STATE 2
198 #define BUFF_FREE 0
199 #define BUFF_VALID 1
200 #define BUFF_LCL 2
201 #define BUFF_USB 3
202
203
204
205 #define PCI_DEVICE_ID_RDK1 0x9054
206
207
208 #define RDK_EPLD_IO_REGISTER1 0x00000000
209 #define RDK_EPLD_USB_RESET 0
210 #define RDK_EPLD_USB_POWERDOWN 1
211 #define RDK_EPLD_USB_WAKEUP 2
212 #define RDK_EPLD_USB_EOT 3
213 #define RDK_EPLD_DPPULL 4
214 #define RDK_EPLD_IO_REGISTER2 0x00000004
215 #define RDK_EPLD_BUSWIDTH 0
216 #define RDK_EPLD_USER 2
217 #define RDK_EPLD_RESET_INTERRUPT_ENABLE 3
218 #define RDK_EPLD_DMA_TIMEOUT_ENABLE 4
219 #define RDK_EPLD_STATUS_REGISTER 0x00000008
220 #define RDK_EPLD_USB_LRESET 0
221 #define RDK_EPLD_REVISION_REGISTER 0x0000000c
222
223
224 #define INTCSR 0x68
225 #define PCI_INTERRUPT_ENABLE 8
226 #define LOCAL_INTERRUPT_INPUT_ENABLE 11
227 #define LOCAL_INPUT_INTERRUPT_ACTIVE 15
228 #define LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE 18
229 #define LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE 19
230 #define DMA_CHANNEL_0_INTERRUPT_ACTIVE 21
231 #define DMA_CHANNEL_1_INTERRUPT_ACTIVE 22
232 #define CNTRL 0x6C
233 #define RELOAD_CONFIGURATION_REGISTERS 29
234 #define PCI_ADAPTER_SOFTWARE_RESET 30
235 #define DMAMODE0 0x80
236 #define LOCAL_BUS_WIDTH 0
237 #define INTERNAL_WAIT_STATES 2
238 #define TA_READY_INPUT_ENABLE 6
239 #define LOCAL_BURST_ENABLE 8
240 #define SCATTER_GATHER_MODE 9
241 #define DONE_INTERRUPT_ENABLE 10
242 #define LOCAL_ADDRESSING_MODE 11
243 #define DEMAND_MODE 12
244 #define DMA_EOT_ENABLE 14
245 #define FAST_SLOW_TERMINATE_MODE_SELECT 15
246 #define DMA_CHANNEL_INTERRUPT_SELECT 17
247 #define DMAPADR0 0x84
248 #define DMALADR0 0x88
249 #define DMASIZ0 0x8c
250 #define DMADPR0 0x90
251 #define DESCRIPTOR_LOCATION 0
252 #define END_OF_CHAIN 1
253 #define INTERRUPT_AFTER_TERMINAL_COUNT 2
254 #define DIRECTION_OF_TRANSFER 3
255 #define DMACSR0 0xa8
256 #define CHANNEL_ENABLE 0
257 #define CHANNEL_START 1
258 #define CHANNEL_ABORT 2
259 #define CHANNEL_CLEAR_INTERRUPT 3
260 #define CHANNEL_DONE 4
261 #define DMATHR 0xb0
262 #define LBRD1 0xf8
263 #define MEMORY_SPACE_LOCAL_BUS_WIDTH 0
264 #define W8_BIT 0
265 #define W16_BIT 1
266
267
268 #define LOCAL_INTERRUPT_TEST \
269 ((1 << LOCAL_INPUT_INTERRUPT_ACTIVE) | \
270 (1 << LOCAL_INTERRUPT_INPUT_ENABLE))
271
272 #define DMA_CHANNEL_0_TEST \
273 ((1 << DMA_CHANNEL_0_INTERRUPT_ACTIVE) | \
274 (1 << LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE))
275
276 #define DMA_CHANNEL_1_TEST \
277 ((1 << DMA_CHANNEL_1_INTERRUPT_ACTIVE) | \
278 (1 << LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE))
279
280
281 #define RDK_EPLD_IO_REGISTER1 0x00000000
282 #define RDK_EPLD_USB_RESET 0
283 #define RDK_EPLD_USB_POWERDOWN 1
284 #define RDK_EPLD_USB_WAKEUP 2
285 #define RDK_EPLD_USB_EOT 3
286 #define RDK_EPLD_DPPULL 4
287 #define RDK_EPLD_IO_REGISTER2 0x00000004
288 #define RDK_EPLD_BUSWIDTH 0
289 #define RDK_EPLD_USER 2
290 #define RDK_EPLD_RESET_INTERRUPT_ENABLE 3
291 #define RDK_EPLD_DMA_TIMEOUT_ENABLE 4
292 #define RDK_EPLD_STATUS_REGISTER 0x00000008
293 #define RDK_EPLD_USB_LRESET 0
294 #define RDK_EPLD_REVISION_REGISTER 0x0000000c
295
296 #define EPLD_IO_CONTROL_REGISTER 0x400
297 #define NET2272_RESET 0
298 #define BUSWIDTH 1
299 #define MPX_MODE 3
300 #define USER 4
301 #define DMA_TIMEOUT_ENABLE 5
302 #define DMA_CTL_DACK 6
303 #define EPLD_DMA_ENABLE 7
304 #define EPLD_DMA_CONTROL_REGISTER 0x800
305 #define SPLIT_DMA_MODE 0
306 #define SPLIT_DMA_DIRECTION 1
307 #define SPLIT_DMA_ENABLE 2
308 #define SPLIT_DMA_INTERRUPT_ENABLE 3
309 #define SPLIT_DMA_INTERRUPT 4
310 #define EPLD_DMA_MODE 5
311 #define EPLD_DMA_CONTROLLER_ENABLE 7
312 #define SPLIT_DMA_ADDRESS_LOW 0xc00
313 #define SPLIT_DMA_ADDRESS_HIGH 0x1000
314 #define SPLIT_DMA_BYTE_COUNT_LOW 0x1400
315 #define SPLIT_DMA_BYTE_COUNT_HIGH 0x1800
316 #define EPLD_REVISION_REGISTER 0x1c00
317 #define SPLIT_DMA_RAM 0x4000
318 #define DMA_RAM_SIZE 0x1000
319
320
321
322 #define PCI_DEVICE_ID_RDK2 0x3272
323
324
325
326
327
328 #define RDK2_IRQENB 0x00
329 #define RDK2_IRQSTAT 0x04
330 #define PB7 23
331 #define PB6 22
332 #define PB5 21
333 #define PB4 20
334 #define PB3 19
335 #define PB2 18
336 #define PB1 17
337 #define PB0 16
338 #define GP3 23
339 #define GP2 23
340 #define GP1 23
341 #define GP0 23
342 #define DMA_RETRY_ABORT 6
343 #define DMA_PAUSE_DONE 5
344 #define DMA_ABORT_DONE 4
345 #define DMA_OUT_FIFO_TRANSFER_DONE 3
346 #define DMA_LOCAL_DONE 2
347 #define DMA_PCI_DONE 1
348 #define NET2272_PCI_IRQ 0
349
350 #define RDK2_LOCCTLRDK 0x08
351 #define CHIP_RESET 3
352 #define SPLIT_DMA 2
353 #define MULTIPLEX_MODE 1
354 #define BUS_WIDTH 0
355
356 #define RDK2_GPIOCTL 0x10
357 #define GP3_OUT_ENABLE 7
358 #define GP2_OUT_ENABLE 6
359 #define GP1_OUT_ENABLE 5
360 #define GP0_OUT_ENABLE 4
361 #define GP3_DATA 3
362 #define GP2_DATA 2
363 #define GP1_DATA 1
364 #define GP0_DATA 0
365
366 #define RDK2_LEDSW 0x14
367 #define LED3 27
368 #define LED2 26
369 #define LED1 25
370 #define LED0 24
371 #define PBUTTON 16
372 #define DIPSW 0
373
374 #define RDK2_DIAG 0x18
375 #define RDK2_FAST_TIMES 2
376 #define FORCE_PCI_SERR 1
377 #define FORCE_PCI_INT 0
378 #define RDK2_FPGAREV 0x1C
379
380
381 #define RDK2_DMACTL 0x80
382 #define ADDR_HOLD 24
383 #define RETRY_COUNT 16
384 #define FIFO_THRESHOLD 11
385 #define MEM_WRITE_INVALIDATE 10
386 #define READ_MULTIPLE 9
387 #define READ_LINE 8
388 #define RDK2_DMA_MODE 6
389 #define CONTROL_DACK 5
390 #define EOT_ENABLE 4
391 #define EOT_POLARITY 3
392 #define DACK_POLARITY 2
393 #define DREQ_POLARITY 1
394 #define DMA_ENABLE 0
395
396 #define RDK2_DMASTAT 0x84
397 #define GATHER_COUNT 12
398 #define FIFO_COUNT 6
399 #define FIFO_FLUSH 5
400 #define FIFO_TRANSFER 4
401 #define PAUSE_DONE 3
402 #define ABORT_DONE 2
403 #define DMA_ABORT 1
404 #define DMA_START 0
405
406 #define RDK2_DMAPCICOUNT 0x88
407 #define DMA_DIRECTION 31
408 #define DMA_PCI_BYTE_COUNT 0
409
410 #define RDK2_DMALOCCOUNT 0x8C
411
412 #define RDK2_DMAADDR 0x90
413
414
415
416 #define REG_INDEXED_THRESHOLD (1 << 5)
417
418
419 struct net2272_ep {
420 struct usb_ep ep;
421 struct net2272 *dev;
422 unsigned long irqs;
423
424
425 struct list_head queue;
426 const struct usb_endpoint_descriptor *desc;
427 unsigned num:8,
428 fifo_size:12,
429 stopped:1,
430 wedged:1,
431 is_in:1,
432 is_iso:1,
433 dma:1,
434 not_empty:1;
435 };
436
437 struct net2272 {
438
439 struct usb_gadget gadget;
440 struct device *dev;
441 unsigned short dev_id;
442
443 spinlock_t lock;
444 struct net2272_ep ep[4];
445 struct usb_gadget_driver *driver;
446 unsigned protocol_stall:1,
447 softconnect:1,
448 wakeup:1,
449 dma_eot_polarity:1,
450 dma_dack_polarity:1,
451 dma_dreq_polarity:1,
452 dma_busy:1;
453 u16 chiprev;
454 u8 pagesel;
455
456 unsigned int irq;
457 unsigned short fifo_mode;
458
459 unsigned int base_shift;
460 u16 __iomem *base_addr;
461 union {
462 #ifdef CONFIG_USB_PCI
463 struct {
464 void __iomem *plx9054_base_addr;
465 void __iomem *epld_base_addr;
466 } rdk1;
467 struct {
468
469 void __iomem *fpga_base_addr;
470 } rdk2;
471 #endif
472 };
473 };
474
475 static void __iomem *
476 net2272_reg_addr(struct net2272 *dev, unsigned int reg)
477 {
478 return dev->base_addr + (reg << dev->base_shift);
479 }
480
481 static void
482 net2272_write(struct net2272 *dev, unsigned int reg, u8 value)
483 {
484 if (reg >= REG_INDEXED_THRESHOLD) {
485
486
487
488
489
490
491
492
493 writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
494 writeb(value, net2272_reg_addr(dev, REGDATA));
495
496 } else
497 writeb(value, net2272_reg_addr(dev, reg));
498 }
499
500 static u8
501 net2272_read(struct net2272 *dev, unsigned int reg)
502 {
503 u8 ret;
504
505 if (reg >= REG_INDEXED_THRESHOLD) {
506
507
508
509
510
511
512
513
514 writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
515 ret = readb(net2272_reg_addr(dev, REGDATA));
516
517 } else
518 ret = readb(net2272_reg_addr(dev, reg));
519
520 return ret;
521 }
522
523 static void
524 net2272_ep_write(struct net2272_ep *ep, unsigned int reg, u8 value)
525 {
526 struct net2272 *dev = ep->dev;
527
528 if (dev->pagesel != ep->num) {
529 net2272_write(dev, PAGESEL, ep->num);
530 dev->pagesel = ep->num;
531 }
532 net2272_write(dev, reg, value);
533 }
534
535 static u8
536 net2272_ep_read(struct net2272_ep *ep, unsigned int reg)
537 {
538 struct net2272 *dev = ep->dev;
539
540 if (dev->pagesel != ep->num) {
541 net2272_write(dev, PAGESEL, ep->num);
542 dev->pagesel = ep->num;
543 }
544 return net2272_read(dev, reg);
545 }
546
547 static void allow_status(struct net2272_ep *ep)
548 {
549
550 net2272_ep_write(ep, EP_RSPCLR,
551 (1 << CONTROL_STATUS_PHASE_HANDSHAKE) |
552 (1 << ALT_NAK_OUT_PACKETS) |
553 (1 << NAK_OUT_PACKETS_MODE));
554 ep->stopped = 1;
555 }
556
557 static void set_halt(struct net2272_ep *ep)
558 {
559
560 net2272_ep_write(ep, EP_RSPCLR, 1 << CONTROL_STATUS_PHASE_HANDSHAKE);
561 net2272_ep_write(ep, EP_RSPSET, 1 << ENDPOINT_HALT);
562 }
563
564 static void clear_halt(struct net2272_ep *ep)
565 {
566
567 net2272_ep_write(ep, EP_RSPCLR,
568 (1 << ENDPOINT_HALT) | (1 << ENDPOINT_TOGGLE));
569 }
570
571
572 static void set_fifo_bytecount(struct net2272_ep *ep, unsigned count)
573 {
574
575 net2272_ep_write(ep, EP_TRANSFER2, count >> 16);
576 net2272_ep_write(ep, EP_TRANSFER1, count >> 8);
577 net2272_ep_write(ep, EP_TRANSFER0, count);
578 }
579
580 struct net2272_request {
581 struct usb_request req;
582 struct list_head queue;
583 unsigned mapped:1,
584 valid:1;
585 };
586
587 #endif