root/drivers/usb/gadget/udc/m66592-udc.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. m66592_read
  2. m66592_read_fifo
  3. m66592_write
  4. m66592_mdfy
  5. m66592_write_fifo
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * M66592 UDC (USB gadget)
   4  *
   5  * Copyright (C) 2006-2007 Renesas Solutions Corp.
   6  *
   7  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
   8  */
   9 
  10 #ifndef __M66592_UDC_H__
  11 #define __M66592_UDC_H__
  12 
  13 #include <linux/clk.h>
  14 #include <linux/usb/m66592.h>
  15 
  16 #define M66592_SYSCFG           0x00
  17 #define M66592_XTAL             0xC000  /* b15-14: Crystal selection */
  18 #define   M66592_XTAL48          0x8000         /* 48MHz */
  19 #define   M66592_XTAL24          0x4000         /* 24MHz */
  20 #define   M66592_XTAL12          0x0000         /* 12MHz */
  21 #define M66592_XCKE             0x2000  /* b13: External clock enable */
  22 #define M66592_RCKE             0x1000  /* b12: Register clock enable */
  23 #define M66592_PLLC             0x0800  /* b11: PLL control */
  24 #define M66592_SCKE             0x0400  /* b10: USB clock enable */
  25 #define M66592_ATCKM            0x0100  /* b8: Automatic clock supply */
  26 #define M66592_HSE              0x0080  /* b7: Hi-speed enable */
  27 #define M66592_DCFM             0x0040  /* b6: Controller function select  */
  28 #define M66592_DMRPD            0x0020  /* b5: D- pull down control */
  29 #define M66592_DPRPU            0x0010  /* b4: D+ pull up control */
  30 #define M66592_FSRPC            0x0004  /* b2: Full-speed receiver enable */
  31 #define M66592_PCUT             0x0002  /* b1: Low power sleep enable */
  32 #define M66592_USBE             0x0001  /* b0: USB module operation enable */
  33 
  34 #define M66592_SYSSTS           0x02
  35 #define M66592_LNST             0x0003  /* b1-0: D+, D- line status */
  36 #define   M66592_SE1             0x0003         /* SE1 */
  37 #define   M66592_KSTS            0x0002         /* K State */
  38 #define   M66592_JSTS            0x0001         /* J State */
  39 #define   M66592_SE0             0x0000         /* SE0 */
  40 
  41 #define M66592_DVSTCTR          0x04
  42 #define M66592_WKUP             0x0100  /* b8: Remote wakeup */
  43 #define M66592_RWUPE            0x0080  /* b7: Remote wakeup sense */
  44 #define M66592_USBRST           0x0040  /* b6: USB reset enable */
  45 #define M66592_RESUME           0x0020  /* b5: Resume enable */
  46 #define M66592_UACT             0x0010  /* b4: USB bus enable */
  47 #define M66592_RHST             0x0003  /* b1-0: Reset handshake status */
  48 #define   M66592_HSMODE          0x0003         /* Hi-Speed mode */
  49 #define   M66592_FSMODE          0x0002         /* Full-Speed mode */
  50 #define   M66592_HSPROC          0x0001         /* HS handshake is processing */
  51 
  52 #define M66592_TESTMODE         0x06
  53 #define M66592_UTST             0x000F  /* b4-0: Test select */
  54 #define   M66592_H_TST_PACKET    0x000C         /* HOST TEST Packet */
  55 #define   M66592_H_TST_SE0_NAK   0x000B         /* HOST TEST SE0 NAK */
  56 #define   M66592_H_TST_K         0x000A         /* HOST TEST K */
  57 #define   M66592_H_TST_J         0x0009         /* HOST TEST J */
  58 #define   M66592_H_TST_NORMAL    0x0000         /* HOST Normal Mode */
  59 #define   M66592_P_TST_PACKET    0x0004         /* PERI TEST Packet */
  60 #define   M66592_P_TST_SE0_NAK   0x0003         /* PERI TEST SE0 NAK */
  61 #define   M66592_P_TST_K         0x0002         /* PERI TEST K */
  62 #define   M66592_P_TST_J         0x0001         /* PERI TEST J */
  63 #define   M66592_P_TST_NORMAL    0x0000         /* PERI Normal Mode */
  64 
  65 /* built-in registers */
  66 #define M66592_CFBCFG           0x0A
  67 #define M66592_D0FBCFG          0x0C
  68 #define M66592_LITTLE           0x0100  /* b8: Little endian mode */
  69 /* external chip case */
  70 #define M66592_PINCFG           0x0A
  71 #define M66592_LDRV             0x8000  /* b15: Drive Current Adjust */
  72 #define M66592_BIGEND           0x0100  /* b8: Big endian mode */
  73 
  74 #define M66592_DMA0CFG          0x0C
  75 #define M66592_DMA1CFG          0x0E
  76 #define M66592_DREQA            0x4000  /* b14: Dreq active select */
  77 #define M66592_BURST            0x2000  /* b13: Burst mode */
  78 #define M66592_DACKA            0x0400  /* b10: Dack active select */
  79 #define M66592_DFORM            0x0380  /* b9-7: DMA mode select */
  80 #define   M66592_CPU_ADR_RD_WR   0x0000   /* Address + RD/WR mode (CPU bus) */
  81 #define   M66592_CPU_DACK_RD_WR  0x0100   /* DACK + RD/WR mode (CPU bus) */
  82 #define   M66592_CPU_DACK_ONLY   0x0180   /* DACK only mode (CPU bus) */
  83 #define   M66592_SPLIT_DACK_ONLY 0x0200   /* DACK only mode (SPLIT bus) */
  84 #define   M66592_SPLIT_DACK_DSTB 0x0300   /* DACK + DSTB0 mode (SPLIT bus) */
  85 #define M66592_DENDA            0x0040  /* b6: Dend active select */
  86 #define M66592_PKTM             0x0020  /* b5: Packet mode */
  87 #define M66592_DENDE            0x0010  /* b4: Dend enable */
  88 #define M66592_OBUS             0x0004  /* b2: OUTbus mode */
  89 
  90 /* common case */
  91 #define M66592_CFIFO            0x10
  92 #define M66592_D0FIFO           0x14
  93 #define M66592_D1FIFO           0x18
  94 
  95 #define M66592_CFIFOSEL         0x1E
  96 #define M66592_D0FIFOSEL        0x24
  97 #define M66592_D1FIFOSEL        0x2A
  98 #define M66592_RCNT             0x8000  /* b15: Read count mode */
  99 #define M66592_REW              0x4000  /* b14: Buffer rewind */
 100 #define M66592_DCLRM            0x2000  /* b13: DMA buffer clear mode */
 101 #define M66592_DREQE            0x1000  /* b12: DREQ output enable */
 102 #define M66592_MBW_8            0x0000   /*  8bit */
 103 #define M66592_MBW_16           0x0400   /* 16bit */
 104 #define M66592_MBW_32           0x0800   /* 32bit */
 105 #define M66592_TRENB            0x0200  /* b9: Transaction counter enable */
 106 #define M66592_TRCLR            0x0100  /* b8: Transaction counter clear */
 107 #define M66592_DEZPM            0x0080  /* b7: Zero-length packet mode */
 108 #define M66592_ISEL             0x0020  /* b5: DCP FIFO port direction select */
 109 #define M66592_CURPIPE          0x0007  /* b2-0: PIPE select */
 110 
 111 #define M66592_CFIFOCTR         0x20
 112 #define M66592_D0FIFOCTR        0x26
 113 #define M66592_D1FIFOCTR        0x2c
 114 #define M66592_BVAL             0x8000  /* b15: Buffer valid flag */
 115 #define M66592_BCLR             0x4000  /* b14: Buffer clear */
 116 #define M66592_FRDY             0x2000  /* b13: FIFO ready */
 117 #define M66592_DTLN             0x0FFF  /* b11-0: FIFO received data length */
 118 
 119 #define M66592_CFIFOSIE         0x22
 120 #define M66592_TGL              0x8000  /* b15: Buffer toggle */
 121 #define M66592_SCLR             0x4000  /* b14: Buffer clear */
 122 #define M66592_SBUSY            0x2000  /* b13: SIE_FIFO busy */
 123 
 124 #define M66592_D0FIFOTRN        0x28
 125 #define M66592_D1FIFOTRN        0x2E
 126 #define M66592_TRNCNT           0xFFFF  /* b15-0: Transaction counter */
 127 
 128 #define M66592_INTENB0  0x30
 129 #define M66592_VBSE     0x8000  /* b15: VBUS interrupt */
 130 #define M66592_RSME     0x4000  /* b14: Resume interrupt */
 131 #define M66592_SOFE     0x2000  /* b13: Frame update interrupt */
 132 #define M66592_DVSE     0x1000  /* b12: Device state transition interrupt */
 133 #define M66592_CTRE     0x0800  /* b11: Control transfer stage transition irq */
 134 #define M66592_BEMPE    0x0400  /* b10: Buffer empty interrupt */
 135 #define M66592_NRDYE    0x0200  /* b9: Buffer not ready interrupt */
 136 #define M66592_BRDYE    0x0100  /* b8: Buffer ready interrupt */
 137 #define M66592_URST     0x0080  /* b7: USB reset detected interrupt */
 138 #define M66592_SADR     0x0040  /* b6: Set address executed interrupt */
 139 #define M66592_SCFG     0x0020  /* b5: Set configuration executed interrupt */
 140 #define M66592_SUSP     0x0010  /* b4: Suspend detected interrupt */
 141 #define M66592_WDST     0x0008  /* b3: Control write data stage completed irq */
 142 #define M66592_RDST     0x0004  /* b2: Control read data stage completed irq */
 143 #define M66592_CMPL     0x0002  /* b1: Control transfer complete interrupt */
 144 #define M66592_SERR     0x0001  /* b0: Sequence error interrupt */
 145 
 146 #define M66592_INTENB1  0x32
 147 #define M66592_BCHGE    0x4000  /* b14: USB us chenge interrupt */
 148 #define M66592_DTCHE    0x1000  /* b12: Detach sense interrupt */
 149 #define M66592_SIGNE    0x0020  /* b5: SETUP IGNORE interrupt */
 150 #define M66592_SACKE    0x0010  /* b4: SETUP ACK interrupt */
 151 #define M66592_BRDYM    0x0004  /* b2: BRDY clear timing */
 152 #define M66592_INTL     0x0002  /* b1: Interrupt sense select */
 153 #define M66592_PCSE     0x0001  /* b0: PCUT enable by CS assert */
 154 
 155 #define M66592_BRDYENB          0x36
 156 #define M66592_BRDYSTS          0x46
 157 #define M66592_BRDY7            0x0080  /* b7: PIPE7 */
 158 #define M66592_BRDY6            0x0040  /* b6: PIPE6 */
 159 #define M66592_BRDY5            0x0020  /* b5: PIPE5 */
 160 #define M66592_BRDY4            0x0010  /* b4: PIPE4 */
 161 #define M66592_BRDY3            0x0008  /* b3: PIPE3 */
 162 #define M66592_BRDY2            0x0004  /* b2: PIPE2 */
 163 #define M66592_BRDY1            0x0002  /* b1: PIPE1 */
 164 #define M66592_BRDY0            0x0001  /* b1: PIPE0 */
 165 
 166 #define M66592_NRDYENB          0x38
 167 #define M66592_NRDYSTS          0x48
 168 #define M66592_NRDY7            0x0080  /* b7: PIPE7 */
 169 #define M66592_NRDY6            0x0040  /* b6: PIPE6 */
 170 #define M66592_NRDY5            0x0020  /* b5: PIPE5 */
 171 #define M66592_NRDY4            0x0010  /* b4: PIPE4 */
 172 #define M66592_NRDY3            0x0008  /* b3: PIPE3 */
 173 #define M66592_NRDY2            0x0004  /* b2: PIPE2 */
 174 #define M66592_NRDY1            0x0002  /* b1: PIPE1 */
 175 #define M66592_NRDY0            0x0001  /* b1: PIPE0 */
 176 
 177 #define M66592_BEMPENB          0x3A
 178 #define M66592_BEMPSTS          0x4A
 179 #define M66592_BEMP7            0x0080  /* b7: PIPE7 */
 180 #define M66592_BEMP6            0x0040  /* b6: PIPE6 */
 181 #define M66592_BEMP5            0x0020  /* b5: PIPE5 */
 182 #define M66592_BEMP4            0x0010  /* b4: PIPE4 */
 183 #define M66592_BEMP3            0x0008  /* b3: PIPE3 */
 184 #define M66592_BEMP2            0x0004  /* b2: PIPE2 */
 185 #define M66592_BEMP1            0x0002  /* b1: PIPE1 */
 186 #define M66592_BEMP0            0x0001  /* b0: PIPE0 */
 187 
 188 #define M66592_SOFCFG           0x3C
 189 #define M66592_SOFM             0x000C  /* b3-2: SOF palse mode */
 190 #define   M66592_SOF_125US       0x0008   /* SOF OUT 125us uFrame Signal */
 191 #define   M66592_SOF_1MS         0x0004   /* SOF OUT 1ms Frame Signal */
 192 #define   M66592_SOF_DISABLE     0x0000   /* SOF OUT Disable */
 193 
 194 #define M66592_INTSTS0          0x40
 195 #define M66592_VBINT            0x8000  /* b15: VBUS interrupt */
 196 #define M66592_RESM             0x4000  /* b14: Resume interrupt */
 197 #define M66592_SOFR             0x2000  /* b13: SOF frame update interrupt */
 198 #define M66592_DVST             0x1000  /* b12: Device state transition */
 199 #define M66592_CTRT             0x0800  /* b11: Control stage transition */
 200 #define M66592_BEMP             0x0400  /* b10: Buffer empty interrupt */
 201 #define M66592_NRDY             0x0200  /* b9: Buffer not ready interrupt */
 202 #define M66592_BRDY             0x0100  /* b8: Buffer ready interrupt */
 203 #define M66592_VBSTS            0x0080  /* b7: VBUS input port */
 204 #define M66592_DVSQ             0x0070  /* b6-4: Device state */
 205 #define   M66592_DS_SPD_CNFG     0x0070    /* Suspend Configured */
 206 #define   M66592_DS_SPD_ADDR     0x0060    /* Suspend Address */
 207 #define   M66592_DS_SPD_DFLT     0x0050    /* Suspend Default */
 208 #define   M66592_DS_SPD_POWR     0x0040    /* Suspend Powered */
 209 #define   M66592_DS_SUSP         0x0040    /* Suspend */
 210 #define   M66592_DS_CNFG         0x0030    /* Configured */
 211 #define   M66592_DS_ADDS         0x0020    /* Address */
 212 #define   M66592_DS_DFLT         0x0010    /* Default */
 213 #define   M66592_DS_POWR         0x0000    /* Powered */
 214 #define M66592_DVSQS            0x0030  /* b5-4: Device state */
 215 #define M66592_VALID            0x0008  /* b3: Setup packet detected flag */
 216 #define M66592_CTSQ             0x0007  /* b2-0: Control transfer stage */
 217 #define   M66592_CS_SQER         0x0006   /* Sequence error */
 218 #define   M66592_CS_WRND         0x0005   /* Control write nodata status */
 219 #define   M66592_CS_WRSS         0x0004   /* Control write status stage */
 220 #define   M66592_CS_WRDS         0x0003   /* Control write data stage */
 221 #define   M66592_CS_RDSS         0x0002   /* Control read status stage */
 222 #define   M66592_CS_RDDS         0x0001   /* Control read data stage */
 223 #define   M66592_CS_IDST         0x0000   /* Idle or setup stage */
 224 
 225 #define M66592_INTSTS1          0x42
 226 #define M66592_BCHG             0x4000  /* b14: USB bus chenge interrupt */
 227 #define M66592_DTCH             0x1000  /* b12: Detach sense interrupt */
 228 #define M66592_SIGN             0x0020  /* b5: SETUP IGNORE interrupt */
 229 #define M66592_SACK             0x0010  /* b4: SETUP ACK interrupt */
 230 
 231 #define M66592_FRMNUM           0x4C
 232 #define M66592_OVRN             0x8000  /* b15: Overrun error */
 233 #define M66592_CRCE             0x4000  /* b14: Received data error */
 234 #define M66592_SOFRM            0x0800  /* b11: SOF output mode */
 235 #define M66592_FRNM             0x07FF  /* b10-0: Frame number */
 236 
 237 #define M66592_UFRMNUM          0x4E
 238 #define M66592_UFRNM            0x0007  /* b2-0: Micro frame number */
 239 
 240 #define M66592_RECOVER          0x50
 241 #define M66592_STSRECOV         0x0700  /* Status recovery */
 242 #define   M66592_STSR_HI         0x0400           /* FULL(0) or HI(1) Speed */
 243 #define   M66592_STSR_DEFAULT    0x0100           /* Default state */
 244 #define   M66592_STSR_ADDRESS    0x0200           /* Address state */
 245 #define   M66592_STSR_CONFIG     0x0300           /* Configured state */
 246 #define M66592_USBADDR          0x007F  /* b6-0: USB address */
 247 
 248 #define M66592_USBREQ                   0x54
 249 #define M66592_bRequest                 0xFF00  /* b15-8: bRequest */
 250 #define   M66592_GET_STATUS              0x0000
 251 #define   M66592_CLEAR_FEATURE           0x0100
 252 #define   M66592_ReqRESERVED             0x0200
 253 #define   M66592_SET_FEATURE             0x0300
 254 #define   M66592_ReqRESERVED1            0x0400
 255 #define   M66592_SET_ADDRESS             0x0500
 256 #define   M66592_GET_DESCRIPTOR          0x0600
 257 #define   M66592_SET_DESCRIPTOR          0x0700
 258 #define   M66592_GET_CONFIGURATION       0x0800
 259 #define   M66592_SET_CONFIGURATION       0x0900
 260 #define   M66592_GET_INTERFACE           0x0A00
 261 #define   M66592_SET_INTERFACE           0x0B00
 262 #define   M66592_SYNCH_FRAME             0x0C00
 263 #define M66592_bmRequestType            0x00FF  /* b7-0: bmRequestType */
 264 #define M66592_bmRequestTypeDir         0x0080  /* b7  : Data direction */
 265 #define   M66592_HOST_TO_DEVICE          0x0000
 266 #define   M66592_DEVICE_TO_HOST          0x0080
 267 #define M66592_bmRequestTypeType        0x0060  /* b6-5: Type */
 268 #define   M66592_STANDARD                0x0000
 269 #define   M66592_CLASS                   0x0020
 270 #define   M66592_VENDOR                  0x0040
 271 #define M66592_bmRequestTypeRecip       0x001F  /* b4-0: Recipient */
 272 #define   M66592_DEVICE                  0x0000
 273 #define   M66592_INTERFACE               0x0001
 274 #define   M66592_ENDPOINT                0x0002
 275 
 276 #define M66592_USBVAL                           0x56
 277 #define M66592_wValue                           0xFFFF  /* b15-0: wValue */
 278 /* Standard Feature Selector */
 279 #define   M66592_ENDPOINT_HALT                  0x0000
 280 #define   M66592_DEVICE_REMOTE_WAKEUP           0x0001
 281 #define   M66592_TEST_MODE                      0x0002
 282 /* Descriptor Types */
 283 #define M66592_DT_TYPE                          0xFF00
 284 #define M66592_GET_DT_TYPE(v)                   (((v) & DT_TYPE) >> 8)
 285 #define   M66592_DT_DEVICE                      0x01
 286 #define   M66592_DT_CONFIGURATION               0x02
 287 #define   M66592_DT_STRING                      0x03
 288 #define   M66592_DT_INTERFACE                   0x04
 289 #define   M66592_DT_ENDPOINT                    0x05
 290 #define   M66592_DT_DEVICE_QUALIFIER            0x06
 291 #define   M66592_DT_OTHER_SPEED_CONFIGURATION   0x07
 292 #define   M66592_DT_INTERFACE_POWER             0x08
 293 #define M66592_DT_INDEX                         0x00FF
 294 #define M66592_CONF_NUM                         0x00FF
 295 #define M66592_ALT_SET                          0x00FF
 296 
 297 #define M66592_USBINDEX                 0x58
 298 #define M66592_wIndex                   0xFFFF  /* b15-0: wIndex */
 299 #define M66592_TEST_SELECT              0xFF00  /* b15-b8: Test Mode */
 300 #define   M66592_TEST_J                  0x0100   /* Test_J */
 301 #define   M66592_TEST_K                  0x0200   /* Test_K */
 302 #define   M66592_TEST_SE0_NAK            0x0300   /* Test_SE0_NAK */
 303 #define   M66592_TEST_PACKET             0x0400   /* Test_Packet */
 304 #define   M66592_TEST_FORCE_ENABLE       0x0500   /* Test_Force_Enable */
 305 #define   M66592_TEST_STSelectors        0x0600   /* Standard test selectors */
 306 #define   M66592_TEST_Reserved           0x4000   /* Reserved */
 307 #define   M66592_TEST_VSTModes           0xC000   /* Vendor-specific tests */
 308 #define M66592_EP_DIR                   0x0080  /* b7: Endpoint Direction */
 309 #define   M66592_EP_DIR_IN               0x0080
 310 #define   M66592_EP_DIR_OUT              0x0000
 311 
 312 #define M66592_USBLENG          0x5A
 313 #define M66592_wLength          0xFFFF  /* b15-0: wLength */
 314 
 315 #define M66592_DCPCFG           0x5C
 316 #define M66592_CNTMD            0x0100  /* b8: Continuous transfer mode */
 317 #define M66592_DIR              0x0010  /* b4: Control transfer DIR select */
 318 
 319 #define M66592_DCPMAXP          0x5E
 320 #define M66592_DEVSEL           0xC000  /* b15-14: Device address select */
 321 #define   M66592_DEVICE_0        0x0000           /* Device address 0 */
 322 #define   M66592_DEVICE_1        0x4000           /* Device address 1 */
 323 #define   M66592_DEVICE_2        0x8000           /* Device address 2 */
 324 #define   M66592_DEVICE_3        0xC000           /* Device address 3 */
 325 #define M66592_MAXP             0x007F  /* b6-0: Maxpacket size of ep0 */
 326 
 327 #define M66592_DCPCTR           0x60
 328 #define M66592_BSTS             0x8000  /* b15: Buffer status */
 329 #define M66592_SUREQ            0x4000  /* b14: Send USB request  */
 330 #define M66592_SQCLR            0x0100  /* b8: Sequence toggle bit clear */
 331 #define M66592_SQSET            0x0080  /* b7: Sequence toggle bit set */
 332 #define M66592_SQMON            0x0040  /* b6: Sequence toggle bit monitor */
 333 #define M66592_CCPL             0x0004  /* b2: control transfer complete */
 334 #define M66592_PID              0x0003  /* b1-0: Response PID */
 335 #define   M66592_PID_STALL       0x0002           /* STALL */
 336 #define   M66592_PID_BUF         0x0001           /* BUF */
 337 #define   M66592_PID_NAK         0x0000           /* NAK */
 338 
 339 #define M66592_PIPESEL          0x64
 340 #define M66592_PIPENM           0x0007  /* b2-0: Pipe select */
 341 #define   M66592_PIPE0           0x0000           /* PIPE 0 */
 342 #define   M66592_PIPE1           0x0001           /* PIPE 1 */
 343 #define   M66592_PIPE2           0x0002           /* PIPE 2 */
 344 #define   M66592_PIPE3           0x0003           /* PIPE 3 */
 345 #define   M66592_PIPE4           0x0004           /* PIPE 4 */
 346 #define   M66592_PIPE5           0x0005           /* PIPE 5 */
 347 #define   M66592_PIPE6           0x0006           /* PIPE 6 */
 348 #define   M66592_PIPE7           0x0007           /* PIPE 7 */
 349 
 350 #define M66592_PIPECFG          0x66
 351 #define M66592_TYP              0xC000  /* b15-14: Transfer type */
 352 #define   M66592_ISO             0xC000           /* Isochronous */
 353 #define   M66592_INT             0x8000           /* Interrupt */
 354 #define   M66592_BULK            0x4000           /* Bulk */
 355 #define M66592_BFRE             0x0400  /* b10: Buffer ready interrupt mode */
 356 #define M66592_DBLB             0x0200  /* b9: Double buffer mode select */
 357 #define M66592_CNTMD            0x0100  /* b8: Continuous transfer mode */
 358 #define M66592_SHTNAK           0x0080  /* b7: Transfer end NAK */
 359 #define M66592_DIR              0x0010  /* b4: Transfer direction select */
 360 #define   M66592_DIR_H_OUT       0x0010           /* HOST OUT */
 361 #define   M66592_DIR_P_IN        0x0010           /* PERI IN */
 362 #define   M66592_DIR_H_IN        0x0000           /* HOST IN */
 363 #define   M66592_DIR_P_OUT       0x0000           /* PERI OUT */
 364 #define M66592_EPNUM            0x000F  /* b3-0: Eendpoint number select */
 365 #define   M66592_EP1             0x0001
 366 #define   M66592_EP2             0x0002
 367 #define   M66592_EP3             0x0003
 368 #define   M66592_EP4             0x0004
 369 #define   M66592_EP5             0x0005
 370 #define   M66592_EP6             0x0006
 371 #define   M66592_EP7             0x0007
 372 #define   M66592_EP8             0x0008
 373 #define   M66592_EP9             0x0009
 374 #define   M66592_EP10            0x000A
 375 #define   M66592_EP11            0x000B
 376 #define   M66592_EP12            0x000C
 377 #define   M66592_EP13            0x000D
 378 #define   M66592_EP14            0x000E
 379 #define   M66592_EP15            0x000F
 380 
 381 #define M66592_PIPEBUF          0x68
 382 #define M66592_BUFSIZE          0x7C00  /* b14-10: Pipe buffer size */
 383 #define M66592_BUF_SIZE(x)      ((((x) / 64) - 1) << 10)
 384 #define M66592_BUFNMB           0x00FF  /* b7-0: Pipe buffer number */
 385 
 386 #define M66592_PIPEMAXP         0x6A
 387 #define M66592_MXPS             0x07FF  /* b10-0: Maxpacket size */
 388 
 389 #define M66592_PIPEPERI         0x6C
 390 #define M66592_IFIS             0x1000  /* b12: ISO in-buffer flush mode */
 391 #define M66592_IITV             0x0007  /* b2-0: ISO interval */
 392 
 393 #define M66592_PIPE1CTR         0x70
 394 #define M66592_PIPE2CTR         0x72
 395 #define M66592_PIPE3CTR         0x74
 396 #define M66592_PIPE4CTR         0x76
 397 #define M66592_PIPE5CTR         0x78
 398 #define M66592_PIPE6CTR         0x7A
 399 #define M66592_PIPE7CTR         0x7C
 400 #define M66592_BSTS             0x8000  /* b15: Buffer status */
 401 #define M66592_INBUFM           0x4000  /* b14: IN buffer monitor (PIPE 1-5) */
 402 #define M66592_ACLRM            0x0200  /* b9: Out buffer auto clear mode */
 403 #define M66592_SQCLR            0x0100  /* b8: Sequence toggle bit clear */
 404 #define M66592_SQSET            0x0080  /* b7: Sequence toggle bit set */
 405 #define M66592_SQMON            0x0040  /* b6: Sequence toggle bit monitor */
 406 #define M66592_PID              0x0003  /* b1-0: Response PID */
 407 
 408 #define M66592_INVALID_REG      0x7E
 409 
 410 
 411 #define get_pipectr_addr(pipenum)       (M66592_PIPE1CTR + (pipenum - 1) * 2)
 412 
 413 #define M66592_MAX_SAMPLING     10
 414 
 415 #define M66592_MAX_NUM_PIPE     8
 416 #define M66592_MAX_NUM_BULK     3
 417 #define M66592_MAX_NUM_ISOC     2
 418 #define M66592_MAX_NUM_INT      2
 419 
 420 #define M66592_BASE_PIPENUM_BULK        3
 421 #define M66592_BASE_PIPENUM_ISOC        1
 422 #define M66592_BASE_PIPENUM_INT         6
 423 
 424 #define M66592_BASE_BUFNUM      6
 425 #define M66592_MAX_BUFNUM       0x4F
 426 
 427 struct m66592_pipe_info {
 428         u16     pipe;
 429         u16     epnum;
 430         u16     maxpacket;
 431         u16     type;
 432         u16     interval;
 433         u16     dir_in;
 434 };
 435 
 436 struct m66592_request {
 437         struct usb_request      req;
 438         struct list_head        queue;
 439 };
 440 
 441 struct m66592_ep {
 442         struct usb_ep           ep;
 443         struct m66592           *m66592;
 444 
 445         struct list_head        queue;
 446         unsigned                busy:1;
 447         unsigned                internal_ccpl:1;        /* use only control */
 448 
 449         /* this member can able to after m66592_enable */
 450         unsigned                use_dma:1;
 451         u16                     pipenum;
 452         u16                     type;
 453 
 454         /* register address */
 455         unsigned long           fifoaddr;
 456         unsigned long           fifosel;
 457         unsigned long           fifoctr;
 458         unsigned long           fifotrn;
 459         unsigned long           pipectr;
 460 };
 461 
 462 struct m66592 {
 463         spinlock_t              lock;
 464         void __iomem            *reg;
 465         struct clk *clk;
 466         struct m66592_platdata  *pdata;
 467         unsigned long           irq_trigger;
 468 
 469         struct usb_gadget               gadget;
 470         struct usb_gadget_driver        *driver;
 471 
 472         struct m66592_ep        ep[M66592_MAX_NUM_PIPE];
 473         struct m66592_ep        *pipenum2ep[M66592_MAX_NUM_PIPE];
 474         struct m66592_ep        *epaddr2ep[16];
 475 
 476         struct usb_request      *ep0_req;       /* for internal request */
 477         __le16                  ep0_data;       /* for internal request */
 478         u16                     old_vbus;
 479 
 480         struct timer_list       timer;
 481 
 482         int                     scount;
 483 
 484         int                     old_dvsq;
 485 
 486         /* pipe config */
 487         int bulk;
 488         int interrupt;
 489         int isochronous;
 490         int num_dma;
 491 };
 492 #define to_m66592(g)    (container_of((g), struct m66592, gadget))
 493 
 494 #define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
 495 #define m66592_to_gadget(m66592) (&m66592->gadget)
 496 
 497 #define is_bulk_pipe(pipenum)   \
 498         ((pipenum >= M66592_BASE_PIPENUM_BULK) && \
 499          (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK)))
 500 #define is_interrupt_pipe(pipenum)      \
 501         ((pipenum >= M66592_BASE_PIPENUM_INT) && \
 502          (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT)))
 503 #define is_isoc_pipe(pipenum)   \
 504         ((pipenum >= M66592_BASE_PIPENUM_ISOC) && \
 505          (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC)))
 506 
 507 #define enable_irq_ready(m66592, pipenum)       \
 508         enable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
 509 #define disable_irq_ready(m66592, pipenum)      \
 510         disable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
 511 #define enable_irq_empty(m66592, pipenum)       \
 512         enable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
 513 #define disable_irq_empty(m66592, pipenum)      \
 514         disable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
 515 #define enable_irq_nrdy(m66592, pipenum)        \
 516         enable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
 517 #define disable_irq_nrdy(m66592, pipenum)       \
 518         disable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
 519 
 520 /*-------------------------------------------------------------------------*/
 521 static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
 522 {
 523         return ioread16(m66592->reg + offset);
 524 }
 525 
 526 static inline void m66592_read_fifo(struct m66592 *m66592,
 527                 unsigned long offset,
 528                 void *buf, unsigned long len)
 529 {
 530         void __iomem *fifoaddr = m66592->reg + offset;
 531 
 532         if (m66592->pdata->on_chip) {
 533                 len = (len + 3) / 4;
 534                 ioread32_rep(fifoaddr, buf, len);
 535         } else {
 536                 len = (len + 1) / 2;
 537                 ioread16_rep(fifoaddr, buf, len);
 538         }
 539 }
 540 
 541 static inline void m66592_write(struct m66592 *m66592, u16 val,
 542                                 unsigned long offset)
 543 {
 544         iowrite16(val, m66592->reg + offset);
 545 }
 546 
 547 static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
 548                 unsigned long offset)
 549 {
 550         u16 tmp;
 551         tmp = m66592_read(m66592, offset);
 552         tmp = tmp & (~pat);
 553         tmp = tmp | val;
 554         m66592_write(m66592, tmp, offset);
 555 }
 556 
 557 #define m66592_bclr(m66592, val, offset)        \
 558                         m66592_mdfy(m66592, 0, val, offset)
 559 #define m66592_bset(m66592, val, offset)        \
 560                         m66592_mdfy(m66592, val, 0, offset)
 561 
 562 static inline void m66592_write_fifo(struct m66592 *m66592,
 563                 struct m66592_ep *ep,
 564                 void *buf, unsigned long len)
 565 {
 566         void __iomem *fifoaddr = m66592->reg + ep->fifoaddr;
 567 
 568         if (m66592->pdata->on_chip) {
 569                 unsigned long count;
 570                 unsigned char *pb;
 571                 int i;
 572 
 573                 count = len / 4;
 574                 iowrite32_rep(fifoaddr, buf, count);
 575 
 576                 if (len & 0x00000003) {
 577                         pb = buf + count * 4;
 578                         for (i = 0; i < (len & 0x00000003); i++) {
 579                                 if (m66592_read(m66592, M66592_CFBCFG)) /* le */
 580                                         iowrite8(pb[i], fifoaddr + (3 - i));
 581                                 else
 582                                         iowrite8(pb[i], fifoaddr + i);
 583                         }
 584                 }
 585         } else {
 586                 unsigned long odd = len & 0x0001;
 587 
 588                 len = len / 2;
 589                 iowrite16_rep(fifoaddr, buf, len);
 590                 if (odd) {
 591                         unsigned char *p = buf + len*2;
 592                         if (m66592->pdata->wr0_shorted_to_wr1)
 593                                 m66592_bclr(m66592, M66592_MBW_16, ep->fifosel);
 594                         iowrite8(*p, fifoaddr);
 595                         if (m66592->pdata->wr0_shorted_to_wr1)
 596                                 m66592_bset(m66592, M66592_MBW_16, ep->fifosel);
 597                 }
 598         }
 599 }
 600 
 601 #endif  /* ifndef __M66592_UDC_H__ */
 602 
 603
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